KR20060118783A - Method for forming fuse box of semiconductor devices - Google Patents

Method for forming fuse box of semiconductor devices Download PDF

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KR20060118783A
KR20060118783A KR1020050041126A KR20050041126A KR20060118783A KR 20060118783 A KR20060118783 A KR 20060118783A KR 1020050041126 A KR1020050041126 A KR 1020050041126A KR 20050041126 A KR20050041126 A KR 20050041126A KR 20060118783 A KR20060118783 A KR 20060118783A
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fuse box
buffer layer
fuse
forming
interlayer insulating
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KR1020050041126A
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Korean (ko)
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KR100702301B1 (en
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구본성
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive

Abstract

A method for forming a fuse box of a semiconductor device is provided to prevent cracks of a fuse due to stress by using buffer layers between a metal wire and a fuse box. A first interlayer dielectric(33) is formed on a semiconductor where a fuse(31) is formed. A first metal wire(35) and a first buffer layer are formed on an upper portion of the first interlayer dielectric. The first buffer layer is formed between the first metal wire and a fuse box. A second interlayer dielectric(39) is formed on an upper portion of the whole surface. A second metal wire(43) is formed to be contacted to the first metal wire, and, simultaneously, a second buffer layer(45) is formed. The second buffer layer is formed between the second metal wire and the fuse box. A third interlayer dielectric(47) is formed on an upper portion of the whole surface. The third, second, and first interlayer dielectrics are etched to form the fuse box and expose the first and the second buffer layers.

Description

반도체소자의 퓨즈박스 형성방법{Method for forming fuse box of semiconductor devices}Method for forming fuse box of semiconductor devices

도 1a 및 도 1b 는 종래기술에 따라 형성된 반도체소자의 퓨즈박스를 도시한 평면도 및 단면도.1A and 1B are a plan view and a sectional view of a fuse box of a semiconductor device formed according to the prior art;

도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 퓨즈박스 형성방법을 도시한 평면도 및 단면도.2A and 2B are plan and cross-sectional views illustrating a method of forming a fuse box of a semiconductor device in accordance with an embodiment of the present invention.

본 발명은 반도체소자의 퓨즈박스 형성방법에 관한 것으로, 특히 퓨즈 블로잉 ( fuse blowing ) 을 통한 리페어 공정을 위하여 퓨즈박스를 형성할 때 상기 퓨즈박스의 에지부에서 유발되는 크랙을 방지할 수 있도록 하는 방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a fuse box of a semiconductor device, and in particular, a method for preventing cracks caused at an edge portion of a fuse box when a fuse box is formed for a repair process through fuse blowing. It is about.

일반적으로, 리페어 공정은 프리 리페어 테스트 ( pre repair test ), 리페어 ( Repair ), 기존 및 포스트 리페어 테스트 ( post repair test ) 등으로 진행한다. In general, the repair process includes a pre repair test, a repair, a conventional and post repair test, and the like.

상기 프리 리페어 테스트 ( pre repair test ) 공정시 페일이 발생하는 메인 셀에 대하여 퓨즈 세트의 퓨즈 블로잉을 통해 페일이 발생한 메인 셀의 어드레스를 리던던시 셀 ( redundancy cell ) 로 대체하게 된다. In the pre repair test process, an address of a main cell in which a fail occurs is replaced with a redundancy cell through fuse blowing of a fuse set for a main cell in which a fail occurs.

셀 효율성을 향상시키기 위하여 더미 퓨즈 ( dummy fuse ) 와 인에이블 퓨즈 ( enable fuse ) 를 사용하지 않는 방법을 이용하면서 로우 어드레스 ( row address ( X-Address ))를 코딩된 퓨즈 형태로 대체되도록 하는 방법을 이용하고 있다. In order to improve cell efficiency, row address (X-Address) can be replaced by coded fuse while using dummy and enable fuse. I use it.

도 1a 및 도 1b 는 종래기술에 따라 형성된 반도체소자의 퓨즈박스를 도시한 평면도 및 단면도이다. 1A and 1B are a plan view and a cross-sectional view illustrating a fuse box of a semiconductor device formed according to the prior art.

도 1a 및 도 1b를 참조하면, 하부구조물이 형성된 반도체기판(미도시) 상의 소정 영역에 다수의 퓨즈(11)를 패터닝한다. 1A and 1B, a plurality of fuses 11 are patterned in predetermined regions on a semiconductor substrate (not shown) on which a lower structure is formed.

이때, 상기 퓨즈(11)는 셀부의 캐패시터 형성공정시 형성되는 플레이트전극(미도시) 형성공정시 증착하고 후속 패터닝 공정으로 형성한 것으로, 다수의 퓨즈가 라인/스페이스 형태로 형성된 것이다. In this case, the fuse 11 is formed during the plate electrode (not shown) forming process formed during the capacitor forming process of the cell unit and formed by a subsequent patterning process, and a plurality of fuses are formed in a line / space form.

그 다음, 전체표면상부에 제1층간절연막(13)을 형성하고 이를 통한 비아콘택플러그(15)로 상기 퓨즈(11)에 접속되는 제1금속배선(17)을 형성한다. Next, a first interlayer insulating film 13 is formed on the entire surface, and a first metal wiring 17 connected to the fuse 11 is formed by via contact plugs 15 therethrough.

그리고, 전체표면상부에 제2층간절연막(19)을 형성한다. 이때, 상기 제2층간절연막(19)은 상기 제1금속배선(17) 상부를 완전히 도포할 수 있는 두께로 증착하여 형성한 것이다. Then, a second interlayer insulating film 19 is formed over the entire surface. In this case, the second interlayer insulating film 19 is formed by depositing a thickness to completely coat the upper portion of the first metal wiring 17.

그 다음 상기 제1금속배선(17)에 제2금속배선(23)을 콘택시키기 위한 비아 콘택 플러그(21)를 형성한다. Next, via contact plugs 21 are formed on the first metal wires 17 to contact the second metal wires 23.

이때, 상기 비아콘택플러그(21)는 비아콘택마스크를 이용한 사진식각공정으 로 상기 제2층간절연막(19)을 식각하여 형성한 것이다. In this case, the via contact plug 21 is formed by etching the second interlayer insulating layer 19 by a photolithography process using a via contact mask.

그 다음, 상기 제2비아콘택플러그(21)에 접속되는 제2금속배선(23)을 형성함으로써 상기 퓨즈(11)의 바깥쪽을 완전히 감싸는 가아드링 ( guard ring )을 형성한다. Next, by forming a second metal wiring 23 connected to the second via contact plug 21, a guard ring is formed to completely surround the outside of the fuse 11.

그리고, 전체표면상부에 제3층간절연막(25)을 형성하고 마스크를 이용한 식각공정으로 상기 퓨즈(11)들이 구비되는 영역인 퓨즈박스 영역 상측의 제3,2,1층간절연막(25,19,15)을 식각하여 퓨즈박스(100)를 형성한다. In addition, the third interlayer insulating film 25 is formed on the entire surface, and the third, second and first interlayer insulating films 25, 19, on the upper side of the fuse box area, which are areas where the fuses 11 are provided, are formed by etching using a mask. 15) is etched to form a fuse box 100.

이때, 상기 제3,2,1층간절연막(25,19,15)의 식각공정은 상기 퓨즈(13) 상측에 소정두께의 제1층간절연막(15)이 남도록 실시한다.At this time, the etching process of the third, second and first interlayer insulating films 25, 19 and 15 is performed such that the first interlayer insulating film 15 having a predetermined thickness remains on the upper side of the fuse 13.

그러나, 상기 퓨즈박스(100) 외측의 적층구조를 이루는 각 층간의 스트레스로 인하여 상기 퓨즈박스(100)의 에지부에 크랙이 ⓧ 와 같이 유발되어 퓨즈가 단선되는 현상이 발생되고 그에 따른 반도체소자의 리페어 공정을 어렵게 하는 문제점이 있다. However, due to the stress between the layers forming the laminated structure on the outside of the fuse box 100, cracks are induced at the edges of the fuse box 100 such that the fuse is disconnected, thereby causing the semiconductor device to break. There is a problem that makes the repair process difficult.

본 발명은 상기한 종래기술에 따른 문제점을 해결하기 위하여, 퓨즈박스 주변의 적층구조에 의한 소자의 특성 열화를 방지하기 위하여 스트레스를 완화시킬 수 있는 버퍼층을 퓨즈박스에 인접된 적층구조에 형성함으로써 소자의 특성 열화를 방지할 수 있도록 하는 반도체소자의 퓨즈박스 형성방법을 제공하는데 그 목적이 있다. The present invention is to solve the problems according to the prior art, by forming a buffer layer in the laminated structure adjacent to the fuse box to alleviate stress in order to prevent deterioration of the characteristics of the device due to the laminated structure around the fuse box It is an object of the present invention to provide a method for forming a fuse box of a semiconductor device to prevent deterioration of the characteristics of the semiconductor device.

이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 퓨즈박스 형성방법은, In order to achieve the above object, a method of forming a fuse box of a semiconductor device according to the present invention includes:

퓨즈가 형성된 반도체기판 상에 제1층간절연막을 형성하고 그 상부에 제1금속배선 및 제1버퍼층을 형성하되, 상기 제1버퍼층은 제1금속배선과 퓨즈박스 사이에 형성되는 공정과,Forming a first interlayer insulating film on the semiconductor substrate on which the fuse is formed and forming a first metal wiring and a first buffer layer thereon, wherein the first buffer layer is formed between the first metal wiring and the fuse box;

전체표면상부에 제2층간절연막을 형성하고 상기 제1금속배선에 콘택되는 제2금속배선을 형성하는 동시에 제2버퍼층을 형성하되, 상기 제2버퍼층은 제2금속배선과 퓨즈박스 사이에 형성되는 공정과,A second interlayer insulating film is formed on the entire surface and a second metal wiring contacting the first metal wiring is formed, and a second buffer layer is formed. The second buffer layer is formed between the second metal wiring and the fuse box. Fair,

전체표면상부에 보호막인 제3층간절연막을 형성하는 공정과,Forming a third interlayer insulating film as a protective film over the entire surface;

상기 제3,2,1층간절연막을 식각하여 상기 제1,2버퍼층이 노출되도록 퓨즈박스를 형성하는 공정을 포함하는 것과,Etching the third, second, and first interlayer insulating films to form a fuse box to expose the first and second buffer layers;

상기 제1버퍼층 및 제2버퍼층은 금속배선과 같은 물질로 구비되는 것과,The first buffer layer and the second buffer layer is provided with a material such as metal wiring,

상기 제1버퍼층 및 제2버퍼층은 연성의 알루미늄으로 구비되는 것을 특징으로 한다. The first buffer layer and the second buffer layer is characterized in that provided with ductile aluminum.

이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다. Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 및 도 2b 는 본 발명의 실시예에 따른 반도체소자의 퓨즈박스 형성방법을 도시한 평면도 및 단면도이다. 2A and 2B are plan and cross-sectional views illustrating a method of forming a fuse box of a semiconductor device according to an exemplary embodiment of the present invention.

도 2a 및 도 2b를 참조하면, 하부구조물이 형성된 반도체기판(미도시) 상의 소정 영역에 다수의 퓨즈(31)를 패터닝한다. 2A and 2B, a plurality of fuses 31 are patterned in predetermined regions on a semiconductor substrate (not shown) on which a lower structure is formed.

이때, 상기 퓨즈(31)는 셀부의 캐패시터 형성공정시 형성되는 플레이트전극( 미도시) 형성공정시 증착하고 후속 패터닝 공정으로 형성한 것으로, 다수의 퓨즈가 라인/스페이스 형태로 형성된 것이다. In this case, the fuse 31 is deposited during the plate electrode (not shown) forming process formed during the capacitor forming process of the cell unit and formed by a subsequent patterning process, and a plurality of fuses are formed in a line / space form.

그 다음, 전체표면상부에 제1층간절연막(33)을 형성하고 이를 통과하는 비아콘택플러그(34)를 통해 하부구조물(미도시)에 접속되는 제1금속배선(35)을 형성한다. Next, a first interlayer insulating film 33 is formed on the entire surface and a first metal wiring 35 connected to the lower structure (not shown) is formed through the via contact plug 34 passing therethrough.

동시에 상기 제1금속배선(35)과 같은 물질, 특히 연성의 알루미늄으로 상기 제1금속배선(35)과 이격되도록 퓨즈박스 영역(미도시) 사이에 제1버퍼층(37)을 패터닝한다. At the same time, the first buffer layer 37 is patterned between fuse box regions (not shown) to be spaced apart from the first metal wiring 35 by a material such as the first metal wiring 35, in particular, soft aluminum.

이때, 상기 제1금속배선(35) 및 제1버퍼층(37)은 알루미늄이나 텅스텐으로 형성한 것이다. In this case, the first metal wiring 35 and the first buffer layer 37 are formed of aluminum or tungsten.

그 다음, 전체표면상부에 제2층간절연막(39)을 형성한다. 이때, 상기 제2층간절연막(39)은 상기 제1금속배선(35) 상부를 완전히 도포할 수 있는 두께로 증착하여 형성한 것이다. Next, a second interlayer insulating film 39 is formed over the entire surface. In this case, the second interlayer insulating layer 39 is formed by depositing a thickness to completely coat the upper portion of the first metal wiring 35.

그 다음 상기 제1금속배선(35)에 제2금속배선(43)을 콘택시키기 위한 비아 콘택 플러그(41)를 형성한다. Next, a via contact plug 41 for forming the second metal wire 43 on the first metal wire 35 is formed.

이때, 상기 비아콘택플러그(41)는 비아콘택마스크를 이용한 사진식각공정으로 상기 제2층간절연막(39)을 식각하여 형성한 것이다. In this case, the via contact plug 41 is formed by etching the second interlayer insulating layer 39 by a photolithography process using a via contact mask.

그 다음, 상기 제2비아콘택플러그(41)에 접속되는 제2금속배선(43)을 형성함으로써 상기 퓨즈(31)의 바깥쪽을 완전히 감싸는 가아드링 ( guard ring )을 형성한다. Next, a guard ring is formed to completely surround the outside of the fuse 31 by forming the second metal wire 43 connected to the second via contact plug 41.

동시에 상기 제2금속배선(43)과 같은 물질, 특히 연성의 알루미늄으로 상기 제2금속배선(43)과 이격되도록 퓨즈박스 영역(미도시) 사이에 제2버퍼층(45)을 패터닝한다. At the same time, the second buffer layer 45 is patterned between the fuse box regions (not shown) to be spaced apart from the second metal wiring 43 by a material such as the second metal wiring 43, in particular, soft aluminum.

이때, 상기 제2금속배선(43) 및 제2버퍼층(45)은 알루미늄이나 텅스텐으로 형성한 것이다. In this case, the second metal wire 43 and the second buffer layer 45 are formed of aluminum or tungsten.

그 다음, 전체표면상부에 제3층간절연막(47)을 형성하고 마스크를 이용한 식각공정으로 상기 퓨즈(31)들이 구비되는 영역인 퓨즈박스 영역 상측의 제3,2,1층간절연막(47,39,33)을 식각하여 퓨즈박스(100)를 형성한다. Next, the third interlayer insulating film 47 is formed on the entire surface, and the third, second and first interlayer insulating films 47 and 39 are formed on the upper side of the fuse box region, which is an area where the fuses 31 are provided by an etching process using a mask. , 33 is etched to form a fuse box 100.

이때, 상기 제3,2,1층간절연막(25,19,15)의 식각공정은 상기 퓨즈(13) 상측에 소정두께의 제1층간절연막(15)이 남도록 실시한다.At this time, the etching process of the third, second and first interlayer insulating films 25, 19 and 15 is performed such that the first interlayer insulating film 15 having a predetermined thickness remains on the upper side of the fuse 13.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 퓨즈박스 형성방법은, 가아드링을 구성하는 금속배선들과 퓨즈박스 사이에 상기 금속배선들과 같은 물질로 버퍼층을 형성하여 퓨즈박스 외측의 적층구조에 의한 퓨즈박스의 에지부에 발생되는 크랙을 방지함으로써 반도체소자의 리페어 공정을 용이하게 실시할 수 있도록 하는 효과를 제공한다. As described above, in the method of forming a fuse box of a semiconductor device according to the present invention, a buffer layer is formed of the same material as the metal wires between the metal wires constituting the guard ring and the fuse box to form a stack structure outside the fuse box. By preventing cracks generated at the edge portion of the fuse box by the present invention provides an effect to facilitate the repair process of the semiconductor device.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

퓨즈가 형성된 반도체기판 상에 제1층간절연막을 형성하고 그 상부에 제1금속배선 및 제1버퍼층을 형성하되, 상기 제1버퍼층은 제1금속배선과 퓨즈박스 사이에 형성되는 공정과,Forming a first interlayer insulating film on the semiconductor substrate on which the fuse is formed and forming a first metal wiring and a first buffer layer thereon, wherein the first buffer layer is formed between the first metal wiring and the fuse box; 전체표면상부에 제2층간절연막을 형성하고 상기 제1금속배선에 콘택되는 제2금속배선을 형성하는 동시에 제2버퍼층을 형성하되, 상기 제2버퍼층은 제2금속배선과 퓨즈박스 사이에 형성되는 공정과,A second interlayer insulating film is formed on the entire surface and a second metal wiring contacting the first metal wiring is formed, and a second buffer layer is formed. The second buffer layer is formed between the second metal wiring and the fuse box. Fair, 전체표면상부에 보호막인 제3층간절연막을 형성하는 공정과,Forming a third interlayer insulating film as a protective film over the entire surface; 상기 제3,2,1층간절연막을 식각하여 상기 제1,2버퍼층이 노출되도록 퓨즈박스를 형성하는 공정을 포함하는 것을 특징으로 반도체소자의 퓨즈박스 형성방법.And forming a fuse box to etch the third, second, and first interlayer insulating layers to expose the first and second buffer layers. 제 1 항에 있어서,The method of claim 1, 상기 제1버퍼층 및 제2버퍼층은 금속배선과 같은 물질로 구비되는 것을 특징으로 하는 반도체소자의 퓨즈박스 형성방법.The first buffer layer and the second buffer layer is a fuse box forming method of a semiconductor device, characterized in that provided with a material such as metal wiring. 제 1 항에 있어서,The method of claim 1, 상기 제1버퍼층 및 제2버퍼층은 연성의 알루미늄으로 구비되는 것을 특징으로 하는 반도체소자의 퓨즈박스 형성방법.And the first buffer layer and the second buffer layer are made of ductile aluminum. 청구항 1 의 방법으로 형성되는 반도체소자의 퓨즈박스.A fuse box of a semiconductor device formed by the method of claim 1.
KR1020050041126A 2005-05-17 2005-05-17 Method for forming fuse box of semiconductor devices KR100702301B1 (en)

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Publication number Priority date Publication date Assignee Title
KR100792442B1 (en) * 2007-01-10 2008-01-10 주식회사 하이닉스반도체 Semiconductor device having fuse pattern and method for fabricating the same

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KR100305074B1 (en) * 1998-06-30 2001-11-02 박종섭 Method for forming fuse box for repairing semiconductor device
KR20010003523A (en) * 1999-06-23 2001-01-15 김영환 Method for forming a fuse in a semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100792442B1 (en) * 2007-01-10 2008-01-10 주식회사 하이닉스반도체 Semiconductor device having fuse pattern and method for fabricating the same

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