KR20060099620A - Method of manufacturing a flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a flash memory device, wherein the oxide, nitride, and oxide films are sequentially formed to fill a trench, thereby forming an isolation layer, and over-etching the second polysilicon film to pattern the floating gate of the cell region. In this case, a method of manufacturing a flash memory device capable of reducing the threshold of the cell by changing the threshold without reducing the overlay margin by etching the nitride film without loss of the oxide film is disclosed.

Multilevel Cell, Cell Threshold Voltage, Interference, Overlay Margin, Device Isolation, Nitride

Description

Method of manufacturing a flash memory device

1A to 1E are cross-sectional views of devices sequentially shown to explain a method of manufacturing a NAND type flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

A: cell area B: peripheral circuit area

11 semiconductor substrate 12 tunnel oxide film

13: 1st polysilicon film 14: pad nitride film

15 trench 16: first oxide film

17 nitride film 18 second oxide film

19: second polysilicon film 20: dielectric film

21: third polysilicon film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a NAND type flash memory device capable of reducing a cell threshold voltage change due to an interference without reducing an overlay margin.

In a NAND type flash memory device, a plurality of cells for storing data are connected in series to form a string, a drain select transistor is formed between the cell string and the drain, and a source select transistor is formed between the cell string and the source. . The cell of the NAND type flash memory device is formed by forming a device isolation film by a SA-STI process, forming a stack gate in which a floating gate, a dielectric film, and a control gate are stacked, and forming a junction part by an impurity ion implantation process on a semiconductor substrate. Is implemented. Here, the process of forming the stack gate will be described in more detail as follows. After the tunnel oxide film and the first polysilicon film are formed on the semiconductor substrate, trenches are formed by etching the predetermined region and the semiconductor substrate to a predetermined depth, and then an insulating film is embedded to form a device isolation film. After forming a second polysilicon film on the entire structure, patterning is performed to form a floating gate in which the first and second polysilicon films are stacked, and a dielectric film composed of an oxide film, a nitride film, and an oxide film and a third polysilicon film are formed. Patterning to form the control gate.

Meanwhile, the size of flash memory cells is also reduced due to the high integration of semiconductor devices. However, due to the limitation of patterning technology and equipment, the progress of speed is slowing down. In order to overcome this limitation, studies on multiple bit cells capable of storing a plurality of data in one memory cell are being actively conducted. This type of memory cell is commonly referred to as a Multi Level Cell (MLC). The multi-level cell (MLC) typically has two or more threshold voltage distributions, and may store two or more data corresponding thereto. Accordingly, since one cell may be divided into four or more levels as compared to two levels of single level cells (SLCs), the number of bits more than twice as many as SLCs may be increased.

In order to implement the MLC, it is important to reduce the change in the cell threshold voltage. One of the factors of the change in the cell threshold voltage is the interference effect caused by the inter-cell capacitance. However, the interference decreases as the second polysilicon film is excessively etched to recess the device isolation layer. However, when the lower oxide layer of the dielectric layer becomes equal to the height of the tunnel oxide layer due to excessive transient etching, or when the gap between the device isolation layer and the dielectric layer becomes smaller than the tunnel oxide layer thickness due to misalignment of the floating gate mask, the device isolation layer and the dielectric layer There is a possibility of leakage between the membranes. That is, when the second polysilicon film is excessively etched, the interference may be reduced, thereby reducing the change in the threshold voltage of the cell, but the overlay margin of the floating gate mask may be reduced by more than the thickness of the tunnel oxide layer, thereby causing leakage. .

An object of the present invention is that even when the second polysilicon film for etching the floating gate is excessively etched, no leakage occurs because the device isolation layer is not lost, thereby reducing the interference without reducing the overlay margin. It is to provide a method of manufacturing a flash memory device that can reduce the voltage change.

In order to achieve the above object, in the present invention, an oxide film, a nitride film, and an oxide film are formed to form a device isolation film by filling a trench, and when the second polysilicon film is excessively etched, the nitride film is etched without loss of oxide film so that the interlayer can be etched without reducing the overlay margin It is possible to reduce the conduction, which reduces the cell threshold voltage change.

A method of manufacturing a flash memory device according to an embodiment of the present invention may include sequentially forming a tunnel oxide film, a first polysilicon film, and a pad nitride film on an upper portion of a semiconductor substrate in which a cell region and a peripheral circuit region are determined; Etching a predetermined region of the pad nitride layer to the tunnel oxide layer and then etching the semiconductor substrate to a predetermined depth to form a trench; Forming a first oxide film over the entire structure to partially fill the trench, and then forming a nitride film over the trench; Etching the entire nitride film so that the nitride film remains in the cell region and the nitride film is removed in the peripheral circuit region; Forming a second oxide layer over the entire structure to fill the trench; Polishing the first and second oxide films and removing the pad nitride film to form an isolation layer; Forming a floating gate pattern by etching a second polysilicon layer on the entire structure; And forming a dielectric film and a third polysilicon film on the entire structure, and then patterning to form a control gate.

The trench is formed to be narrower in the cell region than the peripheral circuit region.

The second polysilicon layer is excessively etched, and the nitride layer of the cell region is partially removed by the excessive etching, and the first and second oxide layers of the cell region are not removed.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1A to 1E are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a tunnel oxide film 12 and a first polysilicon film 13 are disposed on a semiconductor substrate 11 on which a cell region A, a peripheral circuit region B, and the like are determined through a predetermined process. ) And the pad nitride film 14 are sequentially formed. After etching a predetermined region of the pad nitride layer 14, the first polysilicon layer 13, and the tunnel oxide layer 12 by a photolithography and an etching process using an element isolation mask, the semiconductor substrate 11 is etched to a predetermined depth to form a trench ( 15). At this time, the trench 15 is formed to have a narrow width in the cell region A where the pattern density is dense, and is formed to be wide in the peripheral circuit region B having the coarse pattern density. The first oxide layer 16 is formed on the entire structure such that the trench 15 is partially buried instead of partially buried. The nitride film 17 is formed on the first oxide film 16.

Referring to FIG. 1 (b), the nitride film 17 is etched entirely, so that the nitride film 17 remains only in the cell region A where the pattern density is dense and the nitride film of the peripheral region B having the coarse pattern density. 17 is completely removed. Then, the second oxide film 18 is formed on the entire structure so that the trench 15 is completely buried.

Referring to FIG. 1C, the second oxide film 18 and the first oxide film 16 are polished to expose the nitride film 17. The pad nitride layer 14 is removed to form an isolation layer. The second oxide layer 18 of the cell region A is removed to expose the nitride layer 17.

Referring to FIG. 1D, a second polysilicon layer 19 is formed on the entire structure and then etched to form a floating gate pattern. In this case, the second polysilicon layer 19 of the cell region A is excessively etched to reduce the cell threshold voltage change. However, the nitride layer 17 is partially removed during the excessive etching of the second polysilicon layer 19. The first oxide film 16 is not removed. Therefore, since the first oxide film 16 serving as the device isolation film is not removed, no leakage occurs, thereby ensuring sufficient overlay margin.

Referring to FIG. 1E, after forming the dielectric film 20 over the entire structure, the third polysilicon film 21 is formed. An etching process for forming a gate is performed to form a stack gate in which a floating gate and a control gate are stacked.

As described above, according to the present invention, an oxide film is etched when an oxide film, a nitride film, and an oxide film are formed to form a device isolation film by filling trenches, and the second polysilicon film is excessively etched to reduce the interference for reducing the cell threshold voltage. By etching the nitride film, the interference can be reduced without reducing the overlay margin.

Claims (3)

Sequentially forming a tunnel oxide film, a first polysilicon film, and a pad nitride film on the semiconductor substrate in which the cell region and the peripheral circuit region are determined; Etching a predetermined region of the pad nitride layer to the tunnel oxide layer and then etching the semiconductor substrate to a predetermined depth to form a trench; Forming a first oxide film over the entire structure to partially fill the trench, and then forming a nitride film over the trench; Etching the entire nitride film so that the nitride film remains in the cell region and the nitride film is removed in the peripheral circuit region; Forming a second oxide layer over the entire structure to fill the trench; Polishing the first and second oxide films and removing the pad nitride film to form an isolation layer; Forming a floating gate pattern by etching a second polysilicon layer on the entire structure; And Forming a control gate by forming a dielectric film and a third polysilicon film over the entire structure and then patterning the dielectric film and the third polysilicon film. The method of claim 1, wherein the trench is formed to be narrower in the cell region than the peripheral circuit region. The flash memory device of claim 1, wherein the second polysilicon layer is excessively etched, the nitride layer of the cell region is partially removed by the excessive etching, and the first and second oxide layers of the cell region are not removed. Manufacturing method.

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