KR20060099105A - Method for forming high dielectric film by atomic layer deposition, method of fabricating semiconductor device having high dielectric film and semiconductor device fabricated by the same - Google Patents
Method for forming high dielectric film by atomic layer deposition, method of fabricating semiconductor device having high dielectric film and semiconductor device fabricated by the same Download PDFInfo
- Publication number
- KR20060099105A KR20060099105A KR1020050020134A KR20050020134A KR20060099105A KR 20060099105 A KR20060099105 A KR 20060099105A KR 1020050020134 A KR1020050020134 A KR 1020050020134A KR 20050020134 A KR20050020134 A KR 20050020134A KR 20060099105 A KR20060099105 A KR 20060099105A
- Authority
- KR
- South Korea
- Prior art keywords
- dielectric film
- gas
- high dielectric
- supplying
- predetermined time
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 93
- 238000000231 atomic layer deposition Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000007789 gas Substances 0.000 claims abstract description 179
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 60
- 239000012495 reaction gas Substances 0.000 claims abstract description 44
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 30
- 239000002243 precursor Substances 0.000 claims abstract description 27
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 20
- 238000006243 chemical reaction Methods 0.000 claims abstract description 9
- 238000010926 purge Methods 0.000 claims description 58
- 239000000654 additive Substances 0.000 claims description 22
- 230000000996 additive effect Effects 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 17
- 229910004129 HfSiO Inorganic materials 0.000 claims description 12
- 239000007772 electrode material Substances 0.000 claims description 10
- 229910052786 argon Inorganic materials 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- 230000001590 oxidative effect Effects 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 229910003855 HfAlO Inorganic materials 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims description 4
- 229910052735 hafnium Inorganic materials 0.000 claims description 4
- 229910002367 SrTiO Inorganic materials 0.000 claims description 3
- 229910010052 TiAlO Inorganic materials 0.000 claims description 3
- 229910006501 ZrSiO Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 229910052712 strontium Inorganic materials 0.000 claims description 3
- 229910052726 zirconium Inorganic materials 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052801 chlorine Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 16
- 239000010408 film Substances 0.000 description 134
- 239000003990 capacitor Substances 0.000 description 20
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 16
- 239000010410 layer Substances 0.000 description 15
- 239000010409 thin film Substances 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 7
- WYTZZXDRDKSJID-UHFFFAOYSA-N (3-aminopropyl)triethoxysilane Chemical compound CCO[Si](OCC)(OCC)CCCN WYTZZXDRDKSJID-UHFFFAOYSA-N 0.000 description 6
- 239000012528 membrane Substances 0.000 description 6
- 239000007800 oxidant agent Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 229910004143 HfON Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000006227 byproduct Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000376 reactant Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910001873 dinitrogen Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 210000002381 plasma Anatomy 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000004451 qualitative analysis Methods 0.000 description 1
- 238000004445 quantitative analysis Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000005011 time of flight secondary ion mass spectroscopy Methods 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/308—Oxynitrides
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
- C23C16/45523—Pulsed gas flow or change of composition over time
- C23C16/45525—Atomic layer deposition [ALD]
- C23C16/45527—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations
- C23C16/45531—Atomic layer deposition [ALD] characterized by the ALD cycle, e.g. different flows or temperatures during half-reactions, unusual pulsing sequence, use of precursor mixtures or auxiliary reactants or activations specially adapted for making ternary or higher compositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02194—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing more than one metal element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3145—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers formed by deposition from a gas or vapour
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31645—Deposition of Hafnium oxides, e.g. HfO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
- H01L21/02148—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Formation Of Insulating Films (AREA)
Abstract
고유전막 내에 탄소 함량을 줄여주어 누설전류 특성을 개선할 수 있고, 고유전막 내에 질소의 양을 정밀하게 조절할 수 있는 원자층 증착법에 의한 고유전막 형성 방법, 고유전막을 갖는 반도체소자의 제조 방법 및 이러한 고유전막을 포함하는 반도체소자가 개시되어 있다. 본 발명의 고유전막 형성방법은 (a) 반응챔버내에 제1 소오스가스를 일정 시간 공급하는 단계 (b) 상기 제1 소오스가스를 공급한 후 제1 반응가스를 일정 시간 공급하는 단계 (c) 상기 제1 반응가스를 공급한 후 제2 소오스가스를 일정 시간 공급하는 단계 (d) 상기 제2 소오스가스를 공급한 후 제2 반응가스를 일정 시간 공급하는 단계 및 (e) 상기 (a) 내지 (d) 단계 사이에 적어도 1회 이상 질소 성분을 함유하는 첨가가스를 일정 시간 공급하는 단계를 포함한다. A method of forming a high dielectric film by an atomic layer deposition method capable of reducing the carbon content in the high dielectric film to improve leakage current characteristics and precisely controlling the amount of nitrogen in the high dielectric film, a method of manufacturing a semiconductor device having a high dielectric film, and the like A semiconductor device comprising a high dielectric film is disclosed. The method of forming a high-k dielectric film of the present invention comprises: (a) supplying a first source gas into the reaction chamber for a predetermined time; (b) supplying a first reaction gas after supplying the first source gas for a predetermined time; Supplying a second source gas for a predetermined time after supplying the first reaction gas (d) supplying a second reaction gas for a predetermined time after supplying the second source gas and (e) the above (a) to ( d) supplying an additional gas containing nitrogen components at least one time between steps for a predetermined time.
고유전막, 원자층 증착법, 탄소, 질소, Hf 전구체, Si 전구체 High dielectric film, atomic layer deposition, carbon, nitrogen, Hf precursor, Si precursor
Description
도 1은 본 발명의 일 실시예에 따라 형성된 HfSiON막을 게이트 절연막으로 사용하는 게이트 구조를 개략적으로 나타낸 단면도이다.1 is a schematic cross-sectional view of a gate structure using an HfSiON film formed as a gate insulating film according to an embodiment of the present invention.
도 2는 본 발명의 다른 실시예에 따라 형성된 HfSiON막을 커패시터 유전막으로 사용하는 커패시터 구조를 개략적으로 나타낸 단면도이다. 2 is a schematic cross-sectional view of a capacitor structure using an HfSiON film formed according to another embodiment of the present invention as a capacitor dielectric film.
도 3 내지 도 10은 본 발명의 여러 가지 실시예들에 따라 원자층 증착법으로 고유전막을 형성하는 경우 공급되는 가스 펄싱 다이아그램들이다.3 to 10 are gas pulsing diagrams supplied when a high dielectric film is formed by atomic layer deposition according to various embodiments of the present disclosure.
도 11은 본 발명의 일 실시예에 따라 형성된 고유전막내의 탄소함량과 종래 기술에 따라 형성된 고유전막내의 탄소함량을 비교한 그래프이다.11 is a graph comparing the carbon content in the high dielectric film formed according to the prior art and the carbon content in the high dielectric film formed according to an embodiment of the present invention.
도 12는 본 발명의 일 실시예에 따라 형성된 고유전막내의 질소 분포와 종래 기술에 따라 형성된 고유전막내의 질소 분포를 비교한 그래프이다.12 is a graph comparing the nitrogen distribution in the high dielectric film formed according to the prior art and the nitrogen distribution in the high dielectric film formed according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
10, 30 ; 반도체기판 12 ; 게이트 유전막10, 30;
14 ; 게이트 전극 16 ; 게이트마스크층14;
18 ; 게이트 스페이서 32 ; 층간절연막18;
34 ; 도전층 플러그 36 ; 커패시터 하부전극34;
38 ; 커패시터 유전막 40 ; 커패시터 상부전극38; Capacitor
본 발명은 반도체 소자에 사용되는 유전막에 관한 것으로, 보다 상세하게는 원자층 증착법(Atomic Layer Deposition : ALD)을 이용한 유전막 형성 방법, 이러한 유전막을 갖는 반도체소자의 제조 방법 및 이들 방법에 의해 제조되는 반도체소자에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric film for use in semiconductor devices, and more particularly, to a method of forming a dielectric film using atomic layer deposition (ALD), a method of manufacturing a semiconductor device having such a dielectric film, and a semiconductor manufactured by these methods. It relates to an element.
최근 반도체 소자의 고집적화 및 대용량화의 경향에 따라 MOSFET의 게이트 유전막(절연막) 또는 커패시터 유전막에 고유전율의 물질을 적용하고자 하는 연구가 급속도로 이루어지고 있다. 고유전막을 게이트 절연막으로 사용할 경우, 동일한 등가 산화막 두께(Toxeq)를 갖는 고유전막은 일반적으로 사용되는 SiO2에 비하여 물리적인 두께가 두껍기 때문에 전자의 터널링으로 인한 누설 전류의 급격한 증가를 줄일 수 있다. 예를 들어, SiO2막을 게이트 절연막으로 사용할 경우 20Å 이하의 두께에서는 전자의 터널링으로 인해 누설 전류가 급격히 증가하지만, 하프늄 산화막(HfO2), 지르코늄 산화막(ZrO2), 탄탈륨 산화막(Ta2O5), 타이타늄 산화막(TiO2) 등 의 고유전막을 게이트 절연막으로 사용할 경우에는 동일한 등가 산화막 두께에서도 누설 전류의 급격한 증가를 억제할 수 있다.Recently, according to the trend of high integration and large capacity of semiconductor devices, researches are being made to apply a material having a high dielectric constant to a gate dielectric layer (insulation layer) or a capacitor dielectric layer of a MOSFET. When the high dielectric film is used as the gate insulating film, the high dielectric film having the same equivalent oxide thickness (Toxeq) has a larger physical thickness than that of SiO 2 , which is generally used, thereby reducing a sudden increase in leakage current due to tunneling of electrons. For example, when the SiO 2 film is used as the gate insulating film, the leakage current increases rapidly due to the tunneling of electrons at a thickness of 20 mA or less, but the hafnium oxide film (HfO 2 ), the zirconium oxide film (ZrO 2 ), and the tantalum oxide film (Ta 2 O 5). ), When a high dielectric film such as a titanium oxide film (TiO 2 ) is used as the gate insulating film, a sudden increase in leakage current can be suppressed even at the same equivalent oxide film thickness.
그러나, 고유전막을 MOSFET 소자의 게이트 절연막에 적용할 경우, 여러 가지 문제점들이 나타나고 있다. 예를 들어, HfO2 및 ZrO2 등의 고유전막을 게이트 절연막으로 사용할 경우, 상부의 폴리실리콘 게이트 전극으로부터의 B, P, As 등의 도펀트 확산으로 인하여, 채널(channel)에서의 캐리어 이동도(mobility)를 저하시키게 된다. 또한, HfO2 등의 고유전막은 후속의 열처리 공정에 의해 쉽게 결정화될 수 있는데, 이와 같은 결정화는 결정화된 계면을 통하여 누설 전류를 일으키게 하는 원인이 된다. 따라서, 게이트 절연막으로 고유전막을 사용할 경우, 상부의 폴리실리콘 게이트 전극으로부터의 도펀트 확산을 억제하고, 열처리 온도에 따른 열적 안정성을 확보할 필요가 있다.However, when the high dielectric film is applied to the gate insulating film of the MOSFET device, various problems appear. For example, when a high dielectric film such as HfO 2 and ZrO 2 is used as the gate insulating film, carrier mobility in the channel may be due to diffusion of dopants such as B, P, and As from the upper polysilicon gate electrode. will reduce mobility. In addition, a high dielectric film such as HfO 2 can be easily crystallized by a subsequent heat treatment process. Such crystallization causes leakage current through the crystallized interface. Therefore, when the high dielectric film is used as the gate insulating film, it is necessary to suppress the dopant diffusion from the upper polysilicon gate electrode and to ensure thermal stability according to the heat treatment temperature.
이와 같은 도펀트 확산의 방지 및 열적 안정성의 확보를 위하여, HfO2 막 등 고유전율의 산화막 내에 Al2O3 또는 질소를 첨가하여 HfON 또는 HfAlO막 등의 고유전율의 질화산화막을 얻고자 하는 연구가 진행되고 있으나, HfO2 단일막에 비하여 특성이 일부 개선되고 있으나 초미세 소자의 트랜지스터에서 요구하는 특성을 만족시키기에는 한계를 드러내고 있다. In order to prevent such diffusion of dopants and to secure thermal stability, studies have been conducted to obtain high dielectric constant nitride films such as HfON or HfAlO films by adding Al 2 O 3 or nitrogen to oxide films having high dielectric constant such as HfO 2 . However, although the characteristics are partially improved compared to the HfO 2 single layer, the characteristics of the transistors of the ultrafine devices are limited.
한편, HfO2 물질에 대한 대안으로 Si을 첨가한 Hf-실리케이트 물질인 HfSiO 물질은 하부 채널영역이 되는 실리콘 기판에 증착할 경우 이동도, 온-오프 전류 특 성등이 기존의 HfO2에 비하여 향상된 특성을 보이나 여전히 상부 게이트 폴리실리콘으로부터의 도펀트의 확산으로 인하여 채널에서의 이동도를 저하시키는 문제점이 여전히 남아있다. On the other hand, HfSiO material, an Hf-silicate material added with Si as an alternative to HfO 2 material, has improved characteristics compared to conventional HfO 2 in terms of mobility and on-off current characteristics when deposited on a silicon substrate that is a lower channel region. Although still visible, the problem of lowering mobility in the channel remains due to the diffusion of dopants from the top gate polysilicon.
이와 같은 도펀트의 확산의 방지 및 열적 안정성의 확보를 위하여 고유전율의 산화막 내에 질소를 첨가하여 고유전율의 질화산화막을 얻고자 하는 연구가 진행되고 있다. 즉, HfO2 또는 HfSiO 등의 고유전막 내에 질소를 첨가하여 고유전율의 질화산화막을 형성함으로써 상부의 전극으로부터 유래되는 불순물의 이동을 막아주고, 고유전막의 결정화 온도를 상승시켜 열적 안정성을 확보할 수 있게 된다. HfON 또는 HfSiON 등의 질화산화막을 제조하는 방법에는 산화막을 증착한 후 NH3 분위기에서 어닐링하는 질화 처리를 진행하는 방법이 있으나 고유전 박막 내에 원하는 질소(N)의 프로파일을 얻기 힘들고, 후속 질화 처리라는 새로운 공정이 추가되는 단점이 있다.In order to prevent such diffusion of dopants and to secure thermal stability, studies have been conducted to obtain nitrogen oxide films having high dielectric constant by adding nitrogen into oxide films having high dielectric constant. In other words, by adding nitrogen into a high dielectric film such as HfO 2 or HfSiO to form a nitride oxide film having a high dielectric constant, it prevents the movement of impurities originating from the upper electrode and increases the crystallization temperature of the high dielectric film to secure thermal stability. Will be. A method of manufacturing a nitride oxide film such as HfON or HfSiON includes a method of performing a nitriding treatment in which an oxide film is deposited and annealing in an NH 3 atmosphere, but it is difficult to obtain a desired profile of nitrogen (N) in the high dielectric film. The disadvantage is that new processes are added.
고유전율의 질화산화막을 얻기위해, N이 포함된 새로운 Hf 전구체(Hf precursor)와 Si 전구체를 이용하여 ALD 방식으로 HfSiON막을 증착하는 방법이 개발되고 있다. 그러나, 박막내에 N 결합을 갖는 HfSiON 박막을 증착하기 힘들며, 반대로 Hf[N(CH3)2]4 처럼 전구체에 N이 포함되어 있는 경우에는, 전구체 내의 질소와 탄소 간의 N-C 결합이 매우 강하기 때문에 H2O 등의 산화제를 사용하여 HfSiO막을 증착하더라도 막 내에는 탄소가 잔존하게 된다. HfSiO막 내에 잔존하는 탄소는 막의 전기적 특성을 저하시키는 요인이 된다.In order to obtain a nitride oxide film having a high dielectric constant, a method of depositing an HfSiON film by an ALD method using a new Hf precursor containing Si and a Si precursor has been developed. However, it is difficult to deposit HfSiON thin films with N bonds in the thin film. On the contrary, when N is included in the precursor, such as Hf [N (CH 3 ) 2 ] 4 , since the NC bond between nitrogen and carbon in the precursor is very strong, H Even if an HfSiO film is deposited using an oxidant such as 2 O, carbon remains in the film. The carbon remaining in the HfSiO film becomes a factor of lowering the electrical properties of the film.
한편, 반도체 메모리 소자가 고집적화됨에 따라 소자의 안정적인 구동을 위해 필요한 단위 셀당 커패시터의 정전 용량은 일정한 반면에 단위셀당 커패시터의 면적이 감소되므로 점차 고집적화의 한계에 접근해 가고 있다. 이를 해결하기 위해 커패시터의 정전 용량을 높여서 단위셀당 축적되는 전하량을 증가시킬 필요가 있다. 커패시터의 정전 용량을 높이는 방법에는, 커패시터 유전막의 유전율을 증가시킴으로써 정전 용량을 증가시키는 방법이 있다. 기존의 실리콘 산화막(SiO2;유전율 ~3.9)이나 실리콘 질화막(Si3N4;유전율 ~7.2) 또는 실리콘 질화막/실리콘 산화막의 복합막(ONO;유전율 3.9~7.2)을 고유전율의 유전막으로 대체하는 기술이 개발되고 있다. 따라서 커패시터 유전막에 대하여도 전술한 게이트 절연막으로서 고유전막을 사용하는 것과 동일한 문제가 대두된다. On the other hand, as semiconductor memory devices are highly integrated, the capacitance of a capacitor per unit cell required for stable driving of the device is constant, whereas the area of the capacitor per unit cell is reduced, thereby approaching the limit of high integration. To solve this problem, it is necessary to increase the amount of charge accumulated per unit cell by increasing the capacitance of the capacitor. As a method of increasing the capacitance of a capacitor, there is a method of increasing the capacitance by increasing the dielectric constant of the capacitor dielectric film. It replaces existing silicon oxide film (SiO 2 ; dielectric constant ~ 3.9), silicon nitride film (Si 3 N 4 ; dielectric constant ~ 7.2) or silicon nitride / silicon oxide composite film (ONO; dielectric constant 3.9 ~ 7.2) Technology is being developed. Therefore, the same problem as that of using the high-k dielectric film as the gate insulating film described above also arises for the capacitor dielectric film.
즉, 고유전막 내에 탄소 등의 결함을 줄여주어 누설전류 특성을 개선할 수 있으며, 고유전막 내에 질소의 양을 정밀하게 조절할 수 있는 원자층 증착법에 대한 연구가 요구되고 있다.That is, it is possible to improve leakage current characteristics by reducing defects such as carbon in the high dielectric film, and research on an atomic layer deposition method capable of precisely controlling the amount of nitrogen in the high dielectric film is required.
따라서, 본 발명이 이루고자 하는 기술적 과제는 상술한 문제점을 해결하기 위한 것으로서, 고유전막 내에 탄소 등 결함을 줄여주어 누설전류 특성을 개선할 수 있고, 고유전막 내에 N의 양을 정밀하게 조절할 수 있는 ALD에 의한 고유전막 형성 방법을 제공하는 것이다.Therefore, the technical problem to be achieved by the present invention is to solve the above-described problems, and can reduce the defects such as carbon in the high dielectric film to improve the leakage current characteristics, ALD capable of precisely adjusting the amount of N in the high dielectric film It is to provide a high dielectric film forming method.
또한, 본 발명이 이루고자 하는 다른 기술적 과제는 본 발명에 따른 고유전 막을 갖는 반도체소자의 제조 방법을 제공하는 것이다.Another object of the present invention is to provide a method of manufacturing a semiconductor device having a high dielectric film according to the present invention.
또한, 본 발명이 이루고자 하는 또 다른 기술적 과제는 상기 방법에 의해 형성된 고유전막 및 이러한 고유전막을 포함하는 반도체소자를 제공하는 것이다.In addition, another technical problem to be achieved by the present invention is to provide a high dielectric film formed by the above method and a semiconductor device comprising such a high dielectric film.
상기 기술적 과제를 달성하기 위하여 본 발명의 제 1 형태에 따르면, (a) 반응챔버내에 제1 소오스가스를 일정 시간 공급하는 단계; (b) 상기 제1 소오스가스를 공급한 후 제1 반응가스를 일정 시간 공급하는 단계; (c) 상기 제1 반응가스를 공급한 후 제2 소오스가스를 일정 시간 공급하는 단계; (d) 상기 제2 소오스가스를 공급한 후 제2 반응가스를 일정 시간 공급하는 단계; 및 (e) 상기 (a) 내지 (d) 단계 사이에 적어도 1회 이상 질소 성분을 함유하는 첨가가스를 일정 시간 공급하는 단계;를 포함하는 원자층 증착법에 의한 고유전막 형성방법이 제공된다.According to a first aspect of the present invention for achieving the above technical problem, (a) supplying a first source gas into the reaction chamber for a predetermined time; (b) supplying a first reaction gas for a predetermined time after supplying the first source gas; (c) supplying a second source gas for a predetermined time after supplying the first reaction gas; (d) supplying a second reaction gas for a predetermined time after supplying the second source gas; And (e) supplying an additional gas containing a nitrogen component at least one time between the steps (a) to (d) for a predetermined time. A high-k dielectric film forming method comprising the atomic layer deposition method is provided.
상기 (e) 단계는 상기 (a) 단계와 상기 (b) 단계 사이, 상기 (b) 단계와 상기 (c) 단계 사이, 상기 (c) 단계와 상기 (d) 단계 사이, 또는 상기 (d) 단계 후에 수행될 수 있다. 또한, 상기 (e) 단계는 상기 (c) 단계 전후에 적어도 1회 이상, 바람직하게는 상기 (a) 단계와 상기 (b) 단계 사이 및 상기 (c) 단계와 상기 (d) 단계 사이, 상기 (a) 단계와 상기 (b) 단계 사이 및 상기 (d) 단계 후, 상기 (b) 단계와 상기 (c) 단계 사이 및 상기 (c) 단계와 상기 (d) 단계 사이, 또는 상기 (b) 단계와 상기 (c) 단계 사이 및 상기 (d) 단계 후에 수행될 수도 있다. 나아가, 상기 (e) 단계는 상기 (a) 단계 내지 상기 (d) 단계 중의 적어도 하나의 단계와 동시에 수행될 수도 있다. 한편, 상기 (a) 단계 내지 상기 (e) 단계 중 적어도 어느 한 단계를 수행한 후 상기 반응챔버내에 공급된 해당 가스를 퍼지가스를 사용하여 퍼지하는 단계를 더 포함할 수 있다.Step (e) is between step (a) and step (b), between step (b) and step (c), between step (c) and step (d), or (d) May be performed after the step. Further, step (e) is at least one or more times before and after step (c), preferably between step (a) and step (b) and between step (c) and step (d), between step (a) and step (b) and after step (d), between step (b) and step (c) and between step (c) and step (d), or (b) It may be performed between step (c) and after step (d). Furthermore, step (e) may be performed simultaneously with at least one of steps (a) to (d). On the other hand, after performing at least one of the steps (a) to (e) may further comprise the step of purging the gas supplied in the reaction chamber using a purge gas.
상기 제1 소오스가스는 Hf, Zr, La, Ta, Sr, Ti 중 어느 하나를 포함하는 전구체를 사용하며, 상기 제1 및 제2 반응가스는 산소를 포함하는 산화성 가스로서 O3, H2O, H2O2, CH3OH, C2H5OH 또는 C3H7OH 중의 어느 하나를 사용하며, 상기 질소 성분을 포함하는 첨가가스는 NH3 가스, N2O 가스, NO 가스 또는 NH3 플라즈마 중의 어느 하나를 사용하며, 상기 제2 소오스가스는 Si, Ti, Al, 중 어느 하나를 포함하는 전구체를 사용하며, 상기 유전막 형성 방법에 의해 형성되는 고유전막은 HfSiO, ZrSiO, LaSiO, HfTaO, TaTiO, SrTiO3, TiAlO, HfAlO 또는 HfTiO 에 질소가 첨가된 단일막 또는 이들의 복합막으로 된다. The first source gas is a precursor containing any one of Hf, Zr, La, Ta, Sr, Ti, and the first and second reaction gas is an oxidizing gas containing oxygen, O 3 , H 2 O , H 2 O 2 , CH 3 OH, C 2 H 5 OH or C 3 H 7 OH is used, the additive gas containing the nitrogen component is NH 3 gas, N 2 O gas, NO gas or NH Any one of three plasmas is used, and the second source gas uses a precursor including any one of Si, Ti, Al, and the high dielectric film formed by the dielectric film forming method is HfSiO, ZrSiO, LaSiO, HfTaO. Or a single film or a composite film thereof in which nitrogen is added to TaTiO, SrTiO 3 , TiAlO, HfAlO, or HfTiO.
상기 본 발명의 다른 기술적 과제를 달성하기 위한 본 발명의 제2 형태에 따르면, 첨부하는 특허청구범위의 청구항 제1항 내지 청구항 제26항 중의 어느 한 항에 의한 고유전막 형성 방법에 의하여 상기 반도체기판 상에 고유전막을 형성하는 단계; 상기 고유전막 상에 게이트 전극 물질을 형성하는 단계; 및 상기 게이트 전극 물질 및 상기 고유전막을 식각하여 게이트 구조를 형성하는 단계를 포함하는 고유전막을 갖는 반도체소자의 제조 방법이 제공된다. According to a second aspect of the present invention for achieving another technical object of the present invention, the semiconductor substrate by the high-k dielectric film forming method according to any one of claims 1 to 26 of the appended claims. Forming a high dielectric film on the substrate; Forming a gate electrode material on the high dielectric film; And etching the gate electrode material and the high dielectric film to form a gate structure.
또한 상기 본 발명의 다른 기술적 과제를 달성하기 위한 본 발명의 제3 형태에 따르면, 반도체 기판 상에 하부 전극을 형성하는 단계; 첨부하는 특허청구범위의 청구항 제1항 내지 제26항 중의 어느 한 항의 유전막 형성 방법에 의해 상기 하 부 전극 상에 고유전막을 형성하는 단계; 및 상기 고유전막 상에 상부 전극을 형성하는 단계를 포함하는 고유전막을 갖는 반도체소자의 제조 방법이 제공된다.In addition, according to a third aspect of the present invention for achieving the above technical problem, forming a lower electrode on a semiconductor substrate; Forming a high dielectric film on the lower electrode by the method of forming a dielectric film according to any one of claims 1 to 26 of the appended claims; And forming an upper electrode on the high dielectric film.
또한 상기 본 발명의 또 다른 기술적 과제를 달성하기 위한 본 발명의 제4 형태에 따르면, 첨부하는 특허청구범위의 청구항 제1항 내지 제26항 중의 어느 한 항의 고유전막 형성 방법에 의해 형성된 고유전막이 제공된다.In addition, according to a fourth aspect of the present invention for achieving another technical problem of the present invention, the high-k dielectric film formed by the high-k dielectric film forming method of any one of claims 1 to 26 of the appended claims Is provided.
또한 상기 본 발명의 또 다른 기술적 과제를 달성하기 위한 본 발명의 제5 형태에 따르면, 첨부하는 특허청구범위의 청구항 제27항 내지 제29항 중의 어느 한 항의 고유전막을 갖는 반도체소자의 제조 방법에 의해 제조된 반도체소자가 제공된다. Further, according to a fifth aspect of the present invention for achieving another technical problem of the present invention, there is provided a method for manufacturing a semiconductor device having the high-k dielectric film of any one of claims 27 to 29 of the appended claims. Provided is a semiconductor device manufactured by the present invention.
또한 상기 본 발명의 또 다른 기술적 과제를 달성하기 위한 본 발명의 제6 형태에 따르면, 첨부하는 특허청구범위의 청구항 제30항 및 제31항 중의 어느 한 항의 고유전막을 갖는 반도체소자의 제조방법 의해 형성된 반도체소자가 제공된다.According to a sixth aspect of the present invention for achieving another technical object of the present invention, there is provided a semiconductor device having a high dielectric film according to any one of
이하, 첨부된 도면을 참조하여 본 발명의 실시예들을 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있으며, 본 발명의 범위가 이하 설명하는 실시예들로 한정되는 것은 아니다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해서 제공되는 것이다. 따라서, 도면에서의 요소들의 형상 및 크기 등은 보다 명확한 설명을 위해 과장될 수 있으며, 도면 상의 동일한 부호로 표시되는 요소는 동일한 요소이다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. Accordingly, the shape and size of elements in the drawings may be exaggerated for clarity, and the elements denoted by the same reference numerals in the drawings are the same elements.
도 1은 본 발명의 일 실시예에 따라 제조된 게이트 구조를 갖는 반도체소자 의 단면도이다. 그 제조방법을 간략히 설명하면, 반도체기판(10) 예를 들어, 실리콘 단결정 기판상에 게이트 유전막(12)으로서 예를 들어, 고유전막인 HfSiON막을 후술하는 바와 같이 원자층 증착법에 의해 소정의 두께가 되도록 형성한다. 이어서 게이트전극 물질(14)로서 예를 들어, B, P, As 등의 도펀트가 주입된 폴리실리콘이 형성되며, 게이트 전극물질(14) 상에 게이트마스크층(16)으로서 예를 들어, 실리콘 나이트라이드가 형성된다. 이어서 도시되지 않은 마스크 패턴을 식각마스크로 이용하여 식각공정을 수행하여 반도체기판(10)을 노출시킴으로서 소정 폭의 게이트 패턴을 갖는 게이트 구조를 형성한다. 게이트 구조의 측벽에는 후속되어 형성되는 층들과의 절연을 위해 게이트 스페이서(18)로서 예를 들어, 실리콘 나이트라이드 또는 실리콘 옥사이드가 형성된다. 1 is a cross-sectional view of a semiconductor device having a gate structure manufactured according to an embodiment of the present invention. A brief description will be made of a method of manufacturing the
상기 게이트 구조의 하부 반도체기판(10)에는 채널영역이 형성되며, 게이트 구조의 양측벽 하부에는 소오스/드레인영역이 형성되어 전형적인 모스(M0S) 트랜지스터가 형성된다. A channel region is formed in the
도 2는 본 발명의 일 실시예에 따라 제조된 커패시터 구조를 갖는 반도체소자의 단면도이다. 그 제조방법을 간략히 설명하면, 반도체기판(30) 예를 들어, 실리콘 단결정 기판상에 층간절연막(32)으로서 나이트라이드계 또는 옥사이드계 절연물질이 형성되며, 층간절연막(32)의 소정 위치에 형성된 콘택홀내에 반도체기판(30)과 전기적으로 연결되는 도전층 플러그(34)가 형성된다. 도전층 플러그(34)가 형성된 층간절연막(32) 상에 커패시터의 하부전극 물질이 형성된 후 패터닝되어 하부전극(36)이 형성된다. 하부전극(36) 및 노출된 층간절연막(32)에는 커패시터 유 전막(38)으로서 예를 들어, 고유전막인 HfSiON막을 후술하는 바와 같이 원자층 증착법에 의해 소정의 두께가 되도록 형성한다. 이어서 커패시터의 상부전극 물질(40)로서 예를 들어, B, P, As 등의 도펀트가 주입된 폴리실리콘 등을 형성함으로써 반도체 메모리소자에 적용되는 전형적인 커패시터가 형성된다. 2 is a cross-sectional view of a semiconductor device having a capacitor structure manufactured according to an embodiment of the present invention. A brief description will be made of a method of fabricating a
도 3은 본 발명의 일 실시예에 따라 고유전막을 형성하기 위한 원자층 증착법에서의 공급되는 가스 펄싱 다이아그램이다. 본 실시예에서 형성되는 고유전막은 전술한 게이트 구조에서의 게이트 유전막 또는 커패시터 구조에서의 커패시터 유전막에 모두 적용될 수 있다. 본 실시예에서는 도 1에서 게이트 유전막(12)으로서 HfSiON 막을 형성하는 방법에 대하여 설명한다. 도 3을 참조하여 고유전막이 형성되는 대상, 즉 반도체기판 상에 HfSiON 막을 원자층 증착법에 의해 형성하는 과정을 설명한다.3 is a gas pulsing diagram supplied in an atomic layer deposition method for forming a high dielectric film according to an embodiment of the present invention. The high dielectric film formed in this embodiment may be applied to both the gate dielectric film in the above-described gate structure or the capacitor dielectric film in the capacitor structure. In this embodiment, a method of forming an HfSiON film as the
먼저, 원자층 증착법을 수행할 수 있는 반응챔버내로 반도체기판을 로딩한 후, 제1 소오스가스로서 Hf 전구체인 TEMAH, 즉 Hf[N(C2H5)CH3]4를 일정 시간, 예를 들어 1초간 공급하여 Hf를 포함하는 화학 흡착층을 형성한다. 상기 제1 소오스가스로서는 Hf와 O, C, H, Cl 또는 N이 결합된 구조를 갖는 Hf 전구체를 사용할 수 있으며, 상기 TEMAH 외에도 Hf[N(CH3)2]4, Hf[N(C2H5)2]4, Hf[OC(CH3)3]4, 또는 HfCl4 중의 어느 하나를 사용할 수도 있다. First, after loading the semiconductor substrate into the reaction chamber capable of performing the atomic layer deposition method, the Hf precursor TEMAH, that is, Hf [N (C 2 H 5 ) CH 3 ] 4 as a first source gas for a predetermined time, for example For example, it is supplied for 1 second to form a chemical adsorption layer containing Hf. As the first source gas, Hf precursor having a structure in which Hf and O, C, H, Cl, or N are combined may be used. In addition to TEMAH, Hf [N (CH 3 ) 2 ] 4 , Hf [N (C 2 H 5 ) 2 ] 4 , Hf [OC (CH 3 ) 3 ] 4 , or HfCl 4 may be used.
이어서, 질소 성분이 함유된 첨가가스로서 NH3 가스를 일정 시간, 예를 들어 1초간 공급한다. NH3 가스를 공급해줌으로써 Hf 전구체 내에 존재하는 CH기가 제거 되고 탈착되지 않고 잔존하는 상당량의 탄소가 제거되어 HfN과 같은 중간막이 형성된다. 본 실시예에서는 NH3 가스를 사용하였지만, NH3 가스 이외에도 N2O 가스, NO 가스 또는 NH3 플라즈마를 사용할 수 있다.Subsequently, NH 3 gas is supplied as a nitrogen-containing additive gas for a predetermined time, for example, 1 second. By supplying the NH 3 gas, the CH group present in the Hf precursor is removed, and a considerable amount of carbon remaining without being desorbed is removed to form an intermediate film such as HfN. In this embodiment, although NH 3 gas is used, in addition to NH 3 gas, N 2 O gas, NO gas, or NH 3 plasma may be used.
이어서 잔존하는 부산물 및 흡착되지 않은 Hf 전구체를 퍼지가스인 아르곤 가스를 예를 들어 1초간 공급하여 제거한다. 퍼지가스로서는 이외에도 He 가스, 질소 가스등을 사용할 수 있다.Subsequently, the remaining byproduct and the unadsorbed Hf precursor are removed by supplying, for example, argon gas, which is a purge gas, for 1 second. In addition to the purge gas, He gas, nitrogen gas, or the like can be used.
그 다음에, 반도체 기판 상에 화합 흡착된 Hf 화합물, 즉 HfN을 산화시키기 위해 반응가스로서 산화제인 O3를 일정 시간, 예를 들어 3초간 공급한다. 이러한 O3의 공급에 의해 상기 HfN막은 산화되어 HfON막을 형성하게 된다. 상기 산화 단계에서 공급되는 산화제로는 O3 이외에 H2O, H2O2, CH3OH, C2H5OH 또는 C3H7OH를 사용할 수도 있다. Next, in order to oxidize the Hf compound, ie, HfN, which is chemically adsorbed onto the semiconductor substrate, O 3 as an oxidant is supplied for a predetermined time, for example, 3 seconds. By the supply of O 3 , the HfN film is oxidized to form an HfON film. In addition to O 3 , H 2 O, H 2 O 2 , CH 3 OH, C 2 H 5 OH, or C 3 H 7 OH may be used as the oxidant supplied in the oxidation step.
이어서, 상기 산화 단계 후에는, 잔존하는 부산물 및 산화되지 않은 산화제를 퍼지가스인 아르곤 가스를 예를 들어 3초간 공급하여 제거한다. 퍼지가스로서는 이외에도 He 가스, 질소 가스등을 사용할 수 있다.Subsequently, after the oxidation step, the remaining byproduct and the unoxidized oxidant are removed by supplying, for example, argon gas, which is a purge gas, for 3 seconds. In addition to the purge gas, He gas, nitrogen gas, or the like can be used.
이어서, 제2 소오스가스로서 Si와 O, C, H 또는 N이 결합된 구조를 갖는 Si 전구체인 H2N(CH2)3Si(OC2H5)3 을 일정 시간, 예를 들어 1초간 공급하여 Si을 포함하는 화학 흡착층을 HfON층 위에 형성한다. 본 실시예에서는 Si 전구체로서 APTES인 H2N(CH2)3Si(OC2H5)3 를 사용하였지만, 이외에도 SiH[N(CH3)2]3, Si[N(CH3)2]4, Si[N(CH3)C2H5]4, HSi[N(C2H5)2]3 등의 어느 하나를 사용할 수 있다. 이어서, 잔존하는 부산물을 제거하기 위해 퍼지가스인 아르곤 가스를 예를 들어 1초간 공급한다.Subsequently, H 2 N (CH 2 ) 3 Si (OC 2 H 5 ) 3, which is a Si precursor having a structure in which Si and O, C, H, or N are bonded as a second source gas, is held for a predetermined time, for example, for 1 second. It supplies and forms the chemisorption layer containing Si on a HfON layer. In this embodiment, H 2 N (CH 2 ) 3 Si (OC 2 H 5 ) 3, which is APTES, was used as the Si precursor. In addition, SiH [N (CH 3 ) 2 ] 3 , Si [N (CH 3 ) 2 ] 4 , Si [N (CH 3 ) C 2 H 5 ] 4 , HSi [N (C 2 H 5 ) 2 ] 3, or the like may be used. Subsequently, argon gas, which is a purge gas, is supplied for 1 second to remove residual byproducts.
이어서, Si을 포함한 Si 화합물을 산화시키기 위해 반응가스로서 산화제인 O3를 일정 시간, 예를 들어 3초간 공급한다. 이어서, 잔존하는 부산물 및 산화되지 않은 산화제를 퍼지가스인 아르곤 가스를 예를 들어 3초간 공급하여 제거한다. Then, after some period of oxidant O 3 as the reactive gas to oxidize the Si compound containing the Si, for example, supply for 3 seconds. Subsequently, the remaining byproduct and the unoxidized oxidant are removed by supplying, for example, argon gas, which is a purge gas, for 3 seconds.
이로써 본 실시예에 의한 HfSiON막 형성 공정의 1 사이클이 종료된다. 이러한 사이클을 계속 반복함으로써 원하는 두께의 HfSiON막을 형성할 수 있다.This completes one cycle of the HfSiON film forming process according to the present embodiment. By repeating this cycle continuously, an HfSiON film of desired thickness can be formed.
전술한 바와 같이, 본 실시예에서는 ALD 방식에 의해 Hf 전구체를 공급한 후, NH3 가스 공급을 수행함으로써 HfSiO막 내에 잔존하는 탄소량를 감소시킬 뿐만 아니라 HfSiO 박막내에 N을 첨가하여 HfSiON 박막을 형성함으로써 열적 안정성을 향상시키게 된다. 또한, NH3 가스의 공급량을 공급시간, 공급횟수 및 공급량을 조절함으로써 HfSiON막 내에 존재하는 질소량을 각각의 공정 조건에 알맞게 정밀하게 조절할 수 있게 된다. 이에 따라, 본 실시예에 의해 형성되는 HfSiON 박막내에 전기적 특성에 악 영향을 미치는 탄소함량이 감소하게 되며, 열적 안정성을 향상시키는 N의 함량이 증가하게 된다. As described above, in this embodiment, after supplying the Hf precursor by the ALD method, NH 3 gas supply is performed to not only reduce the amount of carbon remaining in the HfSiO film, but also add N to the HfSiO film to form the HfSiON thin film. It will improve the thermal stability. In addition, by adjusting the supply time, the number of times and the supply amount of the NH 3 gas it is possible to precisely control the amount of nitrogen present in the HfSiON film to suit the respective process conditions. Accordingly, the carbon content which adversely affects the electrical properties in the HfSiON thin film formed by the present embodiment is reduced, and the content of N increases the thermal stability.
도 11은 본 실시예에 따라 형성된 HfSiON막과 종래 방법에 따라 형성된 HfSiO막의 박막내의 탄소 함유량을 토프-심스(Tof- SIMS) 비교하여 나타낸 그래프이다. 토프-심스(Secondary Ion Mass Spectrometer) 분석은 원소의 정성적 분석 및 정량적 분석에 사용되는 분석 방법의 하나이다. 종래 방법에 따라 형성된 HfSiO막 은, Hf 전구체로서 TEMAH를 1초간 공급한 후 아르곤 가스를 사용하여 1초간 퍼지하고, O3를 3초간 공급한 후 아르곤 가스를 사용하여 3초간 퍼지하고, Si 전구체로서 APTES를 1초간 공급한 후, 아르곤 가스를 사용하여 1초간 퍼지하고, O3를 3초간 공급한 후 아르곤 가스를 사용하여 3초간 퍼지하여 1 사이클을 종료하는 원자층 증착법에 의해 형성된 것이다. Fig. 11 is a graph showing the carbon content in the thin film of the HfSiON film formed according to the present embodiment and the HfSiO film formed according to the conventional method in comparison with Toof-SIMS. Topon-Sims (Secondary Ion Mass Spectrometer) analysis is one of the analytical methods used for qualitative and quantitative analysis of elements. The HfSiO film formed according to the conventional method is supplied with TEMAH as Hf precursor for 1 second, then purged for 1 second using argon gas, for 3 seconds after supplying O 3 for 3 seconds, and purged for 3 seconds using argon gas, and as a Si precursor. After the APTES is supplied for 1 second, it is purged for 1 second using argon gas, and for 3 seconds after supplying O 3 for 3 seconds, and then formed by the atomic layer deposition method in which one cycle is terminated by argon gas.
도 11을 참조하면, 그래프의 가로축은 형성된 고유전막인 HfSiON막을 상측으로부터 스퍼터링하여 식각함에 있어서 그 식각시간을 나타내며, 세로축은 HfSiON 박막으로부터 분석되는 탄소함량에 대한 인텐시티로서 상대적인 값이다. 도 11에서 NH3 가스를 사용하지 않은 종래 방법(□)에 비하여 NH3 가스를 첨가가스로 사용하는 본 발명(○)의 경우 누설전류에 악 영향을 미치는 탄소 함량이 현저히 감소하였음을 알 수 있다.Referring to FIG. 11, the horizontal axis represents the etching time in sputtering and etching the HfSiON film formed as a high dielectric film from the upper side, and the vertical axis is a relative value as intensity for the carbon content analyzed from the HfSiON thin film. The carbon content on the evil influence on the leakage current in the case of the present invention (○) using the NH 3 gas as additive gas in comparison with the conventional method (□) did not use the NH 3 gas it can be seen that significantly was reduced from 11 .
도 12는 본 실시예에 따라 형성된 HfSiON막과 종래 방법에 따라 형성된 HfSiO막의 박막내의 질소 함유량을 토프-심스(Tof- SIMS) 비교하여 나타낸 그래프이다. 종래 방법에 따라 형성된 HfSiO막은, 도 11과 관련하여 전술한 바의 원자층 증착법에 의해 형성된 것이다. FIG. 12 is a graph showing the comparison of the nitrogen content in the thin film of the HfSiON film formed according to the present embodiment and the HfSiO film formed according to the conventional method in a Tof-SIMS comparison. The HfSiO film formed according to the conventional method is formed by the atomic layer deposition method described above with reference to FIG.
도 13를 참조하면, 그래프의 가로축은 형성된 고유전막인 HfSiON막을 상측으로부터 스퍼터링하여 식각함에 있어서 그 식각시간을 나타내며, 세로축은 HfSiON 박막으로부터 분석되는 질소 함량에 대한 인텐시티로서 상대적인 값이다. 도 12에서 NH3 가스를 사용하지 않은 종래 방법(□)에 비하여 NH3 가스를 첨가가스로 사용 하는 본 발명(○)의 경우 외부의 별도의 열처리 공정 없이도 적당량의 질소가 함유되어 있는 것을 볼 수 있다. 일부 두께에서는 종래 방법에 비하여 3배 이상의 질소 함량을 포함하고 있음을 알 수 있다.Referring to FIG. 13, the horizontal axis represents the etching time in sputtering and etching the HfSiON film formed as a high dielectric film from the upper side, and the vertical axis is a relative value as intensity for nitrogen content analyzed from the HfSiON thin film. In the present invention (○) using the NH 3 gas as an additive gas as compared to the conventional method (□) that does not use the NH 3 gas in Figure 12 it can be seen that the appropriate amount of nitrogen is contained without an external heat treatment process have. It can be seen that some thicknesses contain more than three times the nitrogen content of the conventional methods.
도 4 내지 도 10은 본 발명의 다른 실시예들에 따라 원자층 증착법으로 고유전막을 형성하는 경우 공급되는 가스 펄싱 다이아그램들이다. 각 실시예들에 대하여는 도 3의 실시예와 비교하여 간략히 설명한다. 본 발명의 각 실시예에서는 기본적으로 원자층 증착법의 1 사이클 내에 제1 소오스가스(TEMAH) 공급 단계 - 제1 반응가스(O3) 공급 단계 - 제2 소오스가스(APTES) 공급 단계 - 제2 반응가스(O3) 공급 단계를 포함하며, 각 실시예는 첨가가스(NH3) 공급 단계의 시기와 퍼지 단계의 여부 및 시기등에 따라서 다양하게 구성할 수 있다. 4 to 10 are gas pulsing diagrams supplied when a high dielectric film is formed by atomic layer deposition in accordance with other embodiments of the present invention. Each embodiment will be briefly described in comparison with the embodiment of FIG. 3. In each embodiment of the present invention, the first source gas (TEMAH) supply step-the first reaction gas (O 3 ) supply step-the second source gas (APTES) supply step-the second reaction basically within one cycle of atomic layer deposition Gas (O 3 ) supply step, each embodiment can be configured in various ways depending on the timing of the addition gas (NH 3 ) supply step and whether or not the purge step.
즉, 첨가가스의 공급 단계를 제1 소오스가스(TEMAH) 공급 단계와 제1 반응가스(O3) 공급 단계 사이, 제1 반응가스 공급 단계와 제2 소오스가스(APTES) 공급 단계 사이, 제2 소오스가스 공급 단계와 제2 반응가스(O3) 공급 단계 사이, 제2 반응가스 공급 단계와 2번 째 사이클의 제1 소오스가스 공급 단계 사이 중에서 1 사이클당 적어도 1회이상 수행할 수 있다. That is, the supplying of the additive gas may be performed between the first source gas (TEMAH) supplying step and the first reaction gas (O 3 ) supplying step, the first reaction gas supplying step and the second source gas (APTES) supplying step, and the second step. may perform source gas supply step and the second reaction gas (O 3) at least once or more per one cycle in between feed steps, a second reaction gas supply step and the second source and the first gas supply step of second cycle time.
또한, 첨가가스 공급 단계는 제2 소오스가스 공급 단계의 전후에 적어도 1회 이상 수행할 수 있으며, 보다 구체적으로는 제1 소오스가스 공급 단계와 제1 반응가스 공급 단계 사이 및 제2 소오스가스 공급 단계와 제2 반응가스 공급 단계 사이에서 수행하거나, 제1 소오스가스 공급 단계와 제1 반응가스 공급 단계 사이 및 제 2 반응가스 공급 단계 후에 수행하거나, 제1 반응가스 공급 단계와 제2 소오스가스 공급 단계 사이 및 상기 제2 소오스가스 공급 단계와 제2 반응가스 공급 단계 사이에서 수행하거나, 제1 반응가스 공급 단계와 제2 소오스가스 공급 단계 사이 및 제2 반응가스 공급 단계 후에 수행할 수 있다.Further, the addition gas supplying step may be performed at least once or more before and after the second source gas supplying step, more specifically, between the first source gas supplying step and the first reactive gas supplying step and the second source gas supplying step And between the second reaction gas supply step, or between the first source gas supply step and the first reaction gas supply step and after the second reaction gas supply step, or the first reaction gas supply step and the second source gas supply step And between the second source gas supply step and the second reaction gas supply step, or between the first reaction gas supply step and the second source gas supply step and after the second reaction gas supply step.
또한, 본 발명에서 첨가가스 공급 단계는 원자층 증착법의 1 사이클 내의 각 단계, 즉 제1 소오스가스(TEMAH) 공급 단계, 제1 반응가스(O3) 공급 단계, 제2 소오스가스(APTES) 공급 단계, 제2 반응가스(O3) 공급 단계 중의 적어도 하나의 단계와 동시에 수행할 수 있으며, 모든 단계에서 수행할 수도 있다.Further, in the present invention, the addition gas supplying step may include each step within one cycle of atomic layer deposition, that is, supplying a first source gas (TEMAH), supplying a first reaction gas (O 3 ), and supplying a second source gas (APTES). It may be carried out at the same time as at least one of the step, the second reaction gas (O 3 ) supply step, it may be carried out in all steps.
한편, 본 발명의 실시예들에서 퍼지 단계는 원자층 증착법의 1 사이클 내의 제1 소오스가스 공급 단계, 제1 반응가스 공급 단계, 제2 소오스가스 공급 단계, 제2 반응가스 공급 단계 등의 각 단계를 수행한 후에 모두 수행할 수 있으며, 첨가가스 공급 단계 수행후에도 수행할 수 있다. 또한 첨가가스의 수행 단계가 바로 이어지는 제1 소오스가스 공급 단계 또는 제1 반응가스 공급 단계 등에서는 퍼지 단계를 생략할 수도 있다. Meanwhile, in the embodiments of the present invention, the purge step may include steps of supplying a first source gas, supplying a first reactant gas, supplying a second source gas, and supplying a second reactant gas within one cycle of the atomic layer deposition method. After performing all can be performed, even after performing the addition gas supply step. In addition, the purge step may be omitted in the first source gas supply step or the first reactant gas supply step immediately following the step of performing the additive gas.
도 4를 참조하면, 제1 소오스가스(TEMAH) 공급 - 퍼지가스(Ar) 공급 - 첨가가스(NH3) 공급 - 제1 반응가스(O3) 공급 - 퍼지가스(Ar) 공급 - 제2 소오스가스(APTES) 공급 - 퍼지가스(Ar) 공급 - 제2 반응가스(O3) 공급 - 퍼지가스(Ar) 공급을 1 사이클로 하여 원자층 증착법을 수행하여 HfSiON 막을 형성하는 것을 나타낸다. 도 3의 실시예와 비교하여 제1 소오스가스를 공급한 후 퍼지 단계가 추가된 반면에 첨가가스를 공급한 후 퍼지 단계를 수행하지 않고 바로 반응가스를 공급한다는 점에서 차이가 있다. Referring to FIG. 4, a first source gas (TEMAH) supply-purge gas (Ar) supply-additive gas (NH 3 ) supply-first reaction gas (O 3 ) supply-purge gas (Ar) supply-second source A gaseous (APTES) supply-purge gas (Ar) supply-second reaction gas (O 3 ) supply-purge gas (Ar) supply is performed by the atomic layer deposition method with one cycle to form an HfSiON film. Compared with the embodiment of FIG. 3, the purge step is added after supplying the first source gas, while the reaction gas is supplied immediately without performing the purge step after supplying the additive gas.
도 5를 참조하면, 제1 소오스가스 공급 - 첨가가스 공급 - 제1 반응가스 공급 - 퍼지가스 공급 - 제2 소오스가스 공급 - 퍼지가스 공급 - 제2 반응가스 공급 - 퍼지가스 공급을 1 사이클로 하여 원자층 증착법을 수행하여 HfSiON 막을 형성하는 것을 나타낸다. 도 3의 실시예와 비교하여 제1 소오스가스를 공급한 후 퍼지 단계가 추가되지 않고 바로 첨가가스를 공급하며, 제1 반응가스를 공급한 후 퍼지 단계를 수행한다는 점에서 차이가 있다. Referring to FIG. 5, the first source gas supply-the additive gas supply-the first reaction gas supply-the purge gas supply-the second source gas supply-the purge gas supply-the second reactant gas supply-the purge gas supply as an atom A layer deposition method is performed to form an HfSiON film. Compared to the embodiment of FIG. 3, the first source gas is supplied and the purge step is not added, and the additional gas is supplied immediately, and the purge step is performed after the first reaction gas is supplied.
도 6을 참조하면, 제1 소오스가스 공급 - 첨가가스 공급 - 제1 반응가스 공급 - 퍼지가스 공급 - 제2 소오스가스 공급 - 첨가가스 공급 - 퍼지가스 공급 - 제2 반응가스 공급 - 퍼지가스 공급을 1 사이클로 하여 원자층 증착법을 수행하여 HfSiON 막을 형성하는 것을 나타낸다. 도 5의 실시예와 비교하여 첨가가스를 공급하는 단계가 제2 소오스가스 공급후에 한 번 더 추가된다는 점에서 차이가 있다.Referring to FIG. 6, the first source gas supply-the additive gas supply-the first reaction gas supply-the purge gas supply-the second source gas supply-the additive gas supply-the purge gas supply-the second reaction gas supply-the purge gas supply It shows that HfSiON film | membrane is formed by carrying out atomic layer deposition method by one cycle. Compared with the embodiment of FIG. 5, there is a difference in that the step of supplying the additive gas is added once more after the second source gas supply.
도 7을 참조하면, 제1 소오스가스 공급 - 퍼지가스 공급 - 제1 반응가스 공급 - 첨가가스 공급 - 퍼지가스 공급 - 제2 소오스가스 공급 - 퍼지가스 공급 - 제2 반응가스 공급 - 퍼지가스 공급을 1 사이클로 하여 원자층 증착법을 수행하여 HfSiON 막을 형성하는 것을 나타낸다. 도 3의 실시예와 비교하여 첨가가스를 공급하는 단계가 제1 반응가스 공급 단계 수행된다는 점에서 차이가 있다.Referring to FIG. 7, a first source gas supply-purge gas supply-first reaction gas supply-additive gas supply-purge gas supply-second source gas supply-purge gas supply-second reaction gas supply-purge gas supply It shows that HfSiON film | membrane is formed by carrying out atomic layer deposition method by one cycle. Compared with the embodiment of FIG. 3, the step of supplying the additive gas is different in that the first reaction gas supply step is performed.
도 8을 참조하면, 제1 소오스가스 공급/첨가가스 공급 - 퍼지가스 공급 - 제1 반응가스 공급 - 퍼지가스 공급 - 제2 소오스가스 공급 - 퍼지가스 공급 - 제2 반응가스 공급 - 퍼지가스 공급을 1 사이클로 하여 원자층 증착법을 수행하여 HfSiON 막을 형성하는 것을 나타낸다. 도 3의 실시예와 비교하여 첨가가스를 공급하는 단계가 제1 소오스가스 공급 단계와 동시에 수행된다는 점에서 차이가 있다. Referring to FIG. 8, the first source gas supply / addition gas supply-purge gas supply-first reaction gas supply-purge gas supply-second source gas supply-purge gas supply-second reaction gas supply-purge gas supply It shows that HfSiON film | membrane is formed by carrying out atomic layer deposition method by one cycle. Compared with the embodiment of FIG. 3, there is a difference in that the supplying of additional gas is performed simultaneously with the first source gas supplying step.
도 9를 참조하면, 제1 소오스가스 공급 - 퍼지가스 공급 -첨가가스 공급/제1반응가스 공급 - 퍼지가스 공급 - 제2 소오스가스 공급 - 퍼지가스 공급 - 제2 반응가스 공급 - 퍼지가스 공급을 1 사이클로 하여 원자층 증착법을 수행하여 HfSiON 막을 형성하는 것을 나타낸다. 도 8의 실시예와 비교하여 첨가가스를 공급하는 단계가 제1 반응가스 공급 단계와 동시에 수행된다는 점에서 차이가 있다.9, the first source gas supply-purge gas supply-additive gas supply / first reaction gas supply-purge gas supply-second source gas supply-purge gas supply-second reaction gas supply-purge gas supply It shows that HfSiON film | membrane is formed by carrying out atomic layer deposition method by one cycle. Compared with the embodiment of FIG. 8, there is a difference in that the supplying of additional gas is performed simultaneously with the first reaction gas supplying step.
도 10을 참조하면, 제1 소오스가스 공급 - 퍼지가스 공급 - 제1 반응가스 공급 - 퍼지가스 공급 - 제2 소오스가스 공급/첨가가스 공급 - 퍼지가스 공급 - 제2 반응가스 공급 - 퍼지가스 공급을 1 사이클로 하여 원자층 증착법을 수행하여 HfSiON 막을 형성하는 것을 나타낸다. 도 8의 실시예와 비교하여 첨가가스를 공급하는 단계가 제2 소오스가스 공급 단계와 동시에 수행된다는 점에서 차이가 있다.Referring to FIG. 10, the first source gas supply-purge gas supply-first reaction gas supply-purge gas supply-second source gas supply / additive gas supply-purge gas supply-second reaction gas supply-purge gas supply It shows that HfSiON film | membrane is formed by carrying out atomic layer deposition method by one cycle. Compared with the embodiment of FIG. 8, there is a difference in that the supplying of additional gas is performed simultaneously with the second source gas supplying step.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다. 즉, 상기 제1 소오스가스는 Hf를 포함하는 Hf 전구체에 대하여 설명하였지만 Zr, La, Ta, Sr, Ti 중 어느 하나를 포함하는 전구체를 사용할 수 있음은 물론이며, 상기 제2 소오스가스는 Si 전구체를 예로 들어 설명하였지만, Ti, Al, 중 어느 하나를 포함하는 전구체를 사용할 수 있다. 따라 서, 본 발명에 따른 고유전막 형성 방법에 의해 형성되는 고유전막은 HfSiON 뿐만아니라 ZrSiO, LaSiO, HfTaO, TaTiO, SrTiO3, TiAlO, HfAlO 또는 HfTiO 에 질소가 첨가된 단일막 또는 이들의 복합막일 수 있다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge. That is, although the first source gas has been described with respect to the Hf precursor including Hf, a precursor including any one of Zr, La, Ta, Sr, and Ti may be used, and the second source gas may be a Si precursor. Although described as an example, it is possible to use a precursor containing any one of Ti, Al. Therefore, the high-k dielectric film formed by the high-k dielectric film formation method according to the present invention may be a single film or a composite film in which nitrogen is added to ZrSiO, LaSiO, HfTaO, TaTiO, SrTiO 3 , TiAlO, HfAlO, or HfTiO as well as HfSiON. have.
또한, 도 12에서 보여지는 고유전막 내에 첨가된 질소의 함량의 조절은 원자층 증착법의 1사이클당 상기 질소 성분을 함유한 첨가가스의 공급 횟수, 공급시간 및 공급량 중의 적어도 하나를 조절함으로써 수행될 수 있다.In addition, the adjustment of the content of nitrogen added in the high-k dielectric film shown in FIG. 12 may be performed by adjusting at least one of the number of times, supply time and supply amount of the additive gas containing the nitrogen component per cycle of atomic layer deposition. have.
한편, 본 발명의 실시예는 게이트구조의 유전막으로 사용하는 고유전막에 관하여 상술하였지만, 반도체 메모리 소자에서 커패시터의 유전막으로 사용되는 고유전막에 대하여도 동일하게 적용할 수 있음은 물론이다.Meanwhile, although the embodiment of the present invention has been described above with respect to the high dielectric film used as the dielectric film of the gate structure, the same applies to the high dielectric film used as the dielectric film of the capacitor in the semiconductor memory device.
본 발명에 따르면, 도 11에서 알 수 있듯이, 종래 기술과 비교하여 형성된 고유전막내에 탄소의 함량이 현격히 감소되어 소자의 누설전류 특성이 매우 향상되었다.According to the present invention, as can be seen in Figure 11, compared with the prior art, the content of carbon in the high dielectric film formed is significantly reduced, the leakage current characteristics of the device is greatly improved.
또한, 도 12에서 알 수 있듯이, 종래기술과 비교하여 고유전막 내의 질소 함량이 매우 증가하였으며, 질소 함량 및 분포를 매우 정밀하게 조절할 수 있어서 채널 이동도 등의 소자의 특성을 향상시킬 수 있으며, 고유전막의 열적 안정성이 향상되었다.In addition, as can be seen in Figure 12, compared with the prior art, the nitrogen content in the high-k dielectric layer is very increased, and the nitrogen content and distribution can be adjusted very precisely, thereby improving the characteristics of the device such as channel mobility, The thermal stability of the entire membrane was improved.
Claims (40)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050020134A KR100640638B1 (en) | 2005-03-10 | 2005-03-10 | Method for forming high dielectric film by atomic layer deposition and method of fabricating semiconductor device having high dielectric film |
| US11/359,404 US7521331B2 (en) | 2005-03-10 | 2006-02-23 | High dielectric film and related method of manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020050020134A KR100640638B1 (en) | 2005-03-10 | 2005-03-10 | Method for forming high dielectric film by atomic layer deposition and method of fabricating semiconductor device having high dielectric film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20060099105A true KR20060099105A (en) | 2006-09-19 |
| KR100640638B1 KR100640638B1 (en) | 2006-10-31 |
Family
ID=36971572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020050020134A KR100640638B1 (en) | 2005-03-10 | 2005-03-10 | Method for forming high dielectric film by atomic layer deposition and method of fabricating semiconductor device having high dielectric film |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7521331B2 (en) |
| KR (1) | KR100640638B1 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100722843B1 (en) * | 2005-11-30 | 2007-05-30 | 주식회사 아이피에스 | Method of depositing thin film |
| KR100942958B1 (en) * | 2006-09-29 | 2010-02-17 | 주식회사 하이닉스반도체 | Method for forming thin film and method for forming capacitor of semiconductor device using the same |
| US8557713B2 (en) | 2008-05-23 | 2013-10-15 | Samsung Electronics Co., Ltd. | Semiconductor devices and method of forming the same |
| KR20190019979A (en) * | 2011-11-04 | 2019-02-27 | 에이에스엠 인터내셔널 엔.브이. | Methods for forming doped silicon oxide thin films |
| KR20190132039A (en) * | 2018-05-18 | 2019-11-27 | 서울대학교산학협력단 | Method for forming hafnium oxynitride film and semiconductor device using the same |
Families Citing this family (36)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8507389B2 (en) * | 2009-07-17 | 2013-08-13 | Applied Materials, Inc. | Methods for forming dielectric layers |
| US9997357B2 (en) | 2010-04-15 | 2018-06-12 | Lam Research Corporation | Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors |
| US9373500B2 (en) | 2014-02-21 | 2016-06-21 | Lam Research Corporation | Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications |
| US9611544B2 (en) | 2010-04-15 | 2017-04-04 | Novellus Systems, Inc. | Plasma activated conformal dielectric film deposition |
| US8956983B2 (en) | 2010-04-15 | 2015-02-17 | Novellus Systems, Inc. | Conformal doping via plasma activated atomic layer deposition and conformal film deposition |
| US9390909B2 (en) | 2013-11-07 | 2016-07-12 | Novellus Systems, Inc. | Soft landing nanolaminates for advanced patterning |
| US20110256734A1 (en) | 2010-04-15 | 2011-10-20 | Hausmann Dennis M | Silicon nitride films and methods |
| US9257274B2 (en) | 2010-04-15 | 2016-02-09 | Lam Research Corporation | Gapfill of variable aspect ratio features with a composite PEALD and PECVD method |
| US9892917B2 (en) | 2010-04-15 | 2018-02-13 | Lam Research Corporation | Plasma assisted atomic layer deposition of multi-layer films for patterning applications |
| US9076646B2 (en) | 2010-04-15 | 2015-07-07 | Lam Research Corporation | Plasma enhanced atomic layer deposition with pulsed plasma exposure |
| US8637411B2 (en) | 2010-04-15 | 2014-01-28 | Novellus Systems, Inc. | Plasma activated conformal dielectric film deposition |
| US9685320B2 (en) | 2010-09-23 | 2017-06-20 | Lam Research Corporation | Methods for depositing silicon oxide |
| US8524612B2 (en) | 2010-09-23 | 2013-09-03 | Novellus Systems, Inc. | Plasma-activated deposition of conformal films |
| US9123530B2 (en) | 2011-03-23 | 2015-09-01 | Hitachi Kokusai Electric Inc. | Method of manufacturing semiconductor device, substrate processing method and substrate processing apparatus |
| US8647993B2 (en) | 2011-04-11 | 2014-02-11 | Novellus Systems, Inc. | Methods for UV-assisted conformal film deposition |
| US8592328B2 (en) | 2012-01-20 | 2013-11-26 | Novellus Systems, Inc. | Method for depositing a chlorine-free conformal sin film |
| US8728955B2 (en) | 2012-02-14 | 2014-05-20 | Novellus Systems, Inc. | Method of plasma activated deposition of a conformal film on a substrate surface |
| US9355839B2 (en) | 2012-10-23 | 2016-05-31 | Lam Research Corporation | Sub-saturated atomic layer deposition and conformal film deposition |
| JP6538300B2 (en) | 2012-11-08 | 2019-07-03 | ノベラス・システムズ・インコーポレーテッドＮｏｖｅｌｌｕｓ Ｓｙｓｔｅｍｓ Ｉｎｃｏｒｐｏｒａｔｅｄ | Method for depositing a film on a sensitive substrate |
| SG2013083241A (en) | 2012-11-08 | 2014-06-27 | Novellus Systems Inc | Conformal film deposition for gapfill |
| KR102106885B1 (en) | 2013-03-15 | 2020-05-06 | 삼성전자 주식회사 | Precursors for deposition of silicon dioxide film, and method for fabricating semiconductor device using the same |
| US9214334B2 (en) | 2014-02-18 | 2015-12-15 | Lam Research Corporation | High growth rate process for conformal aluminum nitride |
| US9478411B2 (en) | 2014-08-20 | 2016-10-25 | Lam Research Corporation | Method to tune TiOx stoichiometry using atomic layer deposited Ti film to minimize contact resistance for TiOx/Ti based MIS contact scheme for CMOS |
| US9478438B2 (en) | 2014-08-20 | 2016-10-25 | Lam Research Corporation | Method and apparatus to deposit pure titanium thin film at low temperature using titanium tetraiodide precursor |
| US9564312B2 (en) | 2014-11-24 | 2017-02-07 | Lam Research Corporation | Selective inhibition in atomic layer deposition of silicon-containing films |
| US10566187B2 (en) | 2015-03-20 | 2020-02-18 | Lam Research Corporation | Ultrathin atomic layer deposition film accuracy thickness control |
| US9502238B2 (en) | 2015-04-03 | 2016-11-22 | Lam Research Corporation | Deposition of conformal films by atomic layer deposition and atomic layer etch |
| US10526701B2 (en) | 2015-07-09 | 2020-01-07 | Lam Research Corporation | Multi-cycle ALD process for film uniformity and thickness profile modulation |
| KR102350589B1 (en) | 2015-08-24 | 2022-01-14 | 삼성전자주식회사 | Method of forming thin film and method of manufacturing integrated circuit device using the same |
| US9773643B1 (en) | 2016-06-30 | 2017-09-26 | Lam Research Corporation | Apparatus and method for deposition and etch in gap fill |
| US10062563B2 (en) | 2016-07-01 | 2018-08-28 | Lam Research Corporation | Selective atomic layer deposition with post-dose treatment |
| US10037884B2 (en) | 2016-08-31 | 2018-07-31 | Lam Research Corporation | Selective atomic layer deposition for gapfill using sacrificial underlayer |
| CN109390394B (en) * | 2017-08-03 | 2022-08-02 | 联华电子股份有限公司 | Tunneling field effect transistor and manufacturing method thereof |
| US10269559B2 (en) | 2017-09-13 | 2019-04-23 | Lam Research Corporation | Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer |
| WO2021097812A1 (en) * | 2019-11-22 | 2021-05-27 | Yangtze Memory Technologies Co., Ltd. | Memory device and hybrid spacer thereof |
| JP2022094106A (en) * | 2020-12-14 | 2022-06-24 | キオクシア株式会社 | Semiconductor device |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100363088B1 (en) | 2000-04-20 | 2002-12-02 | 삼성전자 주식회사 | Method of manufacturing barrier metal layer using atomic layer deposition method |
| KR100721503B1 (en) | 2000-06-08 | 2007-05-23 | 에이에스엠지니텍코리아 주식회사 | Method for forming a thin film |
| KR100396694B1 (en) | 2000-07-27 | 2003-09-02 | 주식회사 하이닉스반도체 | Method for forming thin film using atomic layer deposition |
| KR100418569B1 (en) | 2001-12-10 | 2004-02-14 | 주식회사 하이닉스반도체 | Method for forming high dielectric thin film using atomic layer deposition |
| JP3627106B2 (en) | 2002-05-27 | 2005-03-09 | 株式会社高純度化学研究所 | Method for producing hafnium silicate thin film by atomic layer adsorption deposition |
| JP4168775B2 (en) | 2003-02-12 | 2008-10-22 | 株式会社デンソー | Thin film manufacturing method |
| US20040198069A1 (en) * | 2003-04-04 | 2004-10-07 | Applied Materials, Inc. | Method for hafnium nitride deposition |
-
2005
- 2005-03-10 KR KR1020050020134A patent/KR100640638B1/en not_active IP Right Cessation
-
2006
- 2006-02-23 US US11/359,404 patent/US7521331B2/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100722843B1 (en) * | 2005-11-30 | 2007-05-30 | 주식회사 아이피에스 | Method of depositing thin film |
| KR100942958B1 (en) * | 2006-09-29 | 2010-02-17 | 주식회사 하이닉스반도체 | Method for forming thin film and method for forming capacitor of semiconductor device using the same |
| US8557713B2 (en) | 2008-05-23 | 2013-10-15 | Samsung Electronics Co., Ltd. | Semiconductor devices and method of forming the same |
| US8970014B2 (en) | 2008-05-23 | 2015-03-03 | Samsung Electronics Co., Ltd. | Semiconductor devices with dielectric layers |
| KR20190019979A (en) * | 2011-11-04 | 2019-02-27 | 에이에스엠 인터내셔널 엔.브이. | Methods for forming doped silicon oxide thin films |
| KR20190120151A (en) * | 2011-11-04 | 2019-10-23 | 에이에스엠 인터내셔널 엔.브이. | Methods for forming doped silicon oxide thin films |
| KR20190132039A (en) * | 2018-05-18 | 2019-11-27 | 서울대학교산학협력단 | Method for forming hafnium oxynitride film and semiconductor device using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| US20060205186A1 (en) | 2006-09-14 |
| US7521331B2 (en) | 2009-04-21 |
| KR100640638B1 (en) | 2006-10-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100640638B1 (en) | Method for forming high dielectric film by atomic layer deposition and method of fabricating semiconductor device having high dielectric film | |
| KR100555543B1 (en) | Method for forming high dielectric layer by atomic layer deposition and method for manufacturing capacitor having the layer | |
| US8168547B2 (en) | Manufacturing method of semiconductor device | |
| KR101990051B1 (en) | Semiconductor device with fluorine free tungsten barrier layer and method for fabricating the same | |
| US7563729B2 (en) | Method of forming a dielectric film | |
| US20050233598A1 (en) | Method of fabricating high-k dielectric layer having reduced impurity | |
| US20150140838A1 (en) | Two Step Deposition of High-k Gate Dielectric Materials | |
| KR20140028992A (en) | Semiconductor device with tungsten gate electrode and method for fabricating the same | |
| KR100639673B1 (en) | Semiconductor device including a gate dielectric layer formed of a high dielectric alloy and method of fabricating the same | |
| KR20050033831A (en) | Manufacturing method of insulator film and insulator film, and manufacturing method of semiconductor device and semiconductor device | |
| KR100729354B1 (en) | Methods of manufacturing semiconductor device in order to improve the electrical characteristics of a dielectric | |
| US20060240679A1 (en) | Method of manufacturing semiconductor device having reaction barrier layer | |
| KR20050031851A (en) | Method of forming material using atomic layer deposition process, method of forming thin film, and method of forming capacitor using the same | |
| KR100593659B1 (en) | Atomic layer deposition method, method of manufacturing gate structure using same and method of manufacturing capacitor | |
| KR100706803B1 (en) | Semiconductor device and method of forming the same | |
| KR100754012B1 (en) | Method for forming high dielectric thin layer | |
| US20070221968A1 (en) | Transistor of semiconductor device and method for manufacturing the same | |
| KR100755072B1 (en) | Semiconductor device having ternary system oxide gate insulating layer and method of fabricating the same | |
| KR100790567B1 (en) | Semiconductor device having high-k composite gate insulating layer and method of fabricating the same | |
| KR100721202B1 (en) | Semiconductor device having ternary system oxide gate insulating layer and method of fabricating the same | |
| KR100702133B1 (en) | Semiconductor device having TiLaO gate insulating layer and method of fabricating the same | |
| KR100712988B1 (en) | Semiconductor device having talao gate insulating layer and method of fabricating the same | |
| KR100745073B1 (en) | Semiconductor device having HfNbO gate insulating layer and method of fabricating the same | |
| KR20050092368A (en) | Dielectric film forming method | |
| KR100668753B1 (en) | Semiconductor device having high-k gate insulating layer and method of fabricating the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |