KR20060076368A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

Info

Publication number
KR20060076368A
KR20060076368A KR1020040114762A KR20040114762A KR20060076368A KR 20060076368 A KR20060076368 A KR 20060076368A KR 1020040114762 A KR1020040114762 A KR 1020040114762A KR 20040114762 A KR20040114762 A KR 20040114762A KR 20060076368 A KR20060076368 A KR 20060076368A
Authority
KR
South Korea
Prior art keywords
hard mask
gate
forming
trench
film
Prior art date
Application number
KR1020040114762A
Other languages
Korean (ko)
Inventor
이상수
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020040114762A priority Critical patent/KR20060076368A/en
Publication of KR20060076368A publication Critical patent/KR20060076368A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H01L29/42352—Gate electrodes for transistors with charge trapping gate insulator with the gate at least partly formed in a trench
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66719—With a step of forming an insulating sidewall spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 게이트 정렬 마진을 확보할 수 있는 리세스 게이트를 갖는 반도체 소자의 제조방법에 관한 것이다. 본 발명의 방법은, 반도체 기판 상에 액티브 영역의 채널 예정 영역을 노출시키는 하드마스크를 형성하는 단계; 상기 하드마스크의 양측벽에 절연막 스페이서를 형성하는 단계; 상기 스페이서를 포함한 하드마스크를 이용해서 노출된 기판 부분을 식각하여 트렌치를 형성하는 단계; 상기 스페이서와 하드마스크를 제거하는 단계; 상기 트렌치를 포함한 기판 상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상에 트렌치를 매립하도록 도전막을 증착하는 단계; 및 상기 도전막을 패터닝하여 게이트를 형성하는 단계;를 포함한다.The present invention relates to a method for manufacturing a semiconductor device having a recess gate that can secure a gate alignment margin. The method includes forming a hardmask on a semiconductor substrate, the hardmask exposing a channel predetermined region of an active region; Forming insulating film spacers on both sidewalls of the hard mask; Etching the exposed portion of the substrate using a hard mask including the spacer to form a trench; Removing the spacers and the hard mask; Forming a gate oxide film on the substrate including the trench; Depositing a conductive film to fill trenches on the gate oxide film; And forming a gate by patterning the conductive layer.

Description

반도체 소자의 제조방법{Method for manufacturing semiconductor device}Method for manufacturing semiconductor device

도 1은 게이트 정렬 마진을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a gate alignment margin.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.2A to 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

20: 기판 21: 희생 하드마스크20: substrate 21: sacrificial hard mask

22: 희생 스페이서 23: 트렌치22: sacrificial spacer 23: trench

24: 게이트 산화막 25: 폴리실리콘막24: gate oxide film 25: polysilicon film

26: 텅스텐 실리사이드막 27: 하드마스크 질화막26: tungsten silicide film 27: hard mask nitride film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 게이트 정렬 마진을 확보할 수 있는 리세스 게이트를 갖는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a recess gate that can secure a gate alignment margin.

반도체 소자의 고집적화에 따라 필연적으로 게이트의 선폭 감소 및 그에 따른 채널 길이의 감소가 초래되고 있다. 그런데, 채널 길이가 감소되면 문턱전압이 급격하게 줄어드는 단채널효과가 유발되고, 이로 인해, 트랜지스터 및 소자 특성의 저하가 야기된다. 따라서, 반도체 소자의 고집적화를 위해서는 단채널효과의 방지가 반드시 해결되어야 한다.Increasing integration of semiconductor devices inevitably results in a decrease in line width of the gate and a corresponding decrease in channel length. However, when the channel length is reduced, a short channel effect in which the threshold voltage is sharply reduced is caused, resulting in deterioration of transistor and device characteristics. Therefore, the prevention of the short channel effect must be solved for high integration of the semiconductor device.

종래에는 단채널 효과를 방지하기 위해 문턱전압 보상용 이온주입, 할로 이온주입 등을 실시하고 있다. 그러나, 이 방법 또한 집적도 증가에 따른 구조적인 한계에 점차 다다르고 있다.Conventionally, in order to prevent short channel effects, ion implantation and halo ion implantation for threshold voltage compensation are performed. However, this method is also gradually approaching the structural limitations of increasing density.

이에, 최근에는 게이트 형성영역을 식각함으로써 채널길이를 동일면적에서 보다 길게 형성할 수 있는 리세스 게이트를 적용하고 있다.Therefore, recently, a recess gate that can form a channel length longer by the same area by etching the gate formation region is applied.

이러한 리세스 게이트 형성시, 리세스 채널을 형성하기 위한 트렌치의 폭은 게이트 폭에 비해서 훨씬 작게 형성되어야 하는데, 이는 트렌치의 폭이 크면 게이트 정렬시 마진이 감소하여 불량이 발생하기 쉽기 때문이다.In forming the recess gate, the width of the trench for forming the recess channel should be formed to be much smaller than the gate width, since a large trench width reduces the margin at the gate alignment and is likely to cause defects.

도 1은 게이트 정렬의 마진을 설명하기 위한 도면으로서, 도시한 바와 같이, 트렌치 폭이 크면 게이트 정렬 마진이 부족하여 게이트의 작은 오정렬에도 불량이 발생한다.1 is a view for explaining the margin of the gate alignment, as shown in the figure, if the trench width is large, the gate alignment margin is insufficient, even a small misalignment of the gate occurs.

한편, 실례로 90㎚ 급에서 웨이브(Waved)가 적용되었을때 119㎚ 정도의 FICD(final inspection critical dimension)를 갖는다. 이때, 리세스 게이트를 형성하기 위한 트렌치는 수십㎚의 폭을 가져야 한다. 그러나, 90㎚ 급 이상에서의 KrF를 광원으로 사용하는 사진공정 장비가 50㎚ 미만의 트렌치를 안정적으로 정의(define) 하기는 거의 불가능하다. 80㎚ 및 70㎚ 급에서도 기존의 장비로 트렌치를 안정적으로 정의하기 매우 어려우며, ArF를 광원으로 사용하는 상위 사진공 정 장비를 새로 장만하려면 매우 큰 비용이 든다.On the other hand, for example, when the wave (Waved) is applied in 90nm class has a final inspection critical dimension (FICD) of about 119nm. At this time, the trench for forming the recess gate should have a width of several tens nm. However, it is almost impossible for a photolithography apparatus using KrF at 90 nm or more as a light source to stably define a trench smaller than 50 nm. Even at 80 nm and 70 nm, it is very difficult to reliably define a trench with existing equipment, and it is very expensive to rebuild a higher level photo processing equipment using ArF as a light source.

따라서, 본 발명은 상기한 바와 같은 종래기술의 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 게이트 정렬 마진을 확보할 수 있는 리세스 게이트를 갖는 반도체 소자의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having a recess gate that can secure a gate alignment margin.

상기한 바와 같은 목적을 달성하기 위한 본 발명은, 반도체 기판 상에 액티브 영역의 채널 예정 영역을 노출시키는 하드마스크를 형성하는 단계; 상기 하드마스크의 양측벽에 절연막 스페이서를 형성하는 단계; 상기 스페이서를 포함한 하드마스크를 이용해서 노출된 기판 부분을 식각하여 트렌치를 형성하는 단계; 상기 스페이서와 하드마스크를 제거하는 단계; 상기 트렌치를 포함한 기판 상에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상에 트렌치를 매립하도록 도전막을 증착하는 단계; 및 상기 도전막을 패터닝하여 게이트를 형성하는 단계;를 포함한다.According to an aspect of the present invention, there is provided a hard mask for exposing a channel predetermined region of an active region on a semiconductor substrate; Forming insulating film spacers on both sidewalls of the hard mask; Etching the exposed portion of the substrate using a hard mask including the spacer to form a trench; Removing the spacers and the hard mask; Forming a gate oxide film on the substrate including the trench; Depositing a conductive film to fill trenches on the gate oxide film; And forming a gate by patterning the conductive layer.

상기 절연막 스페이서는 질화막으로 이루어진다.The insulating film spacer is formed of a nitride film.

상기 절연막 스페이서는 하드마스크의 두께를 조절하기 위해 하드마스크 상에 질화막을 증착한 후 이를 블랭킷 식각하여 형성한다.The insulating film spacer is formed by depositing a nitride film on the hard mask to control the thickness of the hard mask and then blanket etching the nitride film.

(실시예)(Example)

이하, 첨부한 도면을 참고하여 본 발명의 바람직한 실시예를 상술하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2d는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설 명하기 위한 공정 단면도이다.2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 2a를 참조하면, 기판(20) 상에 질화막을 증착하고, 상기 질화막 상에 감광막을 도포한 후 노광 및 현상공정을 거쳐 리세스 채널 예정 영역의 질화막을 노출시키는 감광막 패턴을 형성한다. 감광막 패턴을 식각마스크로 이용하여 질화막을 식각하여 희생 하드마스크(21)를 형성한다.Referring to FIG. 2A, a nitride film is deposited on the substrate 20, a photoresist film is coated on the nitride film, and a photoresist pattern is formed to expose the nitride film of a predetermined recess channel region through an exposure and development process. The sacrificial hard mask 21 is formed by etching the nitride layer using the photoresist pattern as an etching mask.

도 2b를 참조하면, 상기 희생 하드마스크(21)를 덮도록 기판 상에 질화막을 증착하고, 상기 질화막을 블랭킷 식각하여 희생 하드마스크(21) 양측벽에 희생 스페이서(22)를 형성한다. 여기서, 하드마스크(21) 양측벽에 스페이서(22)를 형성함으로써 하드마스크의 두께를 조절하여 보다 미세한 트렌치를 형성할 수 있다.Referring to FIG. 2B, a nitride film is deposited on a substrate to cover the sacrificial hard mask 21, and the nitride film is blanket-etched to form sacrificial spacers 22 on both sidewalls of the sacrificial hard mask 21. Here, by forming the spacers 22 on both side walls of the hard mask 21, finer trenches may be formed by adjusting the thickness of the hard mask.

도 2c를 참조하면, 상기 희생 스페이서(22)를 마스크로 이용하여 기판을 식각하여 채널 예정 영역에 트렌치(23)를 형성한다. Referring to FIG. 2C, the substrate 23 is etched using the sacrificial spacer 22 as a mask to form a trench 23 in a channel predetermined region.

도 2d를 참조하면, 희생 하드마스크(21) 및 희생 스페이서(22)를 제거하고, 상기 트렌치(23)를 포함한 기판 상에 게이트 산화막(24)을 형성한다. 그런다음, 게이트 산화막(24) 상에 폴리실리콘막(25), 텅스텐 실리사이드막(26) 및 하드마스크 질화막(27)을 차례로 증착한다. Referring to FIG. 2D, the sacrificial hard mask 21 and the sacrificial spacer 22 are removed, and the gate oxide layer 24 is formed on the substrate including the trench 23. Then, a polysilicon film 25, a tungsten silicide film 26, and a hard mask nitride film 27 are sequentially deposited on the gate oxide film 24.

이어서, 상기 하드마스크 질화막(27) 상에 감광막을 도포하고 노광 및 현상 공정을 통해 게이트 영역을 정의하는 감광막 패턴을 형성한다. 계속해서, 상기 감광막 패턴을 식각장벽으로 이용해서 하드마스크 질화막(27), 텅스텐 실리사이드막(26), 폴리실리콘막(25) 및 게이트 산화막(24)을 식각하여 리세스 채널을 갖는 게이트(30)를 형성한다. Subsequently, a photoresist layer is coated on the hard mask nitride layer 27, and a photoresist layer pattern defining a gate region is formed through an exposure and development process. Subsequently, the hard mask nitride layer 27, the tungsten silicide layer 26, the polysilicon layer 25, and the gate oxide layer 24 are etched using the photoresist pattern as an etch barrier to form a gate 30 having a recess channel. To form.                     

여기서, 미세한 트렌치를 형성해 줌으로써 게이트 정렬 마진을 확보하여 불량 발생을 줄일 수 있는 바, 제조 수율을 향상시킬 수 있다. 또한, 희생 하드마스크(21) 양측벽에 희생 스페이서(22)를 형성함으로써, 기존의 장비를 그대로 사용하면서 보다 미세한 트렌치를 형성할 수 있다.Here, by forming a fine trench to secure a gate alignment margin to reduce the occurrence of defects, it is possible to improve the manufacturing yield. In addition, by forming the sacrificial spacers 22 on both side walls of the sacrificial hard mask 21, finer trenches can be formed while the existing equipment is used as it is.

이후, 도시하지는 않았지만, 상기 게이트 양측 기판 내에 불순물 이온주입을 진행하여 접합영역을 형성하고, 공지된 일련의 후속공정들을 차례로 진행하여 반도체 소자의 제조를 완성한다.Subsequently, although not shown, impurity ion implantation is performed in the substrates on both sides of the gate to form a junction region, and a series of known subsequent steps are sequentially performed to complete the manufacture of a semiconductor device.

이상에서와 같이, 본 발명은 미세한 폭의 트렌치를 갖는 리세스 게이트를 형성함으로써, 게이트 정렬 마진을 확보할 수 있다.As described above, the present invention can secure a gate alignment margin by forming a recess gate having a fine width trench.

또한, 본 발명은 하드질화막 및 스페이서를 이용하여 트렌치를 식각함으로써, 기존의 장비를 사용하면서 보다 작은 폭의 트렌치를 갖는 리세스 게이트를 형성할 수 있다.In addition, according to the present invention, the trench may be etched using the hard nitride film and the spacer, thereby forming a recess gate having a smaller trench while using existing equipment.

본 발명을 특정의 바람직한 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니고 이하의 특허청구의 범위에 의해 마련되는 본 발명의 정신이나 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변화될 수 있다는 것을 당 업계에서 통상의 지식을 가진 자는 용이하게 알 수 있다.While the invention has been shown and described with respect to certain preferred embodiments thereof, the invention is not so limited and it is intended that the invention be limited without departing from the spirit or field of the invention as set forth in the following claims It will be readily apparent to one of ordinary skill in the art that various modifications and variations can be made.

Claims (3)

반도체 기판 상에 액티브 영역의 채널 예정 영역을 노출시키는 하드마스크를 형성하는 단계;Forming a hard mask on the semiconductor substrate, the hard mask exposing the channel predetermined region of the active region; 상기 하드마스크의 양측벽에 절연막 스페이서를 형성하는 단계;Forming insulating film spacers on both sidewalls of the hard mask; 상기 스페이서를 포함한 하드마스크를 이용해서 노출된 기판 부분을 식각하여 트렌치를 형성하는 단계;Etching the exposed portion of the substrate using a hard mask including the spacer to form a trench; 상기 스페이서와 하드마스크를 제거하는 단계;Removing the spacers and the hard mask; 상기 트렌치를 포함한 기판 상에 게이트 산화막을 형성하는 단계;Forming a gate oxide film on the substrate including the trench; 상기 게이트 산화막 상에 트렌치를 매립하도록 도전막을 증착하는 단계; 및Depositing a conductive film to fill trenches on the gate oxide film; And 상기 도전막을 패터닝하여 게이트를 형성하는 단계;를 포함하는 반도체 소자의 제조방법.And forming a gate by patterning the conductive layer. 제 1 항에 있어서,The method of claim 1, 상기 절연막 스페이서는 질화막으로 이루어진 것을 특징으로 하는 반도체 소자의 제조방법.The insulating film spacer is a semiconductor device manufacturing method, characterized in that consisting of a nitride film. 제 1 항에 있어서,The method of claim 1, 상기 절연막 스페이서는 하드마스크의 두께를 조절하기 위해 하드마스크 상에 질화막을 증착한 후 이를 블랭킷 식각하여 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The insulating film spacer is a method of manufacturing a semiconductor device, characterized in that the nitride film is deposited on the hard mask to control the thickness of the hard mask and then formed by blanket etching it.
KR1020040114762A 2004-12-29 2004-12-29 Method for manufacturing semiconductor device KR20060076368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020040114762A KR20060076368A (en) 2004-12-29 2004-12-29 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020040114762A KR20060076368A (en) 2004-12-29 2004-12-29 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
KR20060076368A true KR20060076368A (en) 2006-07-04

Family

ID=37168665

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040114762A KR20060076368A (en) 2004-12-29 2004-12-29 Method for manufacturing semiconductor device

Country Status (1)

Country Link
KR (1) KR20060076368A (en)

Similar Documents

Publication Publication Date Title
KR100465596B1 (en) A manufacturing method for semiconductor device
KR100853796B1 (en) Method for fabricating semiconductor device
US7862991B2 (en) Method for fabricating recess pattern in semiconductor device
KR20060076368A (en) Method for manufacturing semiconductor device
KR101031520B1 (en) Method for manufacturing transistor in semiconductor device
KR20200024327A (en) Manufacturing Method of Top Gate Thin Film Transistor
KR100226739B1 (en) Method of manufacturing a semiconductor device
KR100467812B1 (en) Semiconductor device and fabrication method thereof
KR20050034292A (en) Manufacturing method for semiconductor device
KR100743629B1 (en) Method of manufacturing semiconductor device
KR20060000482A (en) Method for forming gate of semiconductor device
KR100314738B1 (en) Method for forming gate electrode in semiconductor device
KR100485933B1 (en) Method for manufacturing nano-gate semiconductor
KR20070001590A (en) Method for forming recessed gate of semiconductor device
KR100336766B1 (en) Manufacturing method for mos transistor
KR100215871B1 (en) Method for fabricating semiconductor device
KR101167192B1 (en) Manufacturing method for high voltage device
KR100486755B1 (en) Method for fabricating fine conducting lines of semiconductor memory device
US20020061625A1 (en) Method of manufacturing a metal oxide semiconductor device
KR100905182B1 (en) Method for manufacturing semiconductor device
KR0140811B1 (en) Fabrication method of transistor
US7902079B2 (en) Method for fabricating recess pattern in semiconductor device
KR100284308B1 (en) How to make static ram cells
KR100537186B1 (en) Method for forming transistor in semiconductor device
KR20080022973A (en) Method for manufacturing semiconductor device

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination