KR20060073739A - Tft substrate - Google Patents

Abstract

The present invention relates to a thin film transistor substrate. In the thin film transistor substrate according to the present invention, a gate wiring and a data wiring are formed, and the gate wiring includes an aluminum (Al) -scandium (Sc) -nickel (Ni) alloy layer. As a result, a thin film transistor substrate including a wiring having a low specific resistance and excellent contact characteristics between the hillock resistance and the transparent conductive film is provided.

Description

Thin Film Transistor Substrate {TFT SUBSTRATE}

1 is a phase diagram of aluminum and scandium,

2a to 2d are photographs showing the change in particle shape of the alloy according to the scandium content,

3 is a plan view of a thin film transistor substrate according to a first embodiment of the present invention;

4 is a cross-sectional view taken along line IV-IV of FIG. 3;

5 to 8 are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a first embodiment of the present invention;

9 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention;

10 is a cross-sectional view taken along the line VII-VII of FIG. 9,

FIG. 11 is a cross-sectional view taken along the line XXXI-XI of FIG. 9;

12A to 19B are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a second embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

22 gate line 26 gate electrode

62: data line 65: source electrode

66: drain electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor substrates, and more particularly, to thin film transistor substrates in which wiring is formed of an aluminum-scandium-nickel alloy.

The liquid crystal display device includes a liquid crystal panel in which liquid crystal is injected between the thin film transistor substrate and the color filter substrate. Since the liquid crystal panel is a non-light emitting device, a backlight unit for supplying light is located at the back of the thin film transistor substrate. Light transmitted from the backlight is adjusted according to the arrangement of liquid crystals.

Recent liquid crystal displays require large screen area, high resolution, and high aperture ratio. As a result, the wirings (gate wirings and data wirings) formed on the thin film transistor substrate are lengthening, while the width thereof is decreasing. In this trend, the high resistivity of the wiring material causes an RC delay, causing a serious problem of distorted image quality.

Metals such as chromium (Cr) and molybdenum-tungsten alloys (MoW), which have been used as wiring materials, have been difficult to be applied to liquid crystal display devices of 20 inches or more due to high resistivity of 10 µΩ / cm or more. Accordingly, there is an increasing demand to use aluminum or an aluminum alloy having a small specific resistance as a wiring material.

By the way, aluminum or aluminum alloy has a high contact resistance with the transparent conductive film has a problem that it is difficult to directly contact, and aluminum has a problem that hillock occurs with this. In order to solve this problem, triple layers such as Mo / Al / Mo or Cr / Al / Cr are used. However, such a laminate structure has a disadvantage in that the production efficiency is lowered, and the deposition process is complicated and the cost is increased.

Accordingly, an object of the present invention is to provide a thin film transistor substrate comprising a wiring having excellent resistivity and low contact resistance and low contact resistance with a transparent conductive film.

The above object is achieved by forming a thin film transistor substrate on which a gate wiring and a data wiring are formed, wherein the gate wiring comprises an aluminum (Al) -scandium (Sc) -nickel (Ni) alloy layer. do.

It is preferable that the said gate wiring is formed in a single layer.

In the aluminum-scandium-nickel alloy layer, the content of scandium and nickel is preferably 0.1 to 10 atomic percent with respect to aluminum, respectively.

It is preferable that the said data wiring is formed including the aluminum- scandium- nickel alloy layer.

The data line is preferably made of a lower aluminum-scandium-nickel alloy layer and an upper chromium layer.

The data line is preferably made of a lower aluminum-scandium-nickel alloy layer and an upper molybdenum layer.                     

Aluminum has the lowest specific resistance among the metals applied to the liquid crystal display and has the advantage of easy mass production. Aluminum has lower resistivity than alloys, but heellock occurs in subsequent high temperature processes, making it difficult to apply as a single layer. AlNd, which is widely used as an aluminum alloy, is expensive and has a problem of cost increase. Accordingly, the present invention seeks to provide an aluminum-scandium-nickel alloy having a relatively low resistivity and preventing hillock and allowing direct contact with the transparent conductive film.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

First, the action of scandium in the aluminum-scandium-nickel alloy according to the present invention will be described with reference to FIGS.

FIG. 1 is a phase diagram of aluminum and scandium, and FIGS. 2A to 2D are photographs showing particle shape changes of aluminum and scandium alloys according to scandium content.

As can be seen in FIG. 1, aluminum and scandium have high solubility and form an intermediate compound of ScAl ₃ . In addition, as shown in Figures 2a to 2d it can be seen that as the content of the scandium increases, the size of the particles is reduced, so that the two metals are uniformly distributed. ScAl ₃ formed by the alloy of the two metals are solidified during the heat treatment acts as nucleation site (site), it is effective to suppress the recrystallization. Therefore, the crystal grains are refined and strength can be improved by uniform distribution of precipitates.

ScAl ₃ formed by adding scandium to aluminum is expected to have the same effect as the intermediate compound of Al ₄ Nd formed by adding neodymium to aluminum to prevent hillock.

As such, scandium serves to prevent heel lock of aluminum.

Next, the action of nickel used in the aluminum-scandium-nickel (AlScNi) alloy will be described.

Aluminum and aluminum-based alloys have a very large contact resistance with indium tin oxide (ITO) or indium zinc oxide (IZO), which are transparent conductive films. Therefore, a molybdenum layer, a chromium layer, etc. are applied as a contact layer of a transparent conductive film.

Unlike aluminum-nedium (AlNd) alloys, the addition of nickel to aluminum-neodymium-nickel (AlNdNi) alloys lowers the contact resistance between IZO and molybdenum to IZO.

Nickel is added to aluminum to suppress the formation of aluminum oxide (Al ₂ O ₃ ) upon contact with IZO deposited in a subsequent process, thereby allowing direct contact between AlNdNi and the transparent conductive film. Nickel in the aluminum-scandium-nickel alloy is expected to have the same effect as AlNdNi.

As such, nickel serves to reduce contact resistance with the transparent conductive film.

The aluminum-scandium-nickel alloy according to the present invention is prevented from heel lock by the action of the scandium as described above, it is possible to directly contact with the transparent conductive film by the action of nickel. In addition, since aluminum is the main component, the specific resistance is relatively low.

In the aluminum-scandium-nickel alloy, the content of scandium and nickel is preferably 0.1 to 10 atomic% with respect to aluminum, respectively. If the content is less than 0.1 atomic%, the contact resistance between Hillock and the transparent conductive film is not sufficiently improved. If the content is more than 10 atomic%, the aluminum content decreases to increase the specific resistance.

Aluminum-scandium-nickel alloys are used for gate wiring and / or data wiring. In the case of the gate wiring, it is preferable to be formed of a single layer of aluminum-scandium-nickel alloy. In the case of data wiring, it is possible to form an aluminum-scandium-nickel alloy, a Cr / AlScNi double layer, a Mo / AlScNi double layer, or the like.

Sputtering is a method of depositing an aluminum-scandium-nickel alloy on a substrate material to form a metal layer.

In the sputtering method, argon gas is injected into a chamber provided with a target electrode made of an aluminum-scandium-nickel alloy to which a high voltage is applied, thereby causing plasma discharge. The argon cation excited by the plasma discharge removes metal atoms from the target electrode, and these metal atoms are bonded to each other on the surface of the substrate material and grow into thin films.

Hereinafter, a thin film transistor substrate and a method of manufacturing the same according to the present invention will be described.

3 is a plan view of a thin film transistor substrate according to a first embodiment of the present invention, and FIG. 4 is a cross-sectional view taken along line IV-IV of the thin film transistor substrate illustrated in FIG. 3. 5 to 8 are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to the first embodiment of the present invention.                     

Gate wirings 22, 24, and 26 are formed on the substrate material 10. Here, the gate wirings 22, 24, and 26 are made of an aluminum-scandium-nickel alloy.

The gate lines 22 and 26 include a gate line 22 extending in the horizontal direction and a gate electrode 26 of the thin film transistor connected to the gate line 22. Here, one end portion 24 of the gate line 22 is extended in width for connection with an external circuit.

On the substrate material 10, a gate insulating film 30 made of silicon nitride (SiNx) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, data wirings 65 and 66 including two layers of first data metal layers 651, 661, and 681 and second data metal layers 652, 662, and 682. , 68). The first data metal layers 651, 661, 681 are aluminum-scandium-nickel alloy layers and the second data metal layers 652, 662, 682 are chromium layers. Although not shown, the data line 62 is a double layer formed of an aluminum-scandium-nickel alloy layer and a chromium layer.

The data lines 62, 65, and 66 are formed in the vertical direction and intersect the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the upper portion of the ohmic contact layer 55. A drain electrode 66 which is separated from the extending source electrode 65 and the source electrode 65 and is formed on the ohmic contact layer 56 opposite to the source electrode 65 with respect to the gate electrode 26. It includes. At this time, one end portion 68 of the data line 62 is extended in width for connection with an external circuit.

A-Si: C: O film or a deposited on the data lines 62, 65, 66, 68 and on the semiconductor layer 40 which is not covered by silicon nitride (SiNx) or plasma enhanced chemical vapor deposition (PECVD) A protective film 70 made of a -Si: O: F film (low dielectric constant CVD film), an arcle-based organic insulating film, and the like is formed. The a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a dielectric constant of 4 or less (the dielectric constant has a value between 2 and 4). The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. Excellent adhesion to another film and step coverage. Moreover, since it is an inorganic CVD film, heat resistance is excellent compared with an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a 4 to 10 times faster process time than the silicon nitride film in terms of deposition rate and etching rate. It is also very advantageous in terms of.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the end portion 68 of the data line, respectively, and the contact portion exposing the end portion 24 of the gate line together with the gate insulating layer 30. The hole 74 is formed.

On the passivation layer 70, a pixel electrode 82 electrically connected to the drain electrode 66 and positioned in the pixel region is formed through the contact hole 76. Further, on the protective film 70, contact auxiliary members 86 and 88 are formed to be connected to the end portion 24 of the gate line and the end portion 68 of the data line, respectively, through the contact holes 74 and 78. Here, the pixel electrode 82 and the contact auxiliary members 86 and 88 are made of a transparent conductive film such as indium tin oxide (ITO) or indium zinc oxide (IZO). That is, the aluminum-scandium-nickel alloy forming the gate line is in direct contact with the transparent conductive film.

3 and 4, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In addition, the pixel electrode 82 may also be formed to overlap the data line 62 to maximize the aperture ratio. Even if the pixel electrode 82 is formed to overlap the data line 62 in order to maximize the aperture ratio, if the low dielectric constant CVD film or the like of the protective film 70 is formed, the parasitic capacitance formed therebetween will be small. I can keep it.

Looking at the manufacturing method of the thin film transistor substrate according to the first embodiment, first, as shown in FIG. 5, a gate metal layer made of aluminum-scandium-nickel alloy is deposited on the substrate material 10, and using a mask Patterning is performed by a photolithography process to form gate lines 22, 24, and 26 including the gate line 22 and the gate electrode 26 and extending in the horizontal direction.

Next, as shown in FIG. 6, the three-layer film of the gate insulating film 30 made of silicon nitride, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively laminated, and the semiconductor layer 40 ) And the doped amorphous silicon layer 50 are photo-etched to form an island-like semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 on the gate electrode 24.

Next, as shown in FIG. 7, first data metal layers 651, 661, and 681 made of an aluminum-scandium-nickel alloy layer are laminated, and then second data metal layers 622, 652, which are chromium layers, are stacked. 662 and 682 are stacked and patterned by a photolithography process using a mask, a source line 62 intersecting the gate line 22 and a source line connected to the data line 62 and extending above the gate electrode 26. A data line, which is separated from the electrode 65 and the source electrode 65, includes a drain electrode 66 facing the source electrode 65 around the gate electrode 26.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIG. 8, the silicon nitride film, the a-Si: C: O film, or the a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film 70. ).

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process, thereby contact holes 74 and 76 exposing the end portion 24 of the gate line, the drain electrode 66 and the end portion 68 of the data line. , 78).                     

3 and 4, the pixel electrode 82 and the contact holes 74 and 78, which are connected to the drain electrode 66 through the contact hole 76 by depositing and etching an ITO or IZO film, are photographed and etched. The contact auxiliary members 86 and 88 which are connected to the end portion 24 of the gate line and the end portion 68 of the data line are respectively formed therethrough. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO or IZO.

The first embodiment described above uses five masks in the manufacture of a thin film transistor substrate, and the second embodiment described below uses four masts.

9 is a plan view of a thin film transistor substrate according to a second embodiment of the present invention, FIG. 10 is a cross-sectional view taken along the line VII-VII of FIG. 9, and FIG. 11 is a sectional view taken along the line VII-XI of FIG. 9. to be. 12A to 19B are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate according to a second embodiment of the present invention.

On the substrate material 10, the gate wirings 22, 24, and 26 made of an alloy layer of aluminum-scandium-nickel are formed as in the first embodiment.

The storage electrode line 28 is formed on the substrate material 10 in parallel with the gate line 22. The sustain electrode line 28 also is made of an aluminum-scandium-nickel alloy layer. The storage electrode line 28 overlaps with the conductor 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves charge storage capability of the pixel. The pixel electrode 82 and the gate line (to be described later) It may not be formed if the holding capacity resulting from the overlap of 22) is sufficient. The same voltage as that of the common electrode of the upper substrate is usually applied to the sustain electrode line 28.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, 26 and the storage electrode line 28 to cover the gate wirings 22, 24, 26 and the storage electrode line 28. .

On the gate insulating layer 30, semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and on the semiconductor patterns 42 and 48, n-type impurities such as phosphorus (P) have a high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, data is formed of two layers of first data metal layers 621, 641, 651, 661, and 681 and second data metal layers 622, 642, 652, 662, and 682. Wirings 62, 64, 65, 66, and 68 are formed. The first data metal layers 621, 641, 651, 661, 681 are aluminum-scandium-nickel alloy layers. The second data metal layers 622, 642, 652, 662, 682 are chromium layer layers. The data line is formed in the vertical direction and is a branch of the data line 62 and the data line 62 which are connected to one end of the data line 62 and have an end portion 68 of the data line to which an image signal from the outside is applied. And a data line portion 62, 68, 65 made of the source electrode 65 of the thin film transistor, and are separated from the data line portions 62, 68, 65 and the channel portion E of the gate electrode 26 or the thin film transistor. ) Also includes the drain electrode 66 of the thin film transistor positioned on the opposite side of the source electrode 65 and the conductor 64 for the storage capacitor located on the storage electrode line 28. When the storage electrode line 28 is not formed, the storage capacitor conductor 64 is also not formed.

The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion C of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has a data wiring and a contact layer. Slightly different from the rest of the pattern. That is, in the channel portion C of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66 and 68, an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD) deposited by silicon nitride or plasma enhanced chemical vapor deposition (PECVD) method Film) or an organic insulating film is formed. The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the end portion 68 of the data line, and the conductor 64 for the storage capacitor. Together, it has a contact hole 74 which exposes the end portion 24 of the gate line.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or indium tin oxide (IZO), and is physically and electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. The pixel electrode 82 is also connected to the storage capacitor conductor 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, on the end portion 24 of the gate line and the end portion 68 of the data line, contact auxiliary members 86 and 88 connected to them through contact holes 74 and 78, respectively, are formed. These contact auxiliary members 86 and 88 complement the adhesion between the ends 24 and 68 and the external circuit device, and serve to protect the ends 24 and 68 of the gate lines and the data lines, respectively, and are also transparent. It is formed of a conductive film. Therefore, the aluminum-scandium-nickel alloy forming the gate line is in direct contact with the transparent conductive film.

Looking at the manufacturing method of the thin film transistor substrate according to the second embodiment, as shown in Figure 12a and 12b as in the first embodiment, the gate metal layer of the aluminum-scandium-nickel alloy layer is laminated, and then photo-etched the gate The gate wiring including the line 22 and the gate electrode 26 and the storage electrode line 28 are formed. At this time, one end portion 24 of the gate line 22 connected to the external circuit has a wider width.

Next, as shown in FIGS. 13A and 13B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 using chemical vapor deposition. Å, 300 600 to 600 연속 of continuous deposition, followed by forming a first conductive film 601 made of an aluminum-scandium-nickel alloy layer to form a data line, followed by a second layer of chromium layer The conductive film 602 is deposited by a method such as sputtering to form the conductor layer 60, and then the photosensitive film 110 is applied thereon with a thickness of 1 μm to 2 μm.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 13A and 13B. At this time, the channel portion C of the photosensitive film patterns 112 and 114, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, is the data wiring portion A, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second portion 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion C to the thickness of the photoresist film 112 remaining in the data wiring portion A should be different depending on the process conditions in the etching process described later. It is preferable that the thickness of the first portion 114 is 1/2 or less of the thickness of the second portion 112, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position, and in order to control the light transmittance in the A region, a slit or lattice pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all the polymer molecules are decomposed, so it should not be so.

This thin photoresist film 114 is developed using a photoresist film made of a reflowable material and exposed with a conventional mask that is divided into a part that can completely transmit light and a part that can not completely transmit light. It may be formed by reflowing a portion of the photosensitive film to a portion where the photosensitive film does not remain.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. At this time, the data wiring and the lower layers thereof remain in the data wiring portion A, only the semiconductor layer should remain in the channel portion C, and the upper three layers 60 and 50 in the remaining portion B. , 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 14A and 14B, the conductor layer 60 exposed to the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, and thus the photoresist patterns 112 and 114 may be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

This leaves only the conductor layer of the channel portion C and the data wiring portion A, that is, the source / drain conductor pattern 67 and the storage capacitor conductor 64, as shown in Figs. 15A and 15B. The conductor layer 60 of the other portion B is all removed to reveal the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 are the same as those of the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. . In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Subsequently, as shown in FIGS. 16A and 16B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 below it are simultaneously removed together with the first portion 114 of the photosensitive film by a dry etching method. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

This removes the first portion 114 of the channel portion C, revealing the source / drain conductor pattern 67, as shown in FIGS. 16A and 16B, and the intermediate layer 50 of the other portion B. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data line portion C is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductors 64, respectively.

Subsequently, ashing removes photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion C.

Next, as illustrated in FIGS. 17A and 17B, the source / drain conductor pattern 67 of the channel portion C and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the intermediate layer pattern 57 is large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in C). In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include a mixture gas of CF ₄ and HCl or a mixture gas of CF ₄ and O ₂ , and CF ₄ and O ₂ . The semiconductor pattern 42 may be left at a uniform thickness. In this case, as shown in FIG. 16B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to some extent. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the second photoresist layer 112 remaining in the data wiring portion A is removed. However, the removal of the second portion 112 may be performed after removing the conductor pattern 67 for the channel portion C source / drain and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 18A and 18B, a silicon nitride, an a-Si: C: O film, or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film. Form 70.

19A to 19B, the protective film 70 is photo-etched together with the gate insulating film 30 to form a drain electrode 66, an end portion 24 of the gate line, an end portion 68 of the data line, and the like. Contact holes 76, 74, 78 and 72 are respectively formed to expose the conductor 64 for the storage capacitor.

Finally, as shown in FIGS. 10 and 11, a pixel connected to the drain electrode 66 and the storage capacitor conductor 64 by depositing and photolithography an ITO layer or an IZO layer having a thickness of 400 kHz to 500 kHz. The data contact assistant member 88 connected to the electrode 82, the end portion 24 of the gate line and the gate contact assistant member 86, and the end portion 68 of the data line are formed.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is the metal film 24 exposed through the contact holes 72, 74, 76, and 78. This is to prevent the metal oxide film from being formed on the upper portions of 64, 66 and 68.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

The thin film transistor substrate according to the present invention may be used in a display device such as a liquid crystal display device or an organic light emitting diode.

The organic electroluminescent device is a self-luminous device using an organic material that emits light upon receiving an electrical signal. In the organic electroluminescent device, a cathode layer (pixel electrode), a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and an anode layer (counter electrode) are stacked. The drain electrode of the TFT substrate according to the present invention may be electrically connected to the cathode layer to apply a data signal.

As described above, according to the present invention, a thin film transistor substrate including a wiring having a low resistivity and preventing hillock and allowing direct contact with a transparent conductive film is provided.

Claims (6)

In the thin film transistor substrate on which the gate wiring and the data wiring are formed, The gate wiring is formed of a thin film transistor substrate comprising an aluminum (Al)-scandium (Sc)-nickel (Ni) alloy layer. The method of claim 1, The gate wiring is a thin film transistor substrate, characterized in that formed in a single layer. The method of claim 1, In the aluminum-scandium-nickel alloy layer, The content of scandium and nickel is a thin film transistor substrate, characterized in that 0.1 to 10 atomic percent with respect to aluminum, respectively. The method of claim 1, The data line is a thin film transistor substrate comprising an aluminum-scandium-nickel alloy layer. The method of claim 4, wherein The data line is a thin film transistor substrate, characterized in that consisting of a lower aluminum- scandium- nickel alloy layer and the upper chromium layer. The method of claim 4, wherein The data line is a thin film transistor substrate, characterized in that consisting of a lower aluminum- scandium- nickel alloy layer and the upper molybdenum layer.

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