KR20050079430A - Method of forming aluminium wiring in tft lcd substrate and tft lcd substrate wiring thereby - Google Patents

Abstract

The present invention relates to a method for forming aluminum wiring of a TFT LCD substrate and a TFT LCD substrate using the same. The aluminum wiring method of a TFT LCD substrate according to the present invention comprises the steps of depositing an aluminum nitride layer containing nitrogen on a substrate material in an atmosphere in which a precursor gas of nitrogen is present, and depositing an aluminum layer on top of the aluminum nitride layer. Characterized in that it comprises a step. Thereby, the TFT LCD substrate containing the aluminum wiring excellent in the hillock resistance can be formed.

Description

METHOD OF FORMING ALUMINIUM WIRING IN TFT LCD SUBSTRATE AND TFT LCD SUBSTRATE WIRING THEREBY}

The present invention relates to a wiring forming method for a TFT LCD substrate using aluminum as a wiring material and a TFT LCD substrate thereby.

A TFT LCD (thin film transistor liquid crystal display) includes a liquid crystal panel in which liquid crystal is injected between a thin film transistor substrate and a color filter substrate. Since the TFT LCD is a non-light emitting device, a backlight unit for supplying light is located behind the thin film transistor. Light transmitted from the backlight is adjusted according to the arrangement of liquid crystals.

Wiring is formed on the thin film transistor substrate used for the TFT LCD. The wiring of the thin film transistor substrate includes a gate wiring and a data wiring. The data line also includes a source / drain.

In recent years, TFT LCDs require large screen sizes and high resolution. As a result, the length of the wiring is getting longer while its width is being reduced. In this trend, the high resistivity of the wiring material causes an RC delay, causing a serious problem of distorted image quality.

Until now, many high melting point materials, such as tantalum (Ta), chromium (Cr), titanium (Ti), or these alloys, were used as a wiring material of TFT LCD. However, high melting point materials are too high for resistivity and are unsuitable for use as electrode materials for TFT LCDs requiring large area and high resolution.

Examples of metals with low specific resistance include silver, copper, and aluminum. Among them, silver and copper have significantly lower adhesion to the glass substrate. In particular, copper penetrates into the amorphous silicon to break down the device or silicon penetrates into the copper on the contrary, thereby lowering the specific resistance value.

Due to these disadvantages of silver and copper, the most commonly used wiring materials are based on aluminum. Aluminum has the advantage that the specific resistance is very low, such as 3μΩcm, the wiring forming process is easy and low cost. For this reason, aluminum has attracted attention as a wiring material.

However, the disadvantage of aluminum is that a hillock occurs, causing a problem such as a broken wire.

1 is a cross-sectional view showing hillocks generated when a conventional aluminum wiring forming method is used. An aluminum wiring 2000 is disposed on the substrate material 1000, and the hillock 2100 protruding from the aluminum wiring damages the insulating layer 3000. The hillock 2100 also includes a thinner and longer whisker 2110. The active layer 4000 is positioned on the insulating layer 3000. Due to the damaged insulating film 3000, the active layer 4000 deposited on the insulating film 3000 is also defective. The insulating film 3000 is made of SiNx, and the active layer is usually made of amorphous silicon.

When the hillock 2100 occurs as shown in FIG. 1, a short with the upper layer occurs or a short occurs between adjacent wirings, resulting in a failure. In addition, if the portion where the hillock 2100 occurs is a position where the thin film transistor is formed, a defect may occur in the formed thin film transistor.

One of the causes of Hillock is the difference in coefficient of thermal expansion between aluminum and glass substrates. The coefficient of thermal expansion of aluminum is about 23.9 × 10 ⁻⁶ / K and that of glass is about 4.5 × 10 ⁻⁶ / K. When the aluminum wiring is formed on the substrate, an insulating film is formed by chemical vapor deposition. Heat of 300 to 400 ° C. is applied to aluminum in this insulating film formation process. At this time, the aluminum wiring tries to be stretched by heat, but is subjected to compressive stress by a substrate having a small coefficient of thermal expansion. In the part where the stress is relaxed, aluminum particles grow to generate hillocks.

Another cause of hillock is the crystal orientation of aluminum. Aluminum wiring consists of numerous aluminum grains and each aluminum grain has a different crystal orientation. That is, each aluminum grain has different crystal directions, such as (100), (110), and (111). For this reason, the structure of aluminum is not stable and heel lock is likely to occur.

As a method of preventing the occurrence of such a hillock, the following method has been suggested.

The first is to add high melting metals such as neodymium, titanium, zirconium, tantalum, silicon, and copper to aluminum, that is, using aluminum alloys.

The second is a capping method in which the aluminum wiring is covered with a high melting point metal layer. In this method, the metal layer covering the aluminum wiring prevents the growth of hillock generated in the aluminum wiring.

Third, a metal layer having a thermal expansion coefficient between aluminum and the glass substrate is formed under the aluminum wiring. In this method, the metal layer under the aluminum wiring serves as a buffer against the thermal expansion difference between the aluminum wiring and the glass substrate.

The first method of the above method has a problem that the hillock is prevented, but the specific resistance of the aluminum alloy is higher than 10μΩ㎝. In addition, in the case of the most commonly used aluminum-neodynium alloy, neodynium is expensive as a rare earth metal, and thus manufacturing cost is high. In addition to these problems, since the component distribution of the constituent metal is not uniform, the process conditions are difficult in the deposition process.

Since the second method does not prevent the occurrence of the hillock itself of the aluminum wiring, there is still a possibility that the hilllock occurs due to a process error. In some cases, the generated hillock may penetrate or deform the upper metal layer. In addition, the cost increases because a separate process called capping follows.

The third method only mitigates the difference in the coefficient of thermal expansion, which is one of the causes of hillock, and does not prevent the hillock from the difference in grain direction between grains.

As such, the conventional method has difficulty in reducing hillocks generated when using pure aluminum as a wiring material.

It is therefore an object of the present invention to provide a method of using pure aluminum as a wiring material while reducing the problem of hillock generation in a TFT LCD substrate.

In the aluminum wiring forming method of a TFT LCD substrate, the above object is to deposit an aluminum nitride layer containing nitrogen on a substrate material under an atmosphere in which a precursor gas of nitrogen is present, and on top of the aluminum nitride layer. By depositing a layer. The aluminum nitride layer deposited in the nitrogen precursor gas atmosphere contains nitrogen and the lattice structure is changed.

There is a sputtering method for depositing the aluminum nitride layer. When the aluminum layer is deposited using the sputtering method, if the precursor gas of nitrogen is present in the sputtering chamber, the aluminum nitride layer may be formed.

The method of depositing the aluminum nitride layer also includes an evaporation method. When the aluminum layer is deposited by the evaporation method, if the precursor gas of nitrogen is present in the evaporation chamber, the aluminum nitride layer may be formed.

The precursor of nitrogen is preferably any one selected from the group consisting of nitrogen gas, ammonia, mixtures thereof and the like.

Preferably, the aluminum nitride layer contains 50 electron% or less of nitrogen. When nitrogen nitride contains 50 electron% or more in the aluminum nitride layer, the function of buffering the thermal expansion coefficient difference decreases. In addition, the nitrogen of the aluminum nitride layer should be more than necessary to change the lattice structure of aluminum.

The thermal expansion coefficient of the aluminum nitride layer is preferably 4.5 × 10 ^-6 / K to 23.9 × 10 ^-6 / K. 4.5 × 10 ^-6 / K is the coefficient of thermal expansion of the glass substrate and 23.9 × 10 ^-6 / K is the coefficient of thermal expansion of aluminum

After depositing the aluminum layer. The metal layer may be further deposited on top of the aluminum layer to form a triple layer. In particular, a molybdenum layer, a molybdenum alloy layer, an aluminum alloy layer, a titanium layer, a titanium alloy layer, a tantalum layer and the like may be further formed on the aluminum layer.

The above object is also achieved by including, in a TFT LCD substrate, an aluminum nitride layer formed on a substrate material and containing nitrogen, and an aluminum layer formed on top of the aluminum nitride layer. The lattice structure of the aluminum nitride layer was changed due to nitrogen.

The aluminum nitride layer has a hexagonal structure and has a (0002) preferred orientation.

The aluminum layer has a (111) preferred orientation. This is because the lower layer has a (0002) first orientation.

The nitrogen content of the aluminum nitride layer is preferably 50 electron% or less. When nitrogen nitride contains 50 electron% or more in the aluminum nitride layer, the function of buffering the thermal expansion coefficient difference decreases.

The thermal expansion coefficient of the aluminum nitride layer is preferably 4.5 × 10 ^-6 / K to 23.9 × 10 ^-6 / K. 4.5 × 10 ^-6 / K is the coefficient of thermal expansion of the glass substrate and 23.9 × 10 ^-6 / K is the coefficient of thermal expansion of aluminum

It may have a triple layer structure in which a metal layer is further deposited on the aluminum layer. In particular, a molybdenum layer, a molybdenum alloy layer, an aluminum alloy layer, a titanium layer, a titanium alloy layer, a tantalum layer may be further formed on the aluminum layer.

The (111) preferred orientation in the present invention is a ratio of the sum of (111) peak intensity to (hkl) peak intensity when analyzed by X-ray diffractometer (XRD) is 80% or more, that is, when the intensity is I, I ₍₁₁₁₎ / Σ I _(hkl) ≥ 0.8, with a ω figure representing the width of the (111) intensity measured within a pole figure with a 4-axis goniometer Say that.

Aluminum has a variety of crystal directions such as (100), (110), and (111) as a structure of face-centered cubes. The crystal direction of each aluminum grain constituting the aluminum wiring is also so diverse that the structure is not dense and not stable.

The hillock resistance of aluminum depends a lot on the crystal direction of aluminum. It is known that when the crystal direction of aluminum has a (111) preferred orientation, that is, each aluminum grain constituting the aluminum wiring has the (111) crystal orientation, and exhibits the best hillock resistance when deposited or grown.

However, aluminum preferential orientation has a close relationship with the crystal structure of the aluminum lower layer. This is described in J. Appl. Phys. 77 (8) Apr. 15, 1999, pp3799-3804. Aluminum has a (111) preferred orientation when the underlying layer has a (0002) preferred orientation.

U. S. Patent No. 5,994, 156 discloses a method of depositing a hexagonal titanium layer with a (0002) preferred orientation and then depositing an aluminum layer thereon. The aluminum layer deposited on top of the (0002) preferred titanium layer has a (111) preferred orientation and thus has excellent hillock resistance.

However, since the titanium layer is difficult to batch etch with the aluminum layer, dry etching must be performed in addition to the wet etching. In addition, the coefficient of thermal expansion of titanium is 8.6 × 10 ⁻⁶ / K, which is close to 4.5 × 10 ⁻⁶ / K, which is a coefficient of thermal expansion of a glass substrate, and is unsuitable for buffering the difference in coefficient of thermal expansion between the glass substrate and the aluminum layer.

Aluminum nitride used in the present invention has a hexagonal structure unlike aluminum. In other words, nitrogen is dissolved in the face-centered cubic structure of aluminum and serves to transform the aluminum into the hexagonal structure. In addition, aluminum nitride has a (0002) priority direction so that the aluminum formed on the top has a (111) priority direction.

Another feature of aluminum nitride is that the coefficient of thermal expansion can be adjusted between the values of aluminum and glass substrates by changing the nitrogen content. If the atomic% of aluminum and nitrogen is the same, that is, 50 atomic% of nitrogen, the parallel coefficient of thermal expansion of aluminum nitride is 4.15 × 10 ⁻⁶ / K, which is similar to the coefficient of thermal expansion of the glass substrate. As the nitrogen content decreases, the thermal expansion coefficient of aluminum nitride is closer to the aluminum thermal expansion coefficient of 23.9 × 10 ^-6 / K. Therefore, by controlling the content of nitrogen in the aluminum nitride it is possible to control the function of buffering the thermal expansion difference between the aluminum and the glass substrate.

Hereinafter, a method of forming an aluminum nitride layer in which a structure is changed by employing nitrogen and a process of depositing an aluminum layer on the aluminum nitride layer will be described in detail. In the present specification, the substrate material refers to a substrate such as glass or quartz, and the substrate refers to a substrate material having a pattern including wiring.

The wiring of the present invention includes both the gate wiring and the data wiring and the data wiring also includes the source / drain. Therefore, when the data wiring is formed, some patterns are formed on the substrate material, and the wiring of the present invention may be formed thereon.

In general, a method of forming a metal layer by depositing a metal on a substrate material includes a sputtering method and an evaporation method.

In the sputtering method, argon gas is injected into a chamber provided with a target electrode made of a metal to be deposited to which a high voltage is applied, thereby causing plasma discharge. The argon cation excited by the plasma discharge removes metal atoms from the target electrode, and these metal atoms are bonded to each other on the surface of the substrate material and grow into thin films.

The method of solid-solving nitrogen in an aluminum layer by the sputtering method uses aluminum as a target electrode, and injects a precursor of nitrogen into a sputtering chamber. As a precursor of nitrogen, nitrogen gas, ammonia, mixtures thereof, and the like are possible.

In the evaporation method, the aluminum metal is heated by irradiation with an electron beam. Aluminum atoms are released from the heated aluminum metal. The aluminum atoms thus released are deposited on the substrate.

The method of solid-solution nitrogen in aluminum by the evaporation method is to inject a precursor of nitrogen into the evaporation chamber. As a precursor of nitrogen, nitrogen gas, ammonia, mixtures thereof, and the like are possible.

In the sputtering method or the evaporation method, the concentration of the nitrogen precursor in the chamber is adjusted according to the deposition temperature, the deposition time, the desired nitrogen content in the aluminum nitride layer, and the like.

Nitrogen dissolved in aluminum transforms the face-centered cubic structure into hexagonal structure and also has a (0002) priority orientation. The content of nitrogen is preferably 50 atomic% or less in the aluminum layer. If the nitrogen content is 50 atomic% or more, the thermal expansion coefficient is 4.15 × 10 ⁻⁶ / K or less, and thus it is difficult to expect a function of buffering the thermal expansion difference between the aluminum layer and the glass substrate.

 When the aluminum nitride layer is completed, an aluminum layer is formed on the top. The deposition of the aluminum layer is also usually by the sputtering method or the evaporation method. The aluminum layer deposited on the aluminum nitride layer having the preferred orientation has a (111) preferred orientation for low interfacial energy.

In this way, the (111) preferred orientation can be obtained to obtain an aluminum layer having excellent hillock properties.

Thereafter, the aluminum wiring is completed by forming an insulating film on the aluminum layer, applying a photoresist, exposing and developing the photoresist, and etching.

Hereinafter, with reference to the accompanying drawings, the aluminum wiring according to the present invention will be described in detail.

2 is a cross-sectional view showing a first embodiment in which aluminum wiring is formed according to the present invention. 2 shows a state in which wiring is completed through etching of a metal layer and the like, and an insulating film and an active layer are formed thereon. An aluminum nitride layer 2 (denoted by AlN) is present on the substrate material 1. The structure of the aluminum nitride layer 2 was changed by nitrogen. The content of nitrogen is preferably 50 atomic% or less of the aluminum nitride layer 2. The nitrogen nitride aluminum nitride layer 2 has a hexagonal structure and has a (0002) priority orientation.

An aluminum layer 3 is positioned on the aluminum nitride layer 2. The aluminum layer 3 has a (111) preferred orientation under the influence of the aluminum nitride layer 2, which is a lower layer.

The aluminum nitride layer 2 and the aluminum layer 3 are covered with the insulating film 4. In addition, the active layer 5 is positioned above the insulating film. The insulating film 4 is mainly SiNx, and the active layer 5 is mainly amorphous silicon.

3 is a cross-sectional view showing a second embodiment in which aluminum wiring is formed according to the present invention. It is the same structure as FIG. 2, However, the metal layer 6 is further formed in the said aluminum layer 3 upper part.

The present invention using an aluminum nitride layer having a preferred orientation as a lower layer can also be applied to a wiring method such as copper, nickel, and silver having a face centered cubic structure.

Hereinafter, a TFT LCD substrate and a method of manufacturing the same according to the present invention will be described.

4 is a plan view of a TFT LCD substrate according to the first embodiment of the present invention, and FIG. 5 is a cross-sectional view taken along the line VV ′ of the TFT LCD substrate shown in FIG. 4. 6 to 9 are cross-sectional views illustrating a manufacturing process of a TFT LCD substrate according to a first embodiment of the present invention.

Gate wirings 22, 24, and 26 formed of a double layer of first gate metal layers 221, 241, and 261 and second gate metal layers 222, 242, and 262 are formed on the substrate material 10. The first gate metal layers 221, 241, and 261 are aluminum nitride layers, and the second gate metal layers 222, 242, and 262 are aluminum layers.

The gate lines 22 and 26 include a gate line 22 extending in the horizontal direction and a gate electrode 26 of the thin film transistor connected to the gate line 22. Here, one end portion 24 of the gate line 22 is extended in width for connection with an external circuit.

On the substrate material 10, a gate insulating film 30 made of silicon nitride (SiNx) covers the gate wirings 22, 24, and 26.

A semiconductor layer 40 made of a semiconductor such as amorphous silicon is formed on the gate insulating film 30 of the gate electrode 24, and n + having a high concentration of silicide or n-type impurity is formed on the semiconductor layer 40. Resistive contact layers 55 and 56 made of a material such as hydrogenated amorphous silicon are formed, respectively.

On the ohmic contact layers 55 and 56 and the gate insulating layer 30, data lines 65 and 66 formed of a double layer of first data metal layers 651, 661, and 681 and second data metal layers 652, 662, and 682. , 68). The first data metal layers 651, 661, 681 are aluminum nitride layers, and the second data metal layers 652, 662, 682 are aluminum layers. Although not shown, the data line 62 is a double layer formed of an aluminum nitride layer and an aluminum layer.

The data lines 62, 65, and 66 are formed in the vertical direction and intersect the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the upper portion of the ohmic contact layer 55. A drain electrode 66 which is separated from the extending source electrode 65 and the source electrode 65 and is formed on the ohmic contact layer 56 opposite to the source electrode 65 with respect to the gate electrode 26. It includes. At this time, one end portion 68 of the data line 62 is extended in width for connection with an external circuit.

A-Si: C: O film or a deposited on the data lines 62, 65, 66, 68 and on the semiconductor layer 40 which is not covered by silicon nitride (SiNx) or plasma enhanced chemical vapor deposition (PECVD) A protective film 70 made of a -Si: O: F film (low dielectric constant CVD film), an arcle-based organic insulating film, and the like is formed. The a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a dielectric constant of 4 or less (the dielectric constant has a value between 2 and 4). The dielectric constant is very low. Therefore, even a thin thickness does not cause a parasitic capacity problem. Excellent adhesion to another film and step coverage. Moreover, since it is an inorganic CVD film, heat resistance is excellent compared with an organic insulating film. In addition, the a-Si: C: O film and a-Si: O: F film (low dielectric constant CVD film) deposited by the PECVD method have a 4 to 10 times faster process time than the silicon nitride film in terms of deposition rate and etching rate. It is also very advantageous in terms of.

In the passivation layer 70, contact holes 76 and 78 are formed to expose the drain electrode 66 and the end portion 68 of the data line, respectively, and the contact portion exposing the end portion 24 of the gate line together with the gate insulating layer 30. The hole 74 is formed.

On the passivation layer 70, a pixel electrode 82 electrically connected to the drain electrode 66 and positioned in the pixel region is formed through the contact hole 76. Further, on the passivation layer 70, contact auxiliary members 86 and 88 are formed to be connected to the end portion 24 of the gate line and the end portion 68 of the data line, respectively, through the contact holes 74 and 78. Here, the pixel electrode 82 and the contact auxiliary members 86 and 88 are made of indium tin oxide (ITO) or indium zinc oxide (IZO).

4 and 5, the pixel electrode 82 overlaps with the gate line 22 to form a storage capacitor. When the storage capacitor is insufficient, the pixel electrode 82 is disposed on the same layer as the gate lines 22, 24, and 26. It is also possible to add a storage capacitor wiring.

In addition, the pixel electrode 82 may also be formed to overlap the data line 62 to maximize the aperture ratio. Even if the pixel electrode 82 is formed to overlap the data line 62 in order to maximize the aperture ratio, if the low dielectric constant CVD film or the like of the protective film 70 is formed, the parasitic capacitance formed therebetween will be small. I can keep it.

Referring to the method of manufacturing a TFT LCD substrate according to the first embodiment, first, as shown in FIG. 6, first gate metal layers 221, 241, and 261, which are aluminum nitride layers, are deposited on the substrate material 10. After that, the second gate metal layers 222, 242, and 262, which are aluminum layers, are stacked and patterned by a photolithography process using a mask to include the gate lines 22 and the gate electrodes 26 and extend in the horizontal direction. The wirings 22, 24, and 26 are formed.

Next, as shown in FIG. 7, the three-layer film of the gate insulating film 30 made of silicon nitride, the semiconductor layer 40 made of amorphous silicon, and the doped amorphous silicon layer 50 is successively laminated, and the semiconductor layer 40 ) And the doped amorphous silicon layer 50 are photo-etched to form an island-like semiconductor layer 40 and an ohmic contact layer 50 on the gate insulating layer 30 on the gate electrode 24.

Next, as illustrated in FIG. 8, first data metal layers 651, 661, and 681, which are aluminum nitride layers, are stacked, and then second data metal layers 622, 652, 662, and 682, which are aluminum layers, are stacked. And a data line 62 intersecting the gate line 22 and a source electrode 65 and a source electrode connected to the data line 62 and extending to the upper portion of the gate electrode 26 by patterning by a photolithography process using a mask. A data line separated from the reference numeral 65 and including a drain electrode 66 facing the source electrode 65 around the gate electrode 26 is formed.

Subsequently, the doped amorphous silicon layer pattern 50, which is not covered by the data lines 62, 65, 66, and 68, is etched and separated on both sides of the gate electrode 26, while both doped amorphous silicon layers ( The semiconductor layer pattern 40 between 55 and 56 is exposed. Subsequently, in order to stabilize the surface of the exposed semiconductor layer 40, it is preferable to perform oxygen plasma.

Next, as shown in FIG. 9, a silicon nitride film, an a-Si: C: O film or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film 70. ).

Subsequently, the passivation layer 70 is patterned together with the gate insulating layer 30 by a photolithography process, thereby contact holes 74 and 76 exposing the end portion 24 of the gate line, the drain electrode 66 and the end portion 68 of the data line. , 78).

Next, as shown in FIGS. 4 and 5, the ITO or IZO film is deposited and photo-etched to connect the pixel electrode 82 and the contact holes 74 and 78 connected to the drain electrode 66 through the contact hole 76. The contact auxiliary members 86 and 88 which are connected to the end portion 24 of the gate line and the end portion 68 of the data line are respectively formed therethrough. It is preferable to use nitrogen as the gas used in the pre-heating process before laminating ITO or IZO.

In the first embodiment, both the gate wirings 22, 24, 26 and the data wirings 62, 65, 66, 68 are formed in double layers, but the gate wirings 22, 24, 26 and the data wirings are formed as necessary. Any one of (62, 65, 66, 68) may be a double layer, and either or both may apply a triple layer structure. In addition, the present invention does not have to be applied to both the gate wirings 22, 24, 26 and the data wirings 62, 65, 66, 68.

The first embodiment described above uses five masks in the manufacture of a TFT LCD substrate, and the second embodiment described below uses four masts.

FIG. 10 is a plan view of a TFT LCD substrate according to a second embodiment of the present invention, and FIG. 11 is a plan view of the TFT LCD substrate shown in FIG. 12 is a cross-sectional view of the TFT LCD substrate shown in FIG. It is sectional drawing along a line. 13A to 20B are cross-sectional views illustrating a manufacturing process of a TFT LCD substrate according to a second embodiment of the present invention.

On the substrate material 10, the gate wirings 22, 24, and 26 are formed of two layers of the first gate metal layers 221, 241, and 262 and the second gate metal layers 222, 242, and 262, as in the first embodiment. ) Is formed. The first gate metal layers 221, 241, and 262 are aluminum nitride layers, and the second gate metal layers 222, 242, and 262 are aluminum layers.

The storage electrode line 28 is formed on the substrate material 10 in parallel with the gate line 22. The storage electrode line 28 also consists of a double layer of a first gate metal layer 281 which is an aluminum nitride layer and a second gate metal layer 282 which is an aluminum layer. The storage electrode line 28 overlaps with the conductor 64 for the storage capacitor connected to the pixel electrode 82 to be described later to form a storage capacitor which improves charge storage capability of the pixel. The pixel electrode 82 and the gate line (to be described later) It may not be formed if the holding capacity resulting from the overlap of 22) is sufficient. The same voltage as that of the common electrode of the upper substrate is usually applied to the storage electrode line 28.

A gate insulating film 30 made of silicon nitride (SiNx) is formed on the gate wirings 22, 24, 26 and the storage electrode line 28 to cover the gate wirings 22, 24, 26 and the storage electrode line 28. .

On the gate insulating layer 30, semiconductor patterns 42 and 48 made of semiconductors such as hydrogenated amorphous silicon are formed, and on the semiconductor patterns 42 and 48, n-type impurities such as phosphorus (P) have a high concentration. An ohmic contact layer pattern or an intermediate layer pattern 55, 56, 58 made of amorphous silicon doped with is formed.

On the ohmic contact layer patterns 55, 56, and 58, data is formed of two layers of first data metal layers 621, 641, 651, 661, and 681 and second data metal layers 622, 642, 652, 662, and 682. Wirings 62, 64, 65, 66, and 68 are formed. The first data metal layers 621, 641, 651, 661, and 681 are aluminum nitride layers, and the second data metal layers 622, 642, 652, 662, and 682 are aluminum layers. The data line is formed in the vertical direction and is a branch of the data line 62 and the data line 62 which are connected to one end of the data line 62 and have an end portion 68 of the data line to which an image signal from the outside is applied. And a data line portion 62, 68, 65 made of the source electrode 65 of the thin film transistor, and are separated from the data line portions 62, 68, 65 and the channel portion E of the gate electrode 26 or the thin film transistor. ) Also includes the drain electrode 66 of the thin film transistor positioned on the opposite side of the source electrode 65 and the conductor 64 for the storage capacitor located on the storage electrode line 28. When the storage electrode line 28 is not formed, the storage capacitor conductor 64 is also not formed.

 The contact layer patterns 55, 56, and 58 serve to lower the contact resistance between the semiconductor patterns 42 and 48 below and the data lines 62, 64, 65, 66, and 68 above them. It has exactly the same form as (62, 64, 65, 66, 68). That is, the data line part intermediate layer pattern 55 is the same as the data line parts 62, 68, and 65, the drain electrode intermediate layer pattern 56 is the same as the drain electrode 66, and the storage capacitor intermediate layer pattern 58 is It is the same as the conductor 64 for holding capacitors.

The semiconductor patterns 42 and 48 have the same shape as the data lines 62, 64, 65, 66, and 68 and the ohmic contact layer patterns 55, 56, and 58 except for the channel portion E of the thin film transistor. Doing. Specifically, the semiconductor capacitor 48 for the storage capacitor, the conductor 64 for the storage capacitor, and the contact layer pattern 58 for the storage capacitor have the same shape, but the semiconductor pattern 42 for the thin film transistor has a data wiring and a contact layer. Slightly different from the rest of the pattern. That is, in the channel portion E of the thin film transistor, the data line portions 62, 68, and 65, in particular, the source electrode 65 and the drain electrode 66 are separated, and the contact layer pattern for the data line intermediate layer 55 and the drain electrode. Although 56 is also separated, the semiconductor pattern 42 for thin film transistors is not disconnected here and is connected to generate a channel of the thin film transistor.

On the data lines 62, 64, 65, 66 and 68, an a-Si: C: O film or a-Si: O: F film (low dielectric constant CVD) deposited by silicon nitride or plasma enhanced chemical vapor deposition (PECVD) method Film) or an organic insulating film is formed. The protective film 70 has contact holes 76, 78, and 72 that expose the drain electrode 66, the end portion 68 of the data line, and the conductor 64 for the storage capacitor, and together with the gate insulating film 30. It has a contact hole 74 that exposes the end portion 24 of the gate line.

On the passivation layer 70, a pixel electrode 82 that receives an image signal from a thin film transistor and generates an electric field together with the electrode of the upper plate is formed. The pixel electrode 82 is made of a transparent conductive material such as ITO or indium tin oxide (IZO), and is physically electrically connected to the drain electrode 66 through the contact hole 76 to receive an image signal. The pixel electrode 82 also overlaps with the neighboring gate line 22 and the data line 62 to increase the aperture ratio, but may not overlap. The pixel electrode 82 is also connected to the storage capacitor conductor 64 through the contact hole 72 to transmit an image signal to the conductor pattern 64. On the other hand, on the end portion 24 of the gate line and the end portion 68 of the data line, contact auxiliary members 86 and 88 connected to them through contact holes 74 and 78, respectively, are formed. These contact auxiliary members 86, 88 are essential to complement the adhesion between the ends 24, 68 and the external circuit device and to protect the ends 24, 68 of the gate lines and the data lines, respectively. It is not intended that they be applied.

Looking at the TFT LCD substrate manufacturing method according to the second embodiment, after laminating the first gate metal layer (221, 241, 261, 281) of the aluminum nitride layer as in the first embodiment as shown in Figs. 13a and 13b The second gate metal layers 222, 242, 262, and 282, which are aluminum layers, are stacked and then etched to form gate lines including the gate lines 22 and the gate electrodes 26 and the storage electrode lines 28. . At this time, one end portion 24 of the gate line 22 connected to the external circuit has a wider width.

Next, as shown in FIGS. 14A and 14B, the gate insulating film 30, the semiconductor layer 40, and the intermediate layer 50 made of silicon nitride are respectively 1,500 kV to 5,000 kPa and 500 kPa to 2,000 kPa using chemical vapor deposition. , And continuously deposited to a thickness of 300 kPa to 600 kPa, and then forming a first conductive film 601 made of aluminum nitride in order to form data wirings, and then a second conductive film 602 made of aluminum by sputtering or the like. After the deposition to form the conductor layer 60, the photosensitive film 110 is applied thereon to a thickness of 1㎛ to 2㎛.

Thereafter, the photosensitive film 110 is irradiated with light through a mask and then developed to form photosensitive film patterns 112 and 114 as shown in FIGS. 15A and 15B. At this time, the channel portion E of the thin film transistor, that is, the first portion 114 positioned between the source electrode 65 and the drain electrode 66, of the photoresist patterns 112 and 114 is the data wiring portion C, that is, the data. The thickness of the wirings 62, 64, 65, 66, and 68 is smaller than that of the second part 112 positioned at the portion where the wirings 62, 64, 65, 66, and 68 are to be formed. At this time, the ratio of the thickness of the photoresist film 114 remaining in the channel portion E to the thickness of the photoresist film 112 remaining in the data wiring portion C should be different depending on the process conditions in an etching process which will be described later. It is preferable that the thickness of the first portion 114 is 1/2 or less of the thickness of the second portion 112, for example, 4,000 kPa or less.

As such, there may be various methods of varying the thickness of the photoresist film according to the position, and in order to control the light transmittance in the C region, a slit or lattice-shaped pattern is mainly formed or a translucent film is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure apparatus used for exposure. A thin film having a thickness or a thin film may be used.

When the light is irradiated to the photosensitive film through such a mask, the polymers are completely decomposed at the part directly exposed to the light, and the polymers are not completely decomposed because the amount of light is small at the part where the slit pattern or the translucent film is formed. In the area covered by, the polymer is hardly decomposed. Subsequently, when the photoresist film is developed, only a portion where the polymer molecules are not decomposed is left, and a thin photoresist film may be left at a portion where the light is not irradiated at a portion less irradiated with light. In this case, if the exposure time is extended, all the polymer molecules are decomposed, so it should not be so.

This thin photoresist film 114 is developed using a photoresist film made of a reflowable material and exposed with a conventional mask that is divided into a part that can completely transmit light and a part that can not completely transmit light. It may be formed by reflowing a portion of the photosensitive film to a portion where the photosensitive film does not remain.

Subsequently, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the intermediate layer 50, and the semiconductor layer 40. In this case, the data line and the layers under the data line remain in the data line C, and only the semiconductor layer remains in the channel part E, and the upper three layers 60, 50, 40 must be removed to expose the gate insulating film 30.

First, as shown in FIGS. 14A and 14B, the exposed conductor layer 60 of the other portion B is removed to expose the lower intermediate layer 50. In this process, both a dry etching method and a wet etching method may be used. In this case, the conductor layer 60 may be etched and the photoresist patterns 112 and 114 may be hardly etched. However, in the case of dry etching, it is difficult to find a condition in which only the conductor layer 60 is etched and the photoresist patterns 112 and 114 are not etched, and thus the photoresist patterns 112 and 114 may be etched together. In this case, the thickness of the first portion 114 is thicker than that of the wet etching so that the first portion 114 is removed in this process so that the lower conductive layer 60 is not exposed.

This leaves only the conductor layers of the channel portion E and the data wiring portion D, that is, the source / drain conductor pattern 67 and the storage capacitor conductor 64, as shown in Figs. 16A and 16B. The conductor layer 60 of the other portion B is all removed to reveal the underlying intermediate layer 50. The remaining conductor patterns 67 and 64 are the same as those of the data lines 62, 64, 65, 66 and 68 except that the source and drain electrodes 65 and 66 are connected without being separated. . In addition, when dry etching is used, the photoresist patterns 112 and 114 are also etched to a certain thickness.

Then, as shown in FIGS. 17A and 17B, the exposed intermediate layer 50 of the other portion B and the semiconductor layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. do. At this time, etching is performed under the condition that the photoresist patterns 112 and 114, the intermediate layer 50, and the semiconductor layer 40 (the semiconductor layer and the intermediate layer have almost no etching selectivity) are simultaneously etched, and the gate insulating layer 30 is not etched. In particular, it is preferable to etch under conditions in which the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are almost the same. For example, by using a mixed gas of SF ₆ and HCl or a mixed gas of SF ₆ and O ₂ , the two films can be etched to almost the same thickness. When the etch ratios of the photoresist patterns 112 and 114 and the semiconductor layer 40 are the same, the thickness of the first portion 114 should be equal to or smaller than the sum of the thicknesses of the semiconductor layer 40 and the intermediate layer 50.

In this way, as shown in FIGS. 17A and 17B, the first portion 114 of the channel portion E is removed to reveal the source / drain conductor pattern 67 and the intermediate layer 50 of the other portion D. And the semiconductor layer 40 is removed to expose the gate insulating layer 30 thereunder. On the other hand, since the second portion 112 of the data line portion C is also etched, the thickness becomes thin. In this step, the semiconductor patterns 42 and 48 are completed. Reference numerals 57 and 58 denote intermediate layer patterns under the source / drain conductor patterns 67 and intermediate layer patterns under the storage capacitor conductors 64, respectively.

Subsequently, ashing removes the photoresist residue remaining on the surface of the source / drain conductor pattern 67 of the channel portion E. Referring to FIG.

Next, as shown in FIGS. 18A and 18B, the source / drain conductor pattern 67 of the channel portion E and the source / drain interlayer pattern 57 below are etched and removed. In this case, the etching may be performed only by dry etching with respect to both the source / drain conductor pattern 67 and the intermediate layer pattern 57. The etching may be performed by wet etching on the source / drain conductor pattern 67. 57 may be performed by dry etching. In the former case, it is preferable to perform etching under the condition that the etching selectivity of the source / drain conductor pattern 67 and the interlayer pattern 57 is large, which is difficult to find the etching end point when the etching selectivity is not large. This is because it is not easy to adjust the thickness of the semiconductor pattern 42 remaining in E). In the latter case of alternating between wet etching and dry etching, the side surface of the conductive pattern 67 for wet etching of the source / drain is etched, but the intermediate layer pattern 57 which is dry etched is hardly etched, and thus is formed in a step shape. Examples of the etching gas used to etch the intermediate layer pattern 57 and the semiconductor pattern 42 include a mixture gas of CF ₄ and HCl or a mixture gas of CF ₄ and O ₂ , and CF ₄ and O ₂ . The semiconductor pattern 42 may be left at a uniform thickness. In this case, as shown in FIG. 18B, a portion of the semiconductor pattern 42 may be removed to reduce the thickness, and the second portion 112 of the photoresist pattern may also be etched to a certain thickness at this time. At this time, the etching must be performed under the condition that the gate insulating film 30 is not etched, and the photoresist film is not exposed so that the second portion 112 is etched so that the data lines 62, 64, 65, 66, and 68 underneath are not exposed. It is a matter of course that the pattern is thick.

In this way, the source electrode 65 and the drain electrode 66 are separated, thereby completing the data lines 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, and 58 under the data lines.

Finally, the photosensitive film second portion 112 remaining in the data line part C is removed. However, the removal of the second portion 112 may be performed after removing the channel pattern E source / drain conductor pattern 67 and before removing the intermediate layer pattern 57 thereunder.

As mentioned earlier, wet and dry etching can be alternately used or only dry etching can be used. In the latter case, since only one type of etching is used, the process is relatively easy, but it is difficult to find a suitable etching condition. On the other hand, in the former case, the etching conditions are relatively easy to find, but the process is more cumbersome than the latter.

Next, as shown in FIGS. 19A and 19B, a silicon nitride, an a-Si: C: O film, or an a-Si: O: F film is grown by chemical vapor deposition (CVD) or an organic insulating film is applied to the protective film. Form 70.

Next, as shown in FIGS. 20A to 20B, the passivation layer 70 is photo-etched together with the gate insulating layer 30 to drain the electrode 66, the end portion 24 of the gate line, the end portion 68 of the data line, and the like. Contact holes 76, 74, 78 and 72 are respectively formed to expose the conductor 64 for the storage capacitor.

Lastly, as shown in FIGS. 11 to 12, a pixel electrode connected to the drain electrode 66 and the storage capacitor conductor 64 by depositing and photolithography an ITO layer or an IZO layer having a thickness of 400 μs to 500 μs. 82, a data contact assistant member 88 connected to an end portion 24 of the gate line and the gate contact assistant member 86 and an end portion 68 of the data line are formed.

On the other hand, as a gas used in the pre-heating process before laminating ITO or IZO, it is preferable to use nitrogen, which is the metal film 24 exposed through the contact holes 72, 74, 76, and 78. This is to prevent the metal oxide film from being formed on the upper portions of 64, 66 and 68.

In the second embodiment of the present invention, the data wirings 62, 64, 65, 66, and 68 and the contact layer patterns 55, 56, 58 and the semiconductor pattern 42 below the data wirings 62, 64, 65, 66, and 68, as well as the effects of the first embodiment. , 48 may be formed using a single mask, and the manufacturing process may be simplified by separating the source electrode 65 and the drain electrode 66 in this process.

In the second embodiment, the gate wirings 22, 24, 26, the storage electrode lines 28, and the data wirings 62, 64, 65, 66, 68 are all formed in double layers, but only a part of them is double layered as necessary. can do. It is also possible to apply a triple layer structure to some or all of them. In addition, the present invention should not be applied to all of the gate wirings 22, 24, 26, the storage electrode lines 28, and the data wirings 62, 64, 65, 66, 68.

As described above, according to the present invention, generation of hillock can be suppressed even when pure aluminum wiring is used for the TFT LCD substrate. As a result, aluminum having a low specific resistance can be used as a wiring material of the TFT LCD, and it can appropriately cope with large screen and high resolution of the TFT LCD.

1 is a cross-sectional view showing the hillock generated when using a conventional method for forming aluminum wiring,

2 is a cross-sectional view showing a first embodiment in which aluminum wiring is formed according to the present invention;

3 is a cross-sectional view showing a second embodiment in which aluminum wiring is formed according to the present invention;

4 is a plan view of a TFT LCD substrate according to a first embodiment of the present invention;

5 is a cross-sectional view taken along the line VV 'of the TFT LCD substrate shown in FIG. 4;

6 to 9 are cross-sectional views illustrating a manufacturing process of a TFT LCD substrate according to a first embodiment of the present invention;

10 is a plan view of a TFT LCD substrate according to a second embodiment of the present invention;

11 is a view of the TFT LCD substrate shown in FIG. Section along the line,

12 is a view of the TFT LCD substrate shown in FIG. Section along the line,

13A to 20B are cross-sectional views illustrating a manufacturing process of a TFT LCD substrate according to a second embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

1: substrate material 2: aluminum nitride layer

3: aluminum layer 4: insulating film

5: active layer

Claims (13)

In the method of forming the aluminum wiring of a TFT LCD substrate, Depositing a layer of aluminum nitride including nitrogen on the substrate material in an atmosphere in which a precursor gas of nitrogen is present; And depositing an aluminum layer on top of the aluminum nitride layer. The method of claim 1, Deposition of the aluminum nitride layer, A method of forming aluminum wirings for a TFT LCD substrate, which is performed by sputtering. The method of claim 1, Deposition of the aluminum nitride layer, A method of forming aluminum wirings for a TFT LCD substrate, which is carried out by evaporation. The method of claim 1, The precursor of nitrogen is any one selected from the group consisting of nitrogen gas, ammonia, a mixture thereof, and the like. The method of claim 1, Wherein said aluminum nitride layer contains less than 50 electron percent nitrogen. The method of claim 1, The thermal expansion coefficient of the aluminum nitride layer is 4.5 × 10 ^-6 / K to 23.9 × 10 ^-6 / K aluminum wiring forming method of a TFT LCD substrate. The method of claim 1, After depositing the aluminum layer. And depositing a metal layer on top of the aluminum layer. In a TFT LCD substrate, An aluminum nitride layer formed on the substrate material and including nitrogen; The TFT LCD substrate comprising an aluminum layer formed on top of the aluminum nitride layer. The method of claim 8, The aluminum nitride layer has a hexagonal structure and has a (0002) preferred orientation. The method of claim 8, The aluminum layer has a (111) preferred orientation TFT LCD substrate. The method of claim 8, The TFT LCD substrate, characterized in that the nitrogen content of the aluminum nitride layer is 50 electronic% or less. The method of claim 8, The thermal expansion coefficient of the aluminum nitride layer is a TFT LCD substrate, characterized in that 4.5 × 10 ^-6 / K to 23.9 × 10 ^-6 / K. The method of claim 8, And a metal layer deposited on top of the aluminum layer.