KR20060060795A - Method for fabricating thin film transistor and display pixel - Google Patents

Abstract

In the method for manufacturing a poly-silicon thin film transistor and a display pixel, the poly-silicon channel layer of the thin film transistor is formed after forming an amorphous silicon film containing a Group 5 impurity. Thereafter, the gate insulating film and the gate electrode are sequentially formed on the poly-silicon channel layer. The source-drain region is then formed by ion implantation into the poly-silicon channel layer exposed to the gate electrode, and the interlayer insulating layer includes contact holes that expose the source-drain regions, respectively. Subsequently, the source electrode and the drain electrode are formed to be electrically connected to the source-drain region through the contact hole. By preventing the leakage current of the poly-silicon thin film transistor formed in this way, it has the effect of preventing the deterioration of the characteristics of the display pixel due to the current characteristic difference.

Description

Thin film transistor and display pixel manufacturing method {METHOD FOR FABRICATING THIN FILM TRANSISTOR AND DISPLAY PIXEL}

1 is a cross-sectional view of a poly-silicon thin film transistor according to a first embodiment of the present invention.

2 to 8 are cross-sectional views illustrating a method of manufacturing the poly-silicon thin film transistor shown in FIG. 1.

9 is a cross-sectional view of a poly-silicon thin film transistor according to a second embodiment of the present invention.

10 to 14 are cross-sectional views illustrating a method of manufacturing the poly-silicon thin film transistor illustrated in FIG. 9.

15 and 16 are cross-sectional views illustrating a method of manufacturing a display pixel including the poly-silicon thin film transistor illustrated in FIG. 9.

<Explanation of symbols for the main parts of the drawings>

100: thin film transistor 120: poly-silicon channel layer

130: gate insulating film 142: gate electrode

150: interlayer insulating layer 162: source electrode

164: drain electrode

The present invention relates to a method for manufacturing a poly-silicon thin film transistor and a display pixel, and more particularly, to a method for manufacturing a poly-silicon thin film transistor and a display pixel with improved display characteristics.

Recently, with the rapid development of electric, electronic, and communication fields, development of information processing apparatuses capable of processing massive data in a short time and storing massive data per unit area has been made. As a result data processed by the information processing device has an electrical signal form, it is almost impossible for a user to recognize it. For this reason, the result data processed by the information processing apparatus is converted so that the user can recognize it by the "display apparatus". Display devices that serve as an interface between the information processing device and the user are largely classified into analog display devices and digital display devices.

The digital display device may include a liquid crystal display device (LCD). In the liquid crystal display, two substrates each having a field generating electrode are disposed to face each other on which the two electrodes are formed, an liquid crystal material is injected between the two substrates, and an electric field generated by applying a voltage to the two electrodes. By moving the liquid crystal molecules by means of the device to express the image by the transmittance of light that varies accordingly.                         

The lower substrate of the liquid crystal display includes a thin film transistor which is a switching element. In general, an active layer used in the thin film transistor is made of amorphous silicon (a-Si: H). This is because amorphous silicon can be formed on a large substrate such as a low cost glass substrate at low temperature. However, in order to make the TFT-LCD high density and large area, and to fabricate the display portion and the driving circuit portion on the same substrate, it is urgently required to increase the mobility of the thin film transistor which is a switching element. It is difficult to satisfy this advantage with (a-Si: H TFT).

Recently, a poly-silicon thin film transistor (Polycrystalline silicon TFT; Poly-Si TFT) has attracted much attention as a method to effectively solve this problem.

The polysilicon applied to form the poly-silicon thin film transistor has a field effect mobility of about 100 to 200 times greater than that of amorphous silicon, so that the response speed is high and the stability to temperature and light is excellent. In addition, the peripheral circuit on the glass substrate has the advantage of attracting a lot of attention in terms of production cost reduction. In addition, polysilicon thin film transistors have higher mobility than amorphous silicon thin film transistors and are advantageous as switching elements of high resolution panels.

Referring to the method of manufacturing the poly-silicon thin film transistor, first, a blocking film is formed on the upper surface of the glass substrate, and a poly-silicon pattern is formed on the blocking film. Subsequently, a gate oxide film having a uniform thickness is formed on the blocking film on which the poly-silicon pattern is formed. Subsequently, a gate electrode is formed on the gate oxide film. Subsequently, an ion is implanted into the poly-silicon pattern exposed to the gate to form a source-drain region. Subsequently, the poly-silicon thin film transistor is completed by forming an interlayer insulating layer having a contact hole exposing the source-drain region and then forming a source electrode and a drain electrode respectively connected to the source-drain region.

The poly-silicon thin film transistor manufactured by the above-described method has a characteristic that the current at Vgs = 0 increases when the threshold voltage Vth is shifted positively, so that when the amount of current exceeds 10nA, Malfunctions are caused. In addition, in the case of the P-MOS thin film transistor, V _off is changed by V _com , but when 11 V is applied, the voltage is lowered to 1 to 2 V by Vcom inversion. In this case, when the threshold voltage is positive shifted, a low pixel defect is caused by an increase in leakage current.

A method for solving this problem is to prevent leakage current by adjusting the threshold voltage negative shift value of the thin film transistor by ion implanting Group 5 impurities into the poly-silicon channel layer in which the channel is formed. However, since the method performs a separate ion implantation process on the crystallized poly-silicon channel layer, it causes an increase in the manufacturing process and damage of the channel formation region. Such damage to the channel region causes a problem of deteriorating the characteristics of the thin film transistor. In addition, when a separate ion implantation process is performed on the poly-silicon channel layer, a process of activating impurities in addition to activating impurities existing in the source-drain region should be further performed.

Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a method of manufacturing a thin film transistor which improves display characteristics by adjusting a threshold voltage negative shift value.

Another object of the present invention is to provide a method of manufacturing a display pixel in which a leakage current does not occur when the thin film transistor is driven.

In accordance with an aspect of the present invention, there is provided a method of manufacturing a poly-silicon thin film transistor, including forming an amorphous silicon film including a Group 5 impurity on a substrate, and crystallizing the amorphous silicon film. Forming a poly-silicon channel layer, continuously forming a gate insulating film on the poly-silicon channel layer, forming a gate electrode on the gate insulating film, and a poly exposed to the gate electrode. Implanting impurities into the silicon channel layer to form a source-drain region, forming an interlayer insulating layer having contact holes exposing the source-drain regions, respectively; Forming a source electrode and a drain electrode electrically connected to the source-drain, respectively.

In addition, the method for manufacturing a poly-silicon thin film transistor according to another embodiment of the present invention for achieving the object of the present invention, the chemical vapor deposition process for depositing an amorphous silicon material further comprises a gas containing a Group 5 impurity Providing an amorphous silicon film comprising a Group 5 impurity on the substrate, crystallizing the amorphous silicon film to form a poly-silicon channel layer, and continuously forming a gate insulating film on the poly-silicon channel layer. Forming a preliminary gate electrode having a structure in which a first metal and a second metal are stacked on the gate insulating layer, and a high concentration of impurities in the poly-silicon channel layer exposed to the preliminary gate electrode Performing ion implantation and etching the preliminary gate electrode to undercut the side surface of the first metal. Forming a source electrode and ion implanting a low concentration of impurities into the poly-silicon channel layer exposed to the gate electrode to form a source-drain region having an LDD structure; Forming an interlayer insulating layer having contact holes respectively exposing the source-drain regions, and forming source and drain electrodes electrically connected to the source-drain regions through the contact holes, respectively; do.

In addition, the display pixel manufacturing method according to an embodiment of the present invention for achieving another object of the present invention, by providing a gas containing a Group 5 impurities in the chemical vapor deposition process for depositing the amorphous silicon material Forming an amorphous silicon film including a Group 5 impurity on a substrate, crystallizing the amorphous silicon film to form a poly-silicon channel layer, and continuously forming a gate insulating film on the poly-silicon channel layer And forming a preliminary gate electrode having a structure in which a first metal and a second metal are stacked on the gate insulating layer, and ion implanting a high concentration of impurities into the poly-silicon channel layer exposed to the preliminary gate electrode. And etching the preliminary gate electrode to form a gate electrode having a side surface of the first metal undercut. Forming a source-drain region having an LDD structure by ion implanting a low concentration of impurities into the poly-silicon channel layer exposed to the gate electrode; Forming an interlayer insulating layer having contact holes exposing the source-drain regions, respectively, forming source and drain electrodes electrically connected to the source-drain regions through the contact holes; Forming a pixel electrode electrically connected to the drain electrode.

Here, it is preferable to use a transparent substrate having a blocking film formed thereon. The amorphous silicon film including the Group 5 impurities is formed by additionally injecting a gas containing Group 5 impurities in the chemical vapor deposition process for forming the amorphous silicon film. At this time, the gas is preferably hydrogen phosphide gas (PH ₃ ).

Group 5 impurity phosphorus included in the amorphous silicon film preferably has a content of about 1E ¹⁵ / Cm ² or less. This is for easily forming a source-drain region having an LDD structure formed by ion implantation of impurities.

Chemical vapor deposition processes for forming the amorphous silicon film may include, for example, low-pressure plasma chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). .

 The poly-silicon channel layer is formed by forming an amorphous silicon pattern by patterning an amorphous silicon film containing impurities by a chemical vapor deposition process and then crystallizing the amorphous silicon pattern. At this time, the crystallization of the amorphous silicon pattern is performed by irradiating a high energy laser beam.

The thin film transistor manufacturing method according to the present invention can form a poly-silicon channel layer having an N channel without performing a separate ion implantation process. Therefore, the process of activating the impurities present in the poly-silicon channel layer does not need to be further performed. The poly-silicon channel layer having the N channel may adjust a shift negative value of the threshold voltage of the thin film transistor, thereby preventing leakage current when the thin film transistor is driven. In addition, it is possible to prevent deterioration of display characteristics of the liquid crystal display.

Hereinafter, a poly-silicon thin film transistor according to an embodiment of the present invention and a manufacturing method of a display device including the same will be described.

<Example 1 of Poly-silicon thin film transistor>

1 is a cross-sectional view of a poly-silicon thin film transistor according to a first embodiment of the present invention.

Referring to FIG. 1, a thin film transistor according to a first exemplary embodiment of the present invention will be described. The thin film transistor includes a polysilicon channel layer including a channel region (not shown) and a source-drain region containing group 5 impurities as a whole. And the gate insulating film 130, the gate electrode 142, the interlayer insulating layer 150, the source electrode 162, and the drain electrode 164. Hereinafter, the poly-silicon thin film transistor will be described in more detail.                     

The substrate 105 on which the poly-silicon thin film transistor is formed is a quartz substrate through which light is transmitted, and a blocking film 110 is formed on the substrate. The blocking film 110 is formed on the quartz substrate 105, and poly-silicon is formed on the upper surface of the blocking film such as sodium ions (Na ⁺ ) or the like, which have a fatal adverse effect on the semiconductor material (channel layer) from the quartz substrate. It blocks the ions so as not to affect the channel layer 120.

The poly-silicon channel layer 120 is formed by forming an amorphous silicon film pattern including a Group 5 impurity and crystallizing the amorphous silicon film pattern by laser crystallization. In addition, the poly-silicon channel layer 120 includes two impurity-implanted source-drain regions 122a and 122b and an N-type channel (not shown) including group 5 impurities.

Group 5 impurities in the N-type channel have a content of about 1E ¹⁵ / Cm ² or less. The poly-silicon channel layer 120 having a channel containing the Group 5 impurity prevents a malfunction of the gate shift resistor circuit and adjusts a negative shift value of the threshold voltage when the poly-silicon thin film transistor is driven so that the leakage current is increased. Has properties to be prevented.

The gate insulating layer 135 is provided between the poly-silicon channel layer 120 and the gate electrode 142, and prevents the short between the poly-silicon channel layer 120 and the gate electrode 142. The gate insulating layer 130 has a very high resistance and a transparent material.

The gate electrode 142 is provided on the gate insulating layer 130 to correspond to the poly-silicon channel layer 120. The gate electrode 142 serves to make the poly-silicon channel layer 120 selectively be a conductor or a non-conductor. On the other hand, the gate electrode 142 is mutually insulated from another conductive thin film, for example, the source electrode 162 and the drain electrode 164 to be described later by the interlayer insulating layer 150.

As such, the contact holes 155a and 155b are provided in the interlayer insulating layer 150 and the gate insulating layer 130 that insulate the gate electrode 142a such that the top surface of the poly-silicon channel layer 120 is exposed to the outside. . In detail, the contact holes 155a and 155b are provided at left and right sides of the gate electrode 140a around the gate electrode 140a. Hereinafter, the contact hole shown by reference numeral 155a is defined as a source electrode contact hole, and the contact hole shown by reference numeral 155b is defined as a drain electrode contact hole.

The source electrode 162 is electrically connected to the source region of the poly-silicon channel layer 120 via the source electrode contact hole 155a, and the drain electrode 164 is connected to the polyelectrode through the drain electrode contact hole 155b. -Electrically connected to the drain region of the silicon channel layer 120.

Referring to the operation of the thin film transistor according to an embodiment of the present invention having such a configuration as follows.

First, the power applied to the source electrode 162 may be output to the drain electrode 164 because the poly-silicon channel layer 120 cannot transport electrons when power is applied to the source electrode 162. none. On the other hand, when power is applied to the gate electrode 142a while power is applied to the source electrode 162, the electrical characteristics of the poly-silicon channel layer 120 are changed from the non-conductor to the conductor and thus the source electrode 162 is applied to the source electrode 162. The applied power is output to the drain electrode 164 via the poly-silicon channel layer 120. The poly-silicon thin film transistor which performs such an operation exhibits excellent electrical properties compared to an amorphous silicon thin film transistor or a thin film transistor having a poly-silicon channel layer containing no impurities.

<Production Method of Poly-silicon Thin Film Transistor Example-1>

2 to 8 are cross-sectional views illustrating a method of manufacturing the poly-silicon thin film transistor shown in FIG. 1.

Referring to FIG. 2, a blocking film 110 having a light transmissive property is formed on a transparent substrate, preferably a glass substrate 105 having excellent light transmittance, to have a thickness of about 5000 kPa. The blocking film preferably has a structure in which a silicon oxide film (SiO ₂ ) / silicon nitride film (SiN) is stacked. The blocking layer 110 is formed to have a uniform thickness by a chemical mechanical deposition (CVD) process. The blocking layer 110 blocks sodium ions (Na ⁺ ), etc., from the quartz substrate 105 that have a fatal adverse effect on the poly-silicon channel layer so as not to affect the semiconductor material formed on the upper surface of the blocking layer 110. Play a role.

Referring to FIG. 3, an amorphous silicon film 115 including phosphorus (P), which is a Group 5 impurity, is formed on the glass substrate 105 on which the blocking film 110 is formed to have a thickness of about 500 μm to about 1000 μm. The amorphous silicon film 115 is formed by performing a chemical vapor deposition process. In the chemical vapor deposition process, a gas containing Group 5 impurities is additionally introduced. The amorphous silicon film 115 formed by the chemical vapor deposition process in which the Group 5 impurity gas is additionally introduced contains Group 5 impurities.

The Group 5 impurity is phosphorus (P) or arsenic (As), and hydrogen phosphide (PH ₃ ) is preferably used as the gas. Group 5 impurity phosphorus included in the amorphous silicon film 120 preferably has a content of about 1E ¹⁵ / Cm ² or less. In addition, the chemical vapor deposition process for forming the amorphous silicon film 120 may include, for example, low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD). A step is mentioned.

Referring to FIG. 4, a polysilicon channel layer 120 is formed by performing a process of crystallizing the amorphous silicon film after patterning the amorphous silicon film 115 including the Group 5 impurities by applying an etching mask. At this time, the crystallization of the amorphous silicon is performed by irradiating a high energy laser beam, the poly-silicon channel layer includes a Group 5 element.

Referring to FIG. 5, the gate insulating layer 130 is formed to have a thickness of about 500 μm to about 1000 μs on the resultant product on which the poly-silicon channel layer 120 is formed. The gate insulating layer 130 is a silicon oxide film and is formed by an enhanced plasma chemical vapor deposition process. The gate insulating layer 130 prevents a short between the poly-silicon channel layer 120 and the gate electrode 142.                     

Referring to FIG. 6, a gate electrode 142 is formed on the gate insulating layer 130.

Referring to the formation of the gate electrode in detail, first, a metal film is formed on the gate insulating film. The metal film is an aluminum alloy film formed of an aluminum alloy, an aluminum-neodymium alloy material by a thickness of 3000 kPa by a sputtering deposition method. Subsequently, after forming a photoresist pattern (not shown) defining a formation region of the preliminary gate electrode on the metal film, the metal film exposed to the photoresist pattern is patterned. Thereafter, the photoresist pattern is removed to complete the gate electrode 142.

Referring to FIG. 7, an impurity (P ⁺ ) is implanted into the poly-silicon channel layer 120 exposed by the gate electrode by applying a gate electrode as an ion implantation mask. Reference numerals 122a and 122b will be given to regions in which impurities of the poly-silicon channel layer are ion-implanted, that is, source-drain regions.

Referring to FIG. 8, an interlayer insulating layer 150 is formed on the quartz substrate 105 on which the gate insulating film is formed to cover the gate electrode 142. The interlayer insulating layer preferably has a structure in which a silicon oxide film (SiO ₂ ) having a thickness of about 4500 GPa and a silicon nitride film (SiN) having a thickness of about 1500 GPa are stacked.

Subsequently, after forming the interlayer insulating layer 150, an etching mask (not shown) defining a contact hole forming region for selectively exposing the source-drain region is formed. Subsequently, the interlayer insulating layer 150 and the gate insulating layer 130 exposed to the etch mask are sequentially patterned to open source-drain contact holes for opening the source-drain regions 122a and 122b of the poly-silicon channel layer. 155a and 155b are formed. The source-drain contact holes are formed at both sides of the gate electrode 140a.

Subsequently, the source-drain contact holes 155a and 155b are buried to form a metal film covering the interlayer insulating layer. The metal film is preferably formed by sputter deposition of an aluminum alloy material. Subsequently, an etch mask (not shown) is applied to selectively pattern the metal film exposed to the etch mask to form the source-drain electrodes 162 and 164, thereby completing the poly-silicon thin film transistor shown in FIG. 1. The poly-silicon thin film transistor including the poly-silicon channel layer having the N-channel containing the Group 5 impurities may prevent the occurrence of leakage current during driving.

<Example 2 of Poly-silicon thin film transistor>

9 is a cross-sectional view of a poly-silicon thin film transistor according to a second embodiment of the present invention. Compared with FIG. 1, the same reference numerals are assigned to the same components, and detailed description thereof will be omitted.

Referring to FIG. 9, a thin film transistor according to a second exemplary embodiment of the present invention will be described. The thin film transistor may include a channel region (not shown) and a source-drain region having an LDD structure. A silicon channel layer 220, a gate insulating film 130, a gate electrode 242a, an interlayer insulating layer 250, a source electrode 262, and a drain electrode 264. Hereinafter, the poly-silicon thin film transistor will be described in more detail.                     

The poly-silicon channel layer 220 is formed by forming an amorphous silicon film pattern including a group 5 impurity and crystallizing the amorphous silicon film pattern by a laser crystallization method. In addition, the poly-silicon channel layer 220 includes two high concentration impurity regions 222a and 222b in which impurities are ion-implanted in the first dose amount, and low concentration impurities in which the impurities are ion-implanted in the second dose amount less than the first dose amount. A source-drain region having a lightly doped drain (LDD) structure including regions 222c and 222d, and an N-type channel (not shown) including a group 5 impurity. Group 5 impurities in the N-type channel preferably have a content of about 1E ¹⁵ / Cm ² or less.

The high concentration impurity regions 222a and 222b are formed to be spaced first inwardly from both edges of the channel layer 220, and the low concentration impurity regions 222c and 222d are formed from the high concentration impurity regions 222a and 222b. It is formed up to two distances apart. The N channel region exists between the low concentration impurity regions 212c and 212d. The poly-silicon channel layer 220 having a channel containing the Group 5 impurity can prevent the gate shift resistance circuit from malfunctioning when the poly-silicon thin film transistor is driven, and adjust the negative shift value of the threshold voltage so that the leakage current is increased. Has properties to be prevented.

<Example 2 of Manufacturing Process of Poly-silicon Thin Film Transistor>

10 to 14 are cross-sectional views illustrating a method of manufacturing the poly-silicon thin film transistor illustrated in FIG. 9. 2 and 8, the same components are assigned the same reference numerals, and detailed description thereof will be omitted.

Referring to FIG. 10, a preliminary gate electrode having a structure in which the first metal film 242 and the second metal film 244 are sequentially stacked is formed on the resultant obtained in FIG. 4.

The formation of the preliminary gate electrode will be described in detail. First, the first metal film 242 and the second metal film 244 are sequentially formed on the gate insulating film. Here, the first metal film is an aluminum alloy film formed of aluminum alloy, aluminum-neodymium alloy material by a thickness of 3000 kPa by a sputtering deposition method. The second metal film 244 is a chromium film formed to a thickness of 1500 kPa by the sputtering deposition method.

Subsequently, after forming a photoresist pattern (not shown) defining a formation region of the preliminary gate electrode on the second metal film 244, the second metal film and the first metal film exposed to the photoresist pattern are sequentially formed. Pattern. Thereafter, the photoresist pattern is removed to complete the preliminary gate electrode.

Referring to FIG. 11, a high concentration of impurities (P ⁺ ) are implanted into the poly-silicon channel layer exposed by the gate electrode by applying a preliminary gate electrode as a first ion implantation mask. Reference numerals 222a and 222b will be given to regions in which the high concentration impurity is ion-implanted in the poly-silicon channel layer. High concentration impurity regions 222a and 222b are formed in the poly-silicon channel layer by ion implantation of the high concentration impurity. The high concentration impurity regions 222a and 222b are formed from the edges of the poly-silicon channel layer 220 to the first length spaced inwardly.

Referring to FIG. 12, an etchant or an etching gas is used to etch the first metal layer under the second metal layer to be under-cut. At this time, artificially under-cutting the first metal layer is to form a source-drain region having an LDD structure by injecting impurities into the poly-silicon channel layer 220 at different concentrations. to be. Thereafter, a predetermined etching process is performed to remove the second metal layer to form the gate electrode 242a.

Referring to FIG. 13, a low concentration of impurity P ⁻ is implanted into the poly-silicon channel layer 220 exposed by the gate electrode by applying the gate electrode 242a as a second ion implantation mask. Reference numerals 222c and 222d will be given to the impurity regions in which the low concentration impurities are ion-implanted in the poly-silicon channel layer. Low concentration impurity regions 222c and 222d are formed in the poly-silicon channel layer by the ion implantation of the low concentration impurity. That is, by forming a high concentration impurity region and a low concentration impurity region in the poly-silicon channel layer, a source-drain region having an LDD structure is formed.

Referring to FIG. 14, an interlayer insulating layer 250 is formed on the quartz substrate 105 on which the gate insulating film is formed to cover the gate electrode 242a. The interlayer insulating layer preferably has a structure in which a silicon oxide film (SiO ₂ ) having a thickness of about 4500 GPa and a silicon nitride film (SiN) having a thickness of about 1500 GPa are stacked.

Subsequently, the interlayer insulating layer 250 and the gate insulating layer 130 exposed to the etch mask are sequentially patterned to open the source-drain contact hole 255a for opening the high concentration impurity regions 222a and 222b of the poly-silicon channel layer. , 255b). The source-drain contact holes are formed at both sides of the gate electrode 242a.

Subsequently, source-drain contact holes 255a and 255b exposing the high concentration impurity regions 222a and 222b are buried, and a metal film covering the interlayer insulating layer is formed. The metal film is preferably formed by sputter deposition of an aluminum alloy material. Subsequently, an etch mask (not shown) is applied to selectively pattern the metal film exposed to the etch mask to form the source-drain electrodes 262 and 264, thereby completing the poly-silicon transistor shown in FIG. 10. The source electrode 262 is electrically connected (or contacted) to the high concentration ion implantation region 222a of the source region through the source contact hole 255a. In addition, the drain electrode 264 is electrically connected to (or contacted with) the high concentration ion implantation region 122b of the drain region through the drain contact hole 155b.

Example of Manufacturing Method of Display Pixel

15 and 16 are cross-sectional views illustrating a method of manufacturing a display device including the poly-silicon thin film transistor illustrated in FIG. 9. Here, since the method of manufacturing the poly-silicon thin film transistor shown in FIG. 15 is the same as that described in Embodiment 2, the drawings and detailed description thereof will be omitted.

Referring to FIG. 15, an insulating layer 270 is formed on a substrate on which the poly-silicon thin film transistor illustrated in FIG. 10 is formed. The insulating layer 270 may be formed of an inorganic insulating material such as silicon nitride or silicon oxide, or may be formed of low organic materials such as acrylic organic compounds, Teflon, BCB (benzocyclobutene), cytop, or perfluorocyclobutane (PFCB). It is formed of an organic insulating material having a dielectric constant. In addition, the insulating layer 270 may not be formed due to the efficiency of the process.

Subsequently, the insulating layer 270 is selectively patterned using a photolithography process to form the contact hole 272. A portion of the drain electrode 264 is exposed through the contact hole 272.

Referring to FIG. 16, a transparent electrode layer, which is a transparent conductive material, is deposited on the insulating layer 270 and then patterned. Examples of the transparent conductive material include indium-tin-oxide (ITO), indium-zinc-oxide (IZO), and indium-tin-zinc-oxide (Oxide). ), And the like. The patterned transparent electrode layer is formed of the pixel electrode 280 in the pixel region. In addition, the drain electrode 264 and the pixel electrode 280 are electrically connected to the pixel electrode 280 through the contact hole 172.

In the above description, a display device having a poly-silicon thin film transistor according to an embodiment of the present invention and a method of manufacturing the same have been described, but those skilled in the art will likewise apply to the display device having a poly-silicon thin film transistor according to another embodiment of the present invention. Applicability is obvious.

As described in detail above, the thin film transistor manufacturing method according to the present invention may form a poly-silicon channel layer having an N channel without performing a separate ion implantation process.

Therefore, the process of activating the impurities present in the poly-silicon channel layer does not need to be further performed. In addition, the poly-silicon channel layer having the N channel may adjust a shift negative value of the threshold voltage of the thin film transistor, thereby preventing leakage current when the thin film transistor is driven. In addition, the display pixel including the poly-silicon thin film transistor does not generate the leakage current of the thin film transistor, thereby preventing the display characteristics of the liquid crystal display from being lowered.

In the present invention has been described the technical spirit of the present invention as a preferred embodiment, those skilled in the art to which the present invention belongs to various modifications within the scope of the claims described below It is apparent that the embodiments can be implemented, and such modified embodiments are obviously within the scope of the present invention.

Claims (10)

Forming an amorphous silicon film containing a Group 5 impurity on the substrate; Crystallizing the amorphous silicon film to form a poly-silicon channel layer; Continuously forming a gate insulating film on the poly-silicon channel layer; Forming a gate electrode on the gate insulating film; Implanting impurities into the poly-silicon channel layer exposed to the gate electrode to form a source-drain region; Forming an interlayer dielectric layer having a contact hole exposing the source-drain region; And And forming a source electrode and a drain electrode electrically connected to the source-drain region through the contact hole, respectively. The method of claim 1, wherein the substrate is formed by forming a blocking film on a transparent substrate. The method of claim 1, wherein the forming of the amorphous silicon film comprises: A method of manufacturing a poly-silicon thin film transistor, characterized in that to form an amorphous silicon film containing a Group 5 impurity by additionally injecting a gas containing a Group 5 impurity during the chemical vapor deposition process for forming an amorphous silicon film on the substrate. The method of claim 3, wherein the gas is hydrogen phosphide gas (PH ₃ ). The method of claim 3, wherein the chemical vapor deposition process is a low pressure plasma chemical vapor deposition (LPCVD) or enhanced plasma chemical vapor deposition (PECVD) process. The method of claim 1, wherein the forming of the poly-silicon channel layer, Patterning the amorphous silicon film to form an amorphous silicon pattern; And And forming a poly-silicon channel layer by performing a process of crystallizing the amorphous silicon pattern. The method of claim 7, wherein the crystallization of the amorphous silicon film is performed by irradiating a high energy laser beam. Further providing a gas containing a Group 5 impurity in a chemical vapor deposition process for depositing an amorphous silicon material to form an amorphous silicon film including a Group 5 impurity on the substrate; Crystallizing the amorphous silicon film to form a poly-silicon channel layer; Continuously forming a gate insulating film on the poly-silicon channel layer; Forming a preliminary gate electrode having a structure in which a first metal and a second metal are stacked on the gate insulating layer; Implanting a high concentration of impurities into the poly-silicon channel layer exposed to the preliminary gate electrode; Performing a process of etching the preliminary gate electrode to form a gate electrode including a first metal having an undercut side surface thereof; Implanting a low concentration of impurities into the poly-silicon channel layer exposed to the gate electrode to form a source-drain region having an LDD structure Forming an interlayer dielectric layer pattern having contact holes exposing the source-drain regions, respectively; And And forming a source electrode and a drain electrode electrically connected to the source-drain region in the contact hole, respectively. The method of claim 8, wherein the chemical vapor deposition process is a low pressure plasma chemical vapor deposition (LPCVD) or enhanced plasma chemical vapor deposition (PECVD) process. Further providing a gas containing a Group 5 impurity in a chemical vapor deposition process for depositing an amorphous silicon material to form an amorphous silicon film including a Group 5 impurity on the substrate; Crystallizing the amorphous silicon film to form a poly-silicon channel layer; Continuously forming a gate insulating film on the poly-silicon channel layer; Forming a preliminary gate electrode having a structure in which a first metal and a second metal are stacked on the gate insulating layer; Implanting a high concentration of impurities into the poly-silicon channel layer exposed to the preliminary gate electrode; Performing a process of etching the preliminary gate electrode to form a gate electrode including a first metal having an undercut side surface thereof; Implanting a low concentration of impurities into the poly-silicon channel layer exposed to the gate electrode to form a source-drain region having an LDD structure; Forming an interlayer dielectric layer pattern having contact holes exposing the source-drain regions, respectively; Forming a source electrode and a drain electrode electrically connected to the source-drain region in the contact hole; And And forming a pixel electrode electrically connected to the drain electrode.

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