KR100600845B1 - Method of Manufacturing a Flat Panel Display Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flat panel display device having at least one TFT, wherein a semiconductor layer is formed on a substrate, a gate insulating film is formed on the entire surface of the substrate so as to cover the semiconductor layer, and a top surface of the gate insulating film is formed. Isotropic etching property is strong and low resistance metal and ion barrier wall forming material are sequentially deposited, and then ion barrier wall forming material is etched first to form ion barrier wall and low resistance metal for LDD and offset After etching to form a gate electrode that is narrower than the ion blocking wall, ions having a predetermined concentration are implanted into the semiconductor layer, and the ion blocking wall is removed.

Then, since the gate electrode is formed of a low resistance metal, delay of the signal can be minimized.

In addition, since the non-metallic material and the gate metal are etched by the dry etching method, the gate electrode and the ion barrier wall can be finely patterned.

In addition, since the ion blocking layer is formed in a self-aligning manner by using the isotropic etching property of the gate metal, it is possible to easily form offset and LDD preventing leakage current without additional equipment and mask process.

Isotropic Etching Properties, Dry Etching, Offset Structure, LDD Structure

Description

Method of manufacturing a flat panel display device

1 is a conceptual diagram conceptually showing a pixel area of a liquid crystal display according to the present invention;

2A and 2B are cross-sectional views illustrating a process of forming a buffer layer and a semiconductor layer according to the present invention.

3 is a cross-sectional view showing a process of forming a gate insulating film according to the present invention.

4A and 4C are cross-sectional views illustrating a process of forming a gate electrode and an ion blocking film according to the present invention.

5 is a cross-sectional view showing a process of implanting a high concentration of ions into the semiconductor layer according to the present invention.

6 is a cross-sectional view showing a state in which an ion blocking film formed on an upper surface of a gate electrode according to the present invention is removed.

7 is a cross-sectional view showing a process of implanting low concentration ions into the semiconductor layer according to the present invention.

8 is a cross-sectional view illustrating a process of forming a source / drain insulating film and forming a contact hole in the source / drain insulating film according to the present invention.

9 is a cross-sectional view showing a state in which a source / drain electrode according to the present invention is formed.

10 is a cross-sectional view showing a state in which a pixel electrode is formed in a planarization protective film according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a flat panel display, and more particularly, to form a gate electrode using a metal having low resistance while showing strong isotropic etching, and to form an ion barrier layer wider than the width of the gate electrode on an upper surface of the gate electrode. The present invention relates to a flat panel display manufacturing method for improving reliability of a product by precisely forming an off-set or LDD in a semiconductor layer to minimize leakage current when the gate electrode is turned off.

Cathode ray tube (CRT), which is one of the commonly used display devices, is mainly used for monitors such as TVs, measuring devices, information terminal devices, etc., but the miniaturization of electronic products due to the weight and size of the CRT itself It cannot actively respond to the demand for weight reduction.

In order to replace such a CRT, a flat panel display device having the advantages of small size and light weight has been attracting attention. Among flat panel displays, a liquid crystal display that displays information by using the electro-optical properties of liquid crystals injected into the LCD panel, and an organic electroluminescent display in which organic materials self-emit by a current flow are active. In recent years, as the information society is socialized, the importance of the liquid crystal display and the organic light emitting display is gradually increasing.

Hereinafter, a liquid crystal display will be described as an example among flat panel displays.

The liquid crystal display device is a TFT substrate on which a thin film transistor element (hereinafter referred to as TFT) is formed, a color filter substrate in which red, green, and blue color filters are arranged in a matrix, and is injected between a TFT substrate and a color filter substrate to be electrically It consists of the liquid crystal reacting by an optical property.

Here, in the TFT substrate, a plurality of signal lines arranged in a matrix form, pixel regions, which are formed at intersection regions of the signal lines and display predetermined information due to the characteristics of the liquid crystal, are formed in each pixel region, and have a switching role. And a charging capacitor which is connected to a pixel electrode formed at a predetermined portion of the pixel region to maintain a signal voltage applied to the pixel electrode for a predetermined time.

The signal lines arranged in a matrix form are composed of gate lines for transmitting the on / off signal of the TFT and data lines for crossing the gate lines and for transmitting a data voltage to the TFT.

The TFT is largely composed of a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode electrically connected to the pixel electrode, and a semiconductor layer electrically connected to the source / drain electrode.

In the TFT thus constructed, a gate insulating film is formed between the semiconductor layer and the gate electrode to insulate the semiconductor layer and the gate electrode, and a source / drain insulating film is formed between the gate electrode and the source / drain electrode to insulate them. A protective film is formed between the source / drain electrodes and the pixel electrodes to insulate them and to protect the source / drain electrodes.

Meanwhile, among the signal lines, gate lines are formed together when the gate electrode is formed, and data lines are formed together when the source / drain electrode is formed.

In order to improve the electrical characteristics of the semiconductor layer and minimize the amount of current leaked when the gate electrode is turned off in the TFT configured as described above, ions are implanted into the semiconductor layer and low concentration ions are implanted in the semiconductor layer. It is formed into an LDD structure that is divided into a region to be formed and a region into which a high concentration of ions are implanted. Or an off-set structure in which the semiconductor layer is divided into a region where no ions are implanted, a region where ions are implanted, and an region where ions are not implanted, and an region where ions are implanted to minimize the leakage current. Form.

The method of forming the off-set or LDD structure in the semiconductor layer will be described below with reference to the two methods most commonly used.

In the first method, a photoresist is applied to the top surface of the gate electrode, the photoresist is etched so as to surround the top surface from the top surface of the gate electrode, and an ion barrier wall is formed on the gate electrode. To form an off-set structure. Then, a doped region is formed in a portion of the semiconductor layer exposed to the outside of the ion blocking wall, and an off-set region is formed in a portion corresponding to the portion of the ion blocking wall surrounding the gate side, and corresponding to the gate electrode. A region in which no ions are implanted is formed in the portion.

On the other hand, the LDD structure forms an ion barrier wall with a photoresist to surround the gate electrode, and then implants a high concentration of ions to form a highly doped region in the semiconductor layer exposed to the outside of the ion barrier wall, and then removes the ion barrier wall. A low concentration doped region is formed between the portion corresponding to the gate electrode and the high concentration doped region by implanting low concentration ions into the semiconductor layer. Here, the portion corresponding to the gate electrode is a region where no ions are implanted.

However, in the process of exposing the photoresist surrounding the gate electrode when forming the offset or LDD structure by the first method described above, the mask cannot be accurately aligned so that the photo having the same width on both sides of the gate electrode with respect to the gate electrode It is difficult to form a resist. Therefore, it is difficult to obtain uniform electrical characteristics.

In addition, a mask is further used to pattern the photoresist surrounding the gate electrode.

The second method oxidizes the gate electrode to form an oxide film (for example, an Al ₂ O ₃ film) on the gate electrode, and then implants ions, thereby forming a doped region in the exposed portion of the oxide film, and forming a doped region in the oxide film. An off-set region is formed in a portion corresponding to the portion surrounding the gap, and a region in which ions are not implanted is formed in the portion corresponding to the gate electrode.

On the other hand, the LDD structure is formed through the same process as the first method.

In the case of forming the off-set or LDD structure by the second method, expensive equipment for oxidizing the gate electrode is required.

Accordingly, it is an object of the present invention to simply form an ion barrier wall in a self-aligned manner (by forming doping barrier films of the same width on both sides of the electrode) without investing new equipment and using masks.

In addition, an object of the present invention is to form a gate electrode using a metal having a low resistance while showing strong isotropic etching.

Still other objects of the present invention will become more apparent from the following detailed description and the accompanying drawings.

In order to achieve the above object, the present invention forms a semiconductor layer on a substrate, forms a gate insulating film on the entire surface of the substrate to cover the semiconductor layer, and exhibits strong isotropic etching property on the upper surface of the gate insulating film and low resistance. After the deposition of the resistive metal and the ion barrier wall forming material sequentially, the ion barrier wall forming material is etched first to form an ion barrier wall, and the low resistance metal is etched to form a gate that is narrower than the ion barrier wall on the lower surface of the ion barrier wall. After forming the electrode, ions having a predetermined concentration are implanted into the semiconductor layer, and the ion barrier wall is removed to form the semiconductor layer in a predetermined structure.

Preferably, when a single ion implantation process is performed, the semiconductor layer is formed in a doping region formed in a portion corresponding to the portion exposed to the outside of the ion blocking wall, and in a portion corresponding to the ion blocking wall drawn out of the gate electrode. An off-set structure is formed in which the ions formed in the portion corresponding to the gate electrode and the off-set region for blocking the leakage current are divided into undoped regions.

Preferably, after removing the ion barrier wall and implanting ions having a high concentration, and after removing the ion barrier wall again implanting ions having a low concentration, the semiconductor layer is formed in a portion corresponding to the portion exposed to the outside of the ion barrier wall LDD structure that is divided into a high concentration doped region, a region doped with ions formed in a portion corresponding to the gate electrode, and a low concentration doped region formed between an undoped region and a high concentration doped region to block leakage current Is formed.

In one example, the ion barrier is formed of a nonmetallic material such as SiNx, SiO ₂ .

In another example, the ion barrier wall is formed of photoresist.

Preferably, the material forming the ion barrier wall and the low resistance metal forming the gate electrode are finely etched by a dry etching method.

The present invention is applied to a flat panel display device having at least one TFT. The present invention will be described below with reference to FIGS. 1 to 10 with an example of a method of manufacturing a liquid crystal display device having a simple structure.

The liquid crystal display device 100 according to the present invention includes a TFT substrate 101 on which TFTs are formed, a color filter substrate (not shown) and a TFT substrate 101 on which red, green, and blue color filters are arranged in a matrix form. And a liquid crystal (not shown) injected between the color filter substrate and reacted with electrical and optical properties.

On the TFT substrate 101, a plurality of signal lines arranged in a matrix form as shown in FIG. 1 and pixel regions 107 respectively formed at intersection regions of the signal lines are formed.

The signal lines are formed of gate lines 103 for applying a voltage for turning TFTs on and off, and data lines 105 for vertically crossing the gate lines 103 and for applying a data voltage to the pixel region 107. .

Inside each pixel region 107 formed at the intersection of the gate lines 103 and the data lines 105, a liquid crystal TFT is electrically connected to the TFT and the TFT, which drives the liquid crystal together with the common electrode formed on the color filter substrate. The pixel electrode 190 is formed.

1 and 10, the gate insulating layer 130 electrically insulating the upper electrode and the semiconductor layer 120 by covering the semiconductor layer 120 and the semiconductor layer 120 formed adjacent to the signal lines, as shown in FIGS. 1 and 10. A source / drain which electrically insulates the upper electrode and the gate electrode 140 by covering the gate electrode 140 and the gate electrode 140 formed at the center of the semiconductor layer 120 from the upper surface of the gate insulating layer 130. A source / drain electrode connected to the semiconductor layer 120 through a contact hole 165 formed on the insulating layer 160 and the source / drain insulating layer 160 and formed in a predetermined portion of the source / drain insulating layer 160 ( 170 and 175 and the source / drain electrodes 170 and 175, and a protective insulating layer 180 having a pixel contact hole for connecting the pixel electrode 190 and the drain electrode 175 to a predetermined portion.

For example, the semiconductor layer 120 has a high concentration doping region 122 formed by implanting high concentration ions and a low concentration doping region 124 which blocks a current injected when low concentration ions are injected and the gate electrode 140 is turned off. ) And the region 126 into which the ions formed in the portion corresponding to the gate electrode 140 are not implanted due to the ion blocking of the gate electrode 140. Here, the lightly doped region 124 is formed between the region 126 where the ions are not implanted and the heavily doped region 122 to separate the heavily doped region 122 from the side surface of the gate electrode 140 by a predetermined distance.

Although not illustrated in the drawing, as another example, the semiconductor layer 120 is spaced apart from the doped region into which a predetermined concentration of ions are implanted from the side of the gate electrode 140 by a predetermined distance to turn off the gate electrode 140. An off-set region that blocks a leakage current and an ion barrier of the gate electrode 140 are divided into regions in which ions formed in a portion corresponding to the gate electrode 140 are not implanted. Here, the off-set region is formed between the region where the ions are not implanted and the doping region.

On the other hand, the gate electrode 140 is formed of a low resistance metal with strong isotropic etching properties and low resistance.

The pixel electrode 190 is formed on the upper surface of the protective insulating layer 180 as shown in FIG. 10.

A method of manufacturing a TFT substrate of a liquid crystal display device configured as described above will be described with reference to FIGS. 2 to 10 as follows. Here, the method for forming the LDD structure in the semiconductor layer will be mainly described, and the structure for forming the off-set structure will be briefly mentioned.

2 to 10 illustrate a manufacturing process of a TFT and a pixel electrode which are shown when FIG. 1 is cut along the line A-A.

First, as shown in FIG. 2A, the SiO ₂ material and the amorphous silicon are sequentially applied to the entire upper surface of the TFT substrate 101, and then, the laser is irradiated to the amorphous silicon to form the amorphous silicon as poly-Si (120a). Crystallize with.

Subsequently, as illustrated in FIG. 2B, the polysilicon 120a is patterned to form the semiconductor layer 120 at a predetermined portion adjacent to the gate line 155. Here, the SiO ₂ material applied to the upper surface of the TFT substrate 101 becomes a buffer layer 110 that blocks impurities such as sodium ions generated from the lower substrate from flowing into the semiconductor layer 120.

Subsequently, a gate insulating layer 130 is formed by coating a predetermined insulating material on the entire surface of the TFT substrate 101 on which the semiconductor layer 120 is formed as shown in FIG. 3.

Subsequently, as illustrated in FIG. 4A, a gate metal 140a isotropically etched with respect to an etching gas and low resistance is deposited on the top surface of the gate insulating layer 130, and an ion blocking layer is formed on the top surface of the gate metal 140a. The material 150a is deposited. Thereafter, the photoresist 155 for the photolithography and development process is applied to the upper surface of the ion barrier layer forming material 150a, and a photolithography process and a dry etching process are performed to remove the gate metal 140a as shown in FIG. 4B. An ion blocking layer 150 is formed on a portion of the upper surface corresponding to the semiconductor layer 120.

Subsequently, the gate electrode 140 is formed on the lower surface of the ion blocking layer 150 by supplying a predetermined gas for dry etching the gate metal to the etching chamber (not shown). In this case, since the gate metal 140a is formed of a metal having strong isotropic etching property, when the etching gas is injected, the gate metal 140a is etched isotropically to be etched to a width narrower than the width of the ion blocking layer 150. Accordingly, as shown in FIG. 4C, both end portions of the ion blocking layer 150 protrude outside the gate electrode 140 by a predetermined length.

Preferably, the material forming the ion barrier layer 140 is a non-metal such as SiO ₂ ^, SiNx or photoresist.

When the gate electrode 140 and the ion blocking layer 150 are formed on the upper surface of the gate insulating layer 130, the electrical characteristics of the semiconductor layer 120 may be improved and the amount of current leaked when the gate electrode 140 is turned off is measured. In order to minimize the high concentration of ions are implanted in the semiconductor layer 120 as shown in FIG.

At this time, the ion implanted in the portion corresponding to the ion blocking film 150 among the high concentration of ions injected into the semiconductor layer 120 is blocked by the ion blocking film 150 and does not reach the semiconductor layer 120. Therefore, since a high concentration of ions are implanted only in predetermined portions of both ends of the semiconductor layer 120 exposed to the outside of the ion blocking layer 150, the highly doped regions 122 are formed at both ends of the semiconductor layer 120.

As described above, when the highly doped regions 122 are formed at both ends of the semiconductor layer 120 through the ion implantation process, the ion blocking layer 150 formed on the upper surface of the gate electrode 140 is removed as shown in FIG. 6. . As shown in FIG. 7, a low concentration doping region is implanted into a region corresponding to a portion from both sides of the gate electrode 140 to the point where the high concentration doping region 122 starts by implanting low concentration ions into the semiconductor layer 120. 124 is formed. Here, the lightly doped region 124 separates the heavily doped region 122 from the side surface of the gate electrode 140 by a predetermined distance to block leakage current when the gate electrode 140 is turned off.

The region 126 in which no ions are implanted is formed in a portion corresponding to the gate electrode 140.

Meanwhile, when the off-set structure is formed in the semiconductor layer 120, the semiconductor layer 120 exposed to the outside of the ion blocking layer 150 by implanting ions having a predetermined concentration before removing the ion blocking layer 150. A doped region is formed in the ion barrier layer 150. Then, a region where ions are not implanted is formed in a portion corresponding to the gate electrode 140, and an off-set region is formed between the doped region and the region where the ions are not implanted.

As described above, when the semiconductor layer 120 is divided into a high concentration doped region 122 (or a doped region), a low concentration doped region 124 (or an offset region), and a region 126 into which no ions are implanted, As illustrated, a predetermined insulating material is coated on the entire surface of the TFT substrate 101 to cover the gate electrode 140 to form a source / drain insulating layer 160 that insulates the gate electrode 140 and the upper electrode. Subsequently, a contact hole 165 is drilled in a predetermined portion of the source / drain insulating layer 160 corresponding to both ends of the semiconductor layer 120 to the outside of the gate insulating layer 130 and the source / drain insulating layer 160. A predetermined portion of 120 is exposed.

When the contact holes 165 are formed as described above, the source / drain metal is deposited on the top surface of the source / drain insulating layer 160, and the source / drain metal is patterned to form the source / drain insulating layer (as shown in FIG. 9). Source / drain electrodes 170 and 175 are formed at predetermined portions of 160.

Here, the source electrode 170 is formed at a portion corresponding to one end of the semiconductor layer 120, one end of the source electrode 170 is connected to the data line 105 as shown in FIG. 1 and the source electrode ( The other end of the 170 is connected to one end of the semiconductor layer 120 through the contact hole 165 as shown in FIG. 9. The drain electrode 175 is formed at a portion corresponding to the other end of the semiconductor layer 120, and one end thereof is connected to the other end of the semiconductor layer 120 through the contact hole 165 as shown in FIG. 9. do.

When the source / drain electrodes 170 and 175 are formed, a predetermined insulating material is applied to the upper surfaces of the source / drain electrodes 170 and 175 as shown in FIG. 10 to protect the source / drain electrodes 170 and 175 from the external environment, and The planarization protective layer 180 is formed to planarize the curvature of the film and to electrically insulate the source / drain electrodes 170 and 175 from the upper electrode.

Subsequently, a pixel contact hole is formed in a predetermined portion of the planarization passivation layer 180 corresponding to the drain electrode 175, and a transparent metal, for example, an ITO metal is deposited on the upper surface of the planarization passivation layer 180, and then ITO metal is formed. By patterning, the pixel electrode 190 connected to the other end of the drain electrode 175 is formed through the pixel contact hole as illustrated in FIG. 10.

As described above, according to the present invention, after the gate metal and the non-metallic material having high isotropic etching properties and low resistance are sequentially applied to the upper surface of the gate insulating film, they are etched and dried so that an ion barrier wall is formed on the portion of the gate insulating film corresponding to the semiconductor layer. And a gate electrode having a width narrower than the width of the ion blocking wall on the lower surface of the ion blocking wall.

Then, the delay of the signal can be minimized because the gate electrode is made of a low resistance metal, and the gate electrode and the ion barrier wall can be precisely patterned because the non-metal material and the gate metal are etched by the dry etching method. There is an effect that the reliability can be improved.

In addition, since the ion blocking layer is formed in a self-aligning manner by using the isotropic etching property of the gate metal, there is an effect of easily forming offset and LDD preventing leakage current without additional equipment and mask process.

Claims (9)

In the method of manufacturing a flat panel display device arranged in a matrix form and including signal lines, a TFT, and a pixel electrode, Patterning polysilicon applied to the upper surface of the substrate to form a semiconductor layer in a portion of the pixel region adjacent to gate lines; Forming a gate insulating film by applying an insulating material to the entire surface of the substrate to cover the semiconductor layer; After depositing a gate metal and an ion barrier wall forming material on the upper surface of the gate insulating layer in order, an ion barrier wall is formed on a portion of the gate insulating layer corresponding to the center of the semiconductor layer through a photolithography process and an etching process; Forming a gate electrode on the lower surface of the ion blocking wall that is narrower than the width of the ion blocking wall; Dividing the semiconductor layer into a plurality of regions to implant ions into a portion corresponding to the semiconductor layer and to remove the ion blocking wall to improve electrical characteristics of the semiconductor layer and prevent leakage current; An insulating material is coated on the upper surface of the gate electrode to form a source / drain insulating layer that insulates the double gate electrode and the upper electrode, and a contact hole is formed in a portion of the source / drain insulating layer corresponding to both ends of the semiconductor layer; Forming; Depositing a source / drain metal on an upper surface of the source / drain insulating layer and patterning the source / drain metal to form a source / drain electrode connected to the semiconductor layer through the contact hole; Forming a protective insulating film by applying an insulating material to an upper surface of the source / drain electrode, and forming a pixel contact hole in a portion of the protective insulating film corresponding to the drain electrode; And depositing a transparent metal on the upper surface of the protective insulating layer, and patterning the transparent metal to form a pixel electrode connected to the drain electrode through the pixel contact hole. Way. The method of claim 1, wherein the gate metal is a metal having strong isotropic etching properties and low resistance. The method of claim 1, wherein the material forming the ion barrier layer is a non-metallic material. The method of claim 3, wherein the nonmetal material is any one selected from SiO ₂ , SiNx, and photoresist. The method of claim 1, wherein the gate metal and the ion barrier wall forming material are etched by a dry etching method. The semiconductor layer of claim 1, wherein the semiconductor layer is formed by implanting ions into the semiconductor layer and removing the ion barrier wall. A doped region formed at both ends of the semiconductor layer exposed to the outside of the ion blocking wall and implanted with ions; A region in which no ions are implanted in a region corresponding to a portion corresponding to the gate electrode; And an off-set region formed between the doped region and the region where the ions are not implanted to block leakage current. The flat panel display of claim 1, further comprising: implanting ions having a concentration lower than that of the ion between removing the ion barrier wall and forming the source / drain insulating layer. Method of preparation. 8. The semiconductor layer of claim 7, wherein the semiconductor layer is formed by implanting ions having a concentration lower than that of the ions. A highly doped region formed at both ends of the semiconductor layer exposed to the outside of the ion blocking wall and implanted with the predetermined concentration of ions; A region in which no ions are implanted in a region corresponding to a portion corresponding to the gate electrode; And forming a low concentration doped region between the high concentration doped region and the region where the ions are not implanted and divided into a low concentration doped region to block leakage current. The method of claim 1, wherein a buffer layer is further formed between the substrate and the semiconductor layer to prevent impurities from the substrate from flowing into the semiconductor layer.

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