KR20060037799A - Semiconductor device and method for fabricating the same - Google Patents

Semiconductor device and method for fabricating the same Download PDF

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KR20060037799A
KR20060037799A KR1020040086854A KR20040086854A KR20060037799A KR 20060037799 A KR20060037799 A KR 20060037799A KR 1020040086854 A KR1020040086854 A KR 1020040086854A KR 20040086854 A KR20040086854 A KR 20040086854A KR 20060037799 A KR20060037799 A KR 20060037799A
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conductive pattern
semiconductor device
manufacturing
insulating film
interlayer insulating
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KR1020040086854A
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Korean (ko)
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김홍선
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주식회사 하이닉스반도체
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Publication of KR20060037799A publication Critical patent/KR20060037799A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 콘택플러그 사용에 따른 접족저항의 증가를 방지함과 동시에 공정을 단순화할 수 있는 반도체 소자 및 그의 제조 방법에 관한 것으로, 기판 상에 그 상부에 돌출부를 갖는 제1도전패턴을 형성하는 단계; 상기 제1도전패턴이 형성된 기판의 전면에 층간절연막을 형성하는 단계; 상기 돌출부가 노출되는 타겟으로 상기 층간절연막을 평탄화하는 단계; 및 상기 돌출부 상에 금속배선을 형성하는 단계를 포함한다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, which can prevent an increase in the resistance of contact due to the use of a contact plug and simplify the process. ; Forming an interlayer insulating film on an entire surface of the substrate on which the first conductive pattern is formed; Planarizing the interlayer insulating film with a target to which the protrusion is exposed; And forming a metal wire on the protrusion.

도전패턴, 콘택저항, 콘택플러그Conductive Pattern, Contact Resistance, Contact Plug

Description

반도체 소자 및 그의 제조 방법{SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME} Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}             

도 1a 내지 도 1d는 종래기술에 따른 반도체 소자의 제조 방법을 도시한 공정단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2는 본 발명의 바람직한 실시예에 따른 반도체 소자를 나타낸 단면도.2 is a cross-sectional view showing a semiconductor device according to a preferred embodiment of the present invention.

도 3a 내지 도 3c는 본발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 도시한 공정단면도.
3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

20 : 기판 21 : 제1도전패턴20: substrate 21: first conductive pattern

22 : 층간절연막 23 : 제2도전패턴
22: interlayer insulating film 23: second conductive pattern

본 발명은 반도체 소자 및 그의 제조 방법에 관한 것으로, 특히 콘택플러그 사용에 따른 접촉저항을 증가를 방지함과 동시에 공정을 단순화할 수 있는 반도체 소자 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device and a method for manufacturing the same, which can simplify the process while preventing an increase in contact resistance due to the use of a contact plug.

반도체 소자의 집적도가 증가함에 따라, 배선간을 상하로 연결하는 콘택홀 및 비아홀의 종횡비(Aspect Ratio) 역시 급속히 증가되며, 이러한 종횡비가 큰 콘택홀 및 비아홀 내에 플러그를 매립시키는 과정에서 여러가지 문제점이 발생한다.As the degree of integration of semiconductor devices increases, aspect ratios of contact holes and via holes connecting the wirings up and down also increase rapidly. do.

도 1a 내지 도 1d는 종래기술에 따른 반도체 소자의 제조 방법을 도시한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, 기판(10) 상에 도전패턴(11)을 형성한다. 도전패턴(11)은 비트라인이거나 금속 패턴일 수 있다.Referring to FIG. 1A, the conductive pattern 11 is formed on the substrate 10. The conductive pattern 11 may be a bit line or a metal pattern.

이어서, 도 1b에 도시된 바와 같이, 도전패턴(11)이 형성된 기판(10)의 전면에 절연막(12)을 형성한다. 이어서, 도 1c에 도시된 바와 같이, 절연막(12)을 선택적으로 식각하여 도전패턴(11)의 소정의 부분이 노출되도록 콘택홀(C)을 형성한다.Subsequently, as shown in FIG. 1B, an insulating film 12 is formed on the entire surface of the substrate 10 on which the conductive pattern 11 is formed. Subsequently, as illustrated in FIG. 1C, the insulating layer 12 is selectively etched to form a contact hole C to expose a predetermined portion of the conductive pattern 11.

이어서, 도 1d에 도시된 바와 같이, 콘택홀(C)를 매립하도록 전도막을 증착한 후, CMP등의 평탄화 공정을 실시하여 콘택홀(C)을 통해 도전패턴(11)에 전기적으로 연결되는 플러그(13)를 형성한다, 이어서, 플러그(13) 상에 금속배선(14)을 형성한다.Subsequently, as illustrated in FIG. 1D, after the conductive film is deposited to fill the contact hole C, a plug is electrically connected to the conductive pattern 11 through the contact hole C by performing a planarization process such as CMP. (13) is formed, and then metal wiring 14 is formed on the plug 13.

상기와 같은 종래기술에 따른 반도체 소자의 제조 방법은, 절연막에 콘택홀을 형성하는 과정에서 식각잔류물이 발생하는데 콘택홀이 고종횡비를 가짐에 따라 콘택홀 내부에 남아있는 식각잔류물의 제거가 곤란하며, 도전패턴과 콘택플러그가 접하는 계면에서 접촉저항이 증가되는 문제점이 있다. In the method of manufacturing a semiconductor device according to the related art as described above, etching residues are generated in the process of forming contact holes in the insulating layer, and as the contact holes have a high aspect ratio, it is difficult to remove the etching residues remaining in the contact holes. In addition, there is a problem that the contact resistance is increased at the interface between the conductive pattern and the contact plug.                         

또한, 콘택플러그를 형성하기 위한 별도의 공정이 추가되므로 공정이 복잡해지고 제조비용이 증가되는 문제점이 있다.
In addition, since a separate process for forming the contact plug is added, the process becomes complicated and the manufacturing cost increases.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 콘택플러그 사용에 따른 접촉저항의 증가를 방지함과 동시에 공정을 단순화할 수 있는 반도체 소자 및 그의 제조 방법을 제공하는데 그 목적이 있다.
The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor device and a method of manufacturing the same, which can simplify the process while preventing an increase in contact resistance due to the use of a contact plug. .

상기한 목적을 달성하기 위해 본 발명은 제1도전패턴과 상기 제1도전패턴 상부에서 상기 제1도전패턴과 전기적으로 접속된 제2도전패턴을 포함하며, 상기 제1도전패턴은 상기 제2도전패턴과 콘택플러그 없이 직접 접속되도록 그 일부가 돌출된 형상으로 이루어진 반도체 소자를 제공한다.In order to achieve the above object, the present invention includes a first conductive pattern and a second conductive pattern electrically connected to the first conductive pattern on the first conductive pattern, wherein the first conductive pattern is the second conductive pattern. Provided is a semiconductor device having a portion protruding so as to be directly connected to a pattern without a contact plug.

상기 제1도전패턴과 제2도전패턴 사이에 층간절연막이 더 형성되어 있다.An interlayer insulating film is further formed between the first conductive pattern and the second conductive pattern.

또한, 본 발명은 기판 상에 그 상부에 돌출부를 갖는 제1도전패턴을 형성하는 단계; 상기 제1도전패턴이 형성된 기판의 전면에 층간절연막을 형성하는 단계; 상기 돌출부가 노출되는 타겟으로 상기 층간절연막을 평탄화하는 단계; 및 상기 돌출부 상에 금속배선을 형성하는 단계를 포함하는 반도체 소자의 제조 방법을 제공한다.
In addition, the present invention comprises the steps of forming a first conductive pattern having a protrusion on top of the substrate; Forming an interlayer insulating film on an entire surface of the substrate on which the first conductive pattern is formed; Planarizing the interlayer insulating film with a target to which the protrusion is exposed; And forming a metal wire on the protrusion.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2는 본 발명의 바람직한 실시예에 따른 반도체 소자를 나타낸 단면도이다.2 is a cross-sectional view illustrating a semiconductor device in accordance with a preferred embodiment of the present invention.

도 2를 참조하면, 기판(20) 상에 돌출부를 갖는 제1도전패턴(21)이 형성되어 있다. 제1도전패턴(21)을 포함한 기판(20) 상에 제1도전패턴(21)의 돌출부와 실질적으로 평탄화된 층간절연막(22)이 형성되어있다. 층간절연막(22) 상에는 제1도전패턴(21)의 돌출부와 직접 접속된 제2도전패턴이 형성되어 있다.Referring to FIG. 2, a first conductive pattern 21 having protrusions is formed on the substrate 20. An interlayer insulating film 22 is formed on the substrate 20 including the first conductive pattern 21 to substantially flatten the protrusion of the first conductive pattern 21. On the interlayer insulating film 22, a second conductive pattern directly connected to the protrusion of the first conductive pattern 21 is formed.

상술한 바와 같이, 본 발명에 따른 반도체 소자는 제1도전패턴과 제2도전패턴이 콘택플러그 없이 직접 연결되어 콘택플러그 형성공정을 생략할 수 있어 공정을 단순화 시킬 수 있으며, 콘택플러그 사용에 따른 콘택저항 증가를 방지하고 식각잔류물의 발생을 줄일 수 있다.As described above, in the semiconductor device according to the present invention, since the first conductive pattern and the second conductive pattern are directly connected without the contact plug, the process of forming the contact plug can be omitted, and the process can be simplified. It can prevent the increase of resistance and reduce the occurrence of etch residue.

도 3a 내지 도 3c는 본발명의 바람직한 실시예에 따른 반도체 소자의 제조 방법을 도시한 공정단면도이다.3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

도 3a를 참조하면, 기판(30) 상에 도전물질을 증착한 후, 도전물질을 선택적으로 식각하여 돌출부를 갖는 제1도전패턴(31)을 형성한다. 제1도전패턴(31)은 비트라인 또는 금속배선일 수 있다.Referring to FIG. 3A, after depositing a conductive material on the substrate 30, the conductive material is selectively etched to form a first conductive pattern 31 having protrusions. The first conductive pattern 31 may be a bit line or a metal wiring.

이어서, 도 3b에 도시된 바와 같이, 제1도전패턴(31)을 포함하는 기판(30)의 전면에 층간절연막(32)을 형성한 후, 층간절연막(32)을 제1도전패턴(31)의 돌출부 가 노출되는 타겟으로 CMP공정 또는 에치백공정을 실시하여 평탄화시킨다.Subsequently, as shown in FIG. 3B, after the interlayer insulating film 32 is formed on the entire surface of the substrate 30 including the first conductive pattern 31, the interlayer insulating film 32 is formed on the first conductive pattern 31. Flatten by performing CMP process or etch back process to the target exposed projection.

이어서, 도 3c에 도시된 바와 같이, 노출된 제1도전패턴(31)의 돌출부 상에 제2도전패턴(33)을 형성한다. 제2도전패턴(33)은 금속배선일 수 있다.Subsequently, as illustrated in FIG. 3C, a second conductive pattern 33 is formed on the exposed protrusion of the first conductive pattern 31. The second conductive pattern 33 may be a metal wiring.

전술한 바와 같이 이루어지는 본 발명은, 제1도전패턴과 제1도전패턴이 직접연결되므로, 제1도전패턴과 제2도전패턴을 전기적을 연결시키기 위한 콘택플러그 형성공정을 생략할 수 있어 공정수를 단순화 시킴과 동시에 종래기술에서 발생하던 콘택플러그 사용에 따른 콘택저항의 증가를 방지하고 식각잔류물의 발생을 줄일 수 있다.According to the present invention made as described above, since the first conductive pattern and the first conductive pattern are directly connected, the contact plug forming process for electrically connecting the first conductive pattern and the second conductive pattern can be omitted. At the same time, it is possible to prevent an increase in contact resistance due to the use of a contact plug that has occurred in the prior art and to reduce the occurrence of etch residue.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의해야 한다. 또한, 본 발명의 기술 분야의 통상의 지식을 가진자라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같은 본 발명은, 도전패턴 사이를 콘택플러그 없이 직접 연결하여 콘택플러그 사용에 따른 콘택저항이 증가되는 것을 방지하고, 식각잔류물의 발생을 줄임과 동시에 공정을 단순화시킬 수 있는 효과가 있다.The present invention as described above, there is an effect that can be directly connected between the conductive patterns without a contact plug to prevent the increase in contact resistance due to the use of the contact plug, and to simplify the process while reducing the generation of etching residues.

Claims (8)

제1도전패턴과 상기 제1도전패턴 상부에서 상기 제1도전패턴과 전기적으로 접속된 제2도전패턴을 포함하며,A first conductive pattern and a second conductive pattern electrically connected to the first conductive pattern on the first conductive pattern; 상기 제1도전패턴은 상기 제2도전패턴과 콘택플러그 없이 직접 접속되도록 그 일부가 돌출된 형상으로 이루어진 반도체 소자.And a portion of the first conductive pattern protruding from the second conductive pattern so as to be directly connected to the second conductive pattern without a contact plug. 제1항에 있어서,The method of claim 1, 상기 제1도전패턴과 제2도전패턴 사이에 층간절연막이 더 형성된 반도체 소자.A semiconductor device further comprising an interlayer insulating film formed between the first conductive pattern and the second conductive pattern. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제1도전패턴은 비트라인 패턴 또는 금속배선인 반도체 소자.The first conductive pattern is a bit line pattern or a metal wiring. 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 제2도전 패턴은 금속배선인 반도체 소자.The second conductive pattern is a semiconductor device. 기판 상에 그 상부에 돌출부를 갖는 제1도전패턴을 형성하는 단계;Forming a first conductive pattern having a protrusion on the substrate; 상기 제1도전패턴이 형성된 기판의 전면에 층간절연막을 형성하는 단계;Forming an interlayer insulating film on an entire surface of the substrate on which the first conductive pattern is formed; 상기 돌출부가 노출되는 타겟으로 상기 층간절연막을 평탄화하는 단계; 및Planarizing the interlayer insulating film with a target to which the protrusion is exposed; And 상기 돌출부 상에 금속배선을 형성하는 단계Forming a metal wire on the protrusion 를 포함하는 반도체 소자의 제조 방법.Method for manufacturing a semiconductor device comprising a. 제5항에 있어서,The method of claim 5, 상기 제1도전패턴은 비트라인 패턴 또는 금속배선인 반도체 소자의 제조 방법.The first conductive pattern is a bit line pattern or a metal wiring method of manufacturing a semiconductor device. 제5항에 있어서,The method of claim 5, 상기 제2도전 패턴은 금속배선인 반도체 소자의 제조 방법.The second conductive pattern is a metal wiring method of manufacturing a semiconductor device. 제5항에 있어서,The method of claim 5, 상기 평탄화하는 단계에서, CMP공정 또는 에치백공정을 실시하는 반도체 소자의 제조 방법.In the planarizing step, a semiconductor device manufacturing method performing a CMP process or an etch back process.
KR1020040086854A 2004-10-28 2004-10-28 Semiconductor device and method for fabricating the same KR20060037799A (en)

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