KR20070005070A - Method of forming a metal line in semiconductor device - Google Patents

Method of forming a metal line in semiconductor device Download PDF

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KR20070005070A
KR20070005070A KR1020050060170A KR20050060170A KR20070005070A KR 20070005070 A KR20070005070 A KR 20070005070A KR 1020050060170 A KR1020050060170 A KR 1020050060170A KR 20050060170 A KR20050060170 A KR 20050060170A KR 20070005070 A KR20070005070 A KR 20070005070A
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South Korea
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forming
etch stop
film
contact hole
layer
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KR1020050060170A
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Korean (ko)
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명성환
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주식회사 하이닉스반도체
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Publication of KR20070005070A publication Critical patent/KR20070005070A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal

Abstract

A method for forming a metal line of a semiconductor device is provided to prevent the damage of a metal film and to restrain a contact hole from being excessively etched by using an etch stop buffer layer. A lower metal line is formed on a semiconductor substrate(10). An etch stop buffer layer(28) is formed on the lower metal line alone. An etch stop layer and an interlayer dielectric are sequentially formed on the resultant structure. A contact hole for exposing the etch stop buffer layer to the outside is formed on the resultant structure by patterning selectively the interlayer dielectric and the etch stop layer. An upper metal line for contacting the lower metal line fills the contact hole.

Description

반도체 소자의 금속배선 형성방법{Method of forming a metal line in semiconductor device}Method of forming a metal line in semiconductor device

도 1 내지 도 5는 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이다. 1 to 5 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Explanation of symbols for main parts of drawings *

10: 반도체 기판 12, 26, 36: 금속막10: semiconductor substrate 12, 26, 36: metal film

28: 식각정지 버퍼막 24, 34: 장벽금속막28: etch stop buffer film 24, 34: barrier metal film

본 발명은 반도체 소자의 제조방법에 관한 것으로, 더욱 상세하게는 반도체 소자의 금속배선 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.

반도체 소자의 제조공정시 다층배선의 형성이 요구되고 있는 데, 반도체 소자의 고집적화 및 고밀도화됨에 따라 다층배선 형성에 어려움이 있다.Formation of multi-layered wiring is required in the manufacturing process of the semiconductor device. As the integration and density of semiconductor devices are increased, it is difficult to form the multi-layered wiring.

즉, 하부금속막 상부에 형성되는 상부금속막이 정의될 콘택홀의 형성 공정시, 식각시 반응물질 및 과도 식각으로 인해 하부금속막의 손상이 용이하게 되고, 상부 금속막의 형성영역 즉, 콘택홀에 대한 정의도 어렵게 되는 문제점이 있다. That is, during the process of forming the contact hole in which the upper metal film formed on the lower metal film is to be defined, the lower metal film is easily damaged due to the reaction material and the excessive etching during the etching, and the formation region of the upper metal film, that is, the definition of the contact hole. There is also a problem that becomes difficult.

따라서 하부 금속막 상부에 형성되는 상부 금속막의 형성 공정시 하부 금속막의 손상을 방지하고, 상부 금속막의 형성영역 정의가 용이해지는 기술이 요구되고 있다. Accordingly, there is a demand for a technique of preventing damage to the lower metal film and easily defining the formation region of the upper metal film during the formation of the upper metal film formed on the lower metal film.

상술한 목적을 달성하기 위한 본 발명의 사상은 하부 금속막 상부에 형성되는 상부 금속막의 형성 공정시 하부 금속막의 손상을 방지하고, 상부 금속막의 형성영역 정의가 용이해지도록 하는 반도체 소자의 금속배선 형성방법을 제공함에 있다. The idea of the present invention for achieving the above object is to prevent the damage of the lower metal film during the formation process of the upper metal film formed on the upper metal film, and to form the metal wiring of the semiconductor device to facilitate the definition of the formation region of the upper metal film In providing a method.

상술한 목적을 달성하기 위한 본 발명의 사상은 하부금속배선이 형성되는 반도체 기판이 제공되는 단계, 상기 하부금속배선상에만 식각정지 버퍼막을 형성하는 단계, 상기 결과물 상에 식각정지막 및 층간절연막을 순차적으로 형성한 후 상기 식각정지버퍼막이 노출되도록 상기 층간 절연막 및 식각 정지막을 패터닝하여 콘택홀을 형성하는 단계 및 상기 콘택홀에 매립되도록 도전막을 형성하여 상기 하부금속배선과 접촉되는 상부금속배선을 형성하는 단계를 포함한다.According to an aspect of the present invention, a semiconductor substrate in which a lower metal interconnection is formed is provided, forming an etch stop buffer layer only on the lower metal interconnection, and forming an etch stop layer and an interlayer dielectric layer on the resultant. After forming sequentially, forming a contact hole by patterning the interlayer insulating film and the etch stop layer to expose the etch stop buffer layer, and forming a conductive film to be buried in the contact hole to form an upper metal wiring in contact with the lower metal wiring. It includes a step.

상기 하부금속배선은 콘택플러그 또는 금속배선으로 형성된다.The lower metal wire is formed of a contact plug or a metal wire.

상기 식각정지 버퍼막은 TiN막으로 형성된다.The etch stop buffer layer is formed of a TiN layer.

상기 TiN막은 450~ 550Å의 두께로 형성되되, 1.8~ 2.2E-8의 압력, 24~ 26℃의 온도, 5900~ 6100W의 전력을 공정조건으로 가지는 스퍼터링 공정을 통해 형성된다.The TiN film is formed to a thickness of 450 ~ 550Å, a sputtering process having a pressure of 1.8 ~ 2.2E-8, temperature of 24 ~ 26 ℃, power of 5900 ~ 6100W as a process condition.

상기 콘택홀 형성 후, 상기 콘택홀의 경계를 따라 장벽 금속막을 형성하는 단계를 더 포함한다.After forming the contact hole, forming a barrier metal film along a boundary of the contact hole.

이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.

도 1 내지 도 5는 본 발명에 따른 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이다. 1 to 5 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

도 1을 참조하면, 하부금속배선(12)이 형성된 반도체 기판(10)상에 제1 식각 정지막(14), 제1 층간 절연막(16), 제2 식각 정지막(18), 제2 층간 절연막(20) 및 하드마스크용 절연막(22)을 순차적으로 형성한다. Referring to FIG. 1, a first etch stop layer 14, a first interlayer insulating layer 16, a second etch stop layer 18, and a second interlayer may be formed on a semiconductor substrate 10 on which a lower metal interconnection 12 is formed. The insulating film 20 and the hard mask insulating film 22 are formed sequentially.

상기 하드마스크용 절연막(22)의 소정영역에 제1 콘택홀을 정의하는 포토레지스트 패턴(미도시)을 형성하고, 이를 식각 마스크로 제1 식각 정지막(14)까지 식각공정을 수행하여 제1 콘택홀을 정의한다. A photoresist pattern (not shown) defining a first contact hole is formed in a predetermined region of the hard mask insulating layer 22, and an etching process is performed to the first etch stop layer 14 using an etching mask, thereby forming a first resist hole. Define a contact hole.

이어서, 상기 제1 콘택홀을 정의하는 포토레지스트 패턴을 제거하고, 상기 콘택홀이 형성된 결과물의 상기 하드마스크용 절연막(22)의 또 다른 소정영역에 트렌치를 정의하는 포토레지스트 패턴(미도시)을 형성하고, 이를 식각 마스크로 제2 식각정지막(18)까지 식각공정을 수행하여 트렌치를 정의한다. Subsequently, the photoresist pattern defining the first contact hole is removed, and a photoresist pattern (not shown) defining a trench is formed in another predetermined region of the hard mask insulating film 22 of the resultant product in which the contact hole is formed. The trench may be formed by performing an etching process up to the second etch stop layer 18 using an etch mask.

상기와 같은 듀얼 다마신 공정 즉, 비아퍼스트 듀얼다마신 공정을 통해 제1 콘택홀 및 트렌치(C & T)를 형성한다. The first contact hole and the trench C & T are formed through the dual damascene process, that is, the via first dual damascene process.

도 2를 참조하면, 상기 콘택홀 및 트렌치(C & T)가 형성된 결과물의 경계를 따라 제1 장벽 금속막(24)을 형성한다. Referring to FIG. 2, a first barrier metal layer 24 is formed along a boundary of a resultant product in which the contact hole and trenches C & T are formed.

상기 제1 장벽 금속막(24)은 180~ 220Å 정도 두께의 Ti막과 45~ 55Å 정도 두께의 TiN막으로 적층 형성된다. The first barrier metal film 24 is formed by laminating a Ti film having a thickness of about 180 to 220 GPa and a TiN film having a thickness of about 45 to 55 GPa.

이어서, 상기 제1 장벽 금속막(24)이 형성된 결과물 전면에 금속막을 형성하여, 상기 제1 콘택홀 및 트렌치(C & T)가 완전히 매립되도록 한다. Subsequently, a metal film is formed on the entire surface of the resultant product on which the first barrier metal film 24 is formed so that the first contact hole and the trench C & T are completely filled.

상기 금속막(26)은 구리막 또는 텅스텐막을 3800~ 4200Å 정도의 두께로 형성하고, 이 텅스텐막은 350~ 400℃ 정도의 온도에서 CVD공정을 통해 형성한다. The metal film 26 is formed of a copper film or a tungsten film with a thickness of about 3800 ~ 4200Å, the tungsten film is formed by a CVD process at a temperature of about 350 ~ 400 ℃.

이어서, 상기 금속막(26)이 형성된 결과물 상에 제1 장벽 금속막(24)이 노출 될 때까지 CMP 공정과 같은 평탄화 공정을 수행하여, 상기 하부금속배선(12)과 접촉되는 제1 콘택플러그와 상부금속배선(26)의 형성을 완료한다. Subsequently, a planarization process such as a CMP process is performed until the first barrier metal layer 24 is exposed on the resultant product on which the metal layer 26 is formed, thereby contacting the first contact plug that is in contact with the lower metal wiring 12. And the formation of the upper metal wiring 26 is completed.

도 3을 참조하면, 상기 결과물 전면에 TiN막을 형성하고, 상기 상부금속배선(26)상부에만 형성되도록 패터닝하여 식각정지 버퍼막인 TiN막(28)을 형성한다. Referring to FIG. 3, a TiN film is formed on the entire surface of the resultant, and patterned to be formed only on the upper metal wiring 26 to form a TiN film 28 as an etch stop buffer film.

상기 식각 정지 버퍼막인 TiN막(28)은 상기 상부금속배선과 접촉되는 콘택홀 형성 공정시 손상을 방지하는 식각 정지 버퍼막으로써, 450~ 550Å 정도의 두께로 형성되되, 1.8~ 2.2E-8 정도의 압력, 24~ 26℃ 정도의 온도, 5900~ 6100W 정도의 전력을 공정조건으로 가지는 스퍼터링 공정을 통해 형성한다. The etch stop buffer layer TiN layer 28 is an etch stop buffer layer that prevents damage during the contact hole forming process in contact with the upper metal wiring, and is formed to have a thickness of about 450 to 550 Å, 1.8 to 2.2E-8. It is formed through the sputtering process that has the pressure of about 24 ~ 26 ℃ and the power of about 5900 ~ 6100W as process conditions

도 4를 참조하면, 상기 식각 정지 버퍼막(28)이 형성된 결과물 상에 제3 식각 정지막(30) 및 제3 층간절연막(32)을 순차적으로 형성한다. Referring to FIG. 4, a third etch stop layer 30 and a third interlayer insulating layer 32 are sequentially formed on the resultant product on which the etch stop buffer layer 28 is formed.

상기 제3 식각 정지막(30)은 후속 제2 콘택홀 식각 공정시 식각이 정지되도록 형성되는 질화막으로써, 이 질화막(30)은 380~ 420℃ 정도의 온도에서 480~ 520Å 정도의 두께로 PECVD방법을 통해 형성한다.The third etch stop layer 30 is a nitride film formed so that the etching is stopped in the subsequent second contact hole etching process, the nitride film 30 is a PECVD method with a thickness of about 480 ~ 520 에서 at a temperature of about 380 ~ 420 ℃ Form through.

상기 제3 층간 절연막(32)은 TEOS막으로 형성하되, 상기 TEOS막은 380~ 420℃ 정도의 온도에서 2900~ 3100Å 정도의 두께로 PECVD방법을 통해 형성한다.The third interlayer insulating film 32 is formed of a TEOS film, and the TEOS film is formed by a PECVD method at a thickness of about 2900 to 3100 kPa at a temperature of about 380 to 420 ° C.

이어서, 상기 제3 층간 절연막(32)의 소정 영역에 콘택홀을 형성하기 위한 포토레지스트 패턴(미도시)을 형성하고, 이를 식각 마스크로 제3 식각 정지막(30)까지 식각공정을 수행하여 콘택홀(C)을 정의한다. Subsequently, a photoresist pattern (not shown) for forming a contact hole is formed in a predetermined region of the third interlayer insulating layer 32, and the etching process is performed to the third etch stop layer 30 using an etching mask. Define the hole (C).

상기 콘택홀(C)은 상부금속배선(26)과 접촉하기 위해 형성된다. The contact hole C is formed to contact the upper metal wiring 26.

상기 콘택홀(C) 형성 공정시 하부의 식각 정지 버퍼막인 TiN막으로 인해, 하 부에 위치한 상부금속배선(26)의 손상을 방지하는 버퍼막의 역할을 수행하면서 동시에 콘택홀 형성공정에 대한 식각 정지막의 역할을 수행하게 된다. Due to the TiN film, which is the etch stop buffer film at the bottom of the contact hole (C) forming process, serves as a buffer film to prevent damage to the upper metal wiring 26 located at the bottom, and at the same time to etch the contact hole forming process It will act as a stop membrane.

또한, 상기 콘택홀(C) 형성 공정시 자연산화막이나 식각부산물을 제거하기 위한 식각공정을 수행하는 데, 상기 콘택홀의 저면에 식각정지 버퍼막인 TiN막(28)이 남겨져 있기 때문에 상기 자연산화막이나 식각부산물을 제거하기 위한 식각공정은 수행하지 않아도 된다. {왜요? 이유가 없네요?}In addition, during the contact hole (C) forming process, an etching process for removing a natural oxide film or an etching by-product is performed. Since the TiN film 28, which is an etch stop buffer film, is left on the bottom of the contact hole, The etching process to remove the etch by-products does not have to be performed. {why? No reason?}

도 5를 참조하면, 상기 형성된 콘택홀(C)이 형성된 결과물의 경계를 따라 제2 장벽 금속막(34)을 형성한다. Referring to FIG. 5, a second barrier metal layer 34 is formed along a boundary of the resultant contact hole C formed therein.

상기 제2 장벽 금속막(34)은 80~ 120Å 정도 두께의 Ti막과 450~ 550Å 정도 두께의 TiN막으로 적층 형성된다. The second barrier metal film 34 is formed by laminating a Ti film having a thickness of about 80 to 120 GPa and a TiN film having a thickness of about 450 to 550 GPa.

이어서, 상기 제2 장벽 금속막(34)이 형성된 결과물 전면에 금속막을 형성하여, 상기 제2 콘택홀(C)이 완전히 매립되도록 한다. Subsequently, a metal film is formed on the entire surface of the resultant product on which the second barrier metal film 34 is formed, so that the second contact hole C is completely filled.

상기 금속막(36)은 구리막 또는 텅스텐막을 3800~ 4200Å 정도의 두께로 형성하고, 이 텅스텐막은 350~ 400℃ 정도의 온도에서 CVD공정을 통해 형성한다. The metal film 36 is formed of a copper film or a tungsten film with a thickness of about 3800-4200 kPa, and the tungsten film is formed by a CVD process at a temperature of about 350-400 ° C.

이어서, 상기 금속막(26)이 형성된 결과물 상에 제2 장벽 금속막(34)이 노출될 때까지 CMP 공정과 같은 평탄화 공정을 수행하여, 상기 상부금속배선(26)과 접촉되는 제2 콘택플러그(36)의 형성을 완료한다. Next, a second contact plug contacting the upper metal wiring 26 by performing a planarization process such as a CMP process until the second barrier metal film 34 is exposed on the resultant product on which the metal film 26 is formed. The formation of 36 is completed.

본 발명에 의하면, 하부금속막 상부에 식각정지 버퍼막을 형성한 후 상부 금속막이 정의될 콘택홀을 형성함으로써, 하부에 위치한 금속막의 손상을 방지하게 되면서 동시에 상부금속막이 정의될 콘택홀 형성시 과식각을 방지하게 되는 효과가 있다. According to the present invention, by forming an etch stop buffer layer on the lower metal layer and forming a contact hole in which the upper metal layer is to be defined, over-etching is performed while forming a contact hole in which the upper metal layer is defined while preventing damage to the lower metal layer. There is an effect to prevent.

이상에서 살펴본 바와 같이 본 발명에 의하면, 하부 금속막 상부에 식각정지 버퍼막을 형성한 후 상부 금속막이 정의될 콘택홀을 형성함으로써, 하부에 위치한 금속막의 손상을 방지하게 되면서 동시에 상부금속막이 정의될 콘택홀 형성시 과식각이 방지되어, 과식각이 진행되는 공정시간을 단축할 수 있는 효과가 있다. As described above, according to the present invention, by forming an etch stop buffer layer on the lower metal layer and forming a contact hole in which the upper metal layer is to be defined, the contact of the upper metal layer is defined while preventing the damage of the metal layer located at the bottom. Since over-etching is prevented when the hole is formed, there is an effect that the process time for over-etching can be shortened.

본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.

Claims (5)

하부금속배선이 형성되는 반도체 기판이 제공되는 단계;Providing a semiconductor substrate having a lower metal wiring formed thereon; 상기 하부금속배선상에만 식각정지 버퍼막을 형성하는 단계;Forming an etch stop buffer layer only on the lower metal interconnection; 상기 결과물 상에 식각정지막 및 층간절연막을 순차적으로 형성한 후 상기 식각정지버퍼막이 노출되도록 상기 층간 절연막 및 식각 정지막을 패터닝하여 콘택홀을 형성하는 단계; 및Forming a contact hole by sequentially forming an etch stop layer and an interlayer insulating layer on the resultant, and then patterning the interlayer insulating layer and the etch stop layer to expose the etch stop buffer layer; And 상기 콘택홀에 매립되도록 도전막을 형성하여 상기 하부금속배선과 접촉되는 상부금속배선을 형성하는 단계를 포함하는 반도체 소자의 금속배선 형성방법.And forming an upper metal wiring in contact with the lower metal wiring by forming a conductive film to be filled in the contact hole. 제1 항에 있어서, 상기 하부금속배선은 The method of claim 1, wherein the lower metal wiring 콘택플러그 또는 금속배선으로 형성되는 반도체 소자의 금속배선 형성방법. A metal wiring forming method of a semiconductor device formed by contact plugs or metal wiring. 제1 항에 있어서, 상기 식각정지 버퍼막은  The method of claim 1, wherein the etch stop buffer layer TiN막으로 형성되는 반도체 소자의 금속배선 형성방법. A metal wiring forming method of a semiconductor device formed of a TiN film. 제2 항에 있어서, 상기 TiN막은  The method of claim 2, wherein the TiN film 450~ 550Å의 두께로 형성되되, 1.8~ 2.2E-8의 압력, 24~ 26℃의 온도, 5900~ 6100W의 전력을 공정조건으로 가지는 스퍼터링 공정을 통해 형성되는 반도체 소자의 금속배선 형성방법. Forming a thickness of 450 ~ 550Å, metal wiring forming method of a semiconductor device formed by a sputtering process having a pressure of 1.8 ~ 2.2E-8, temperature of 24 ~ 26 ℃, power of 5900 ~ 6100W as a process condition. 제1 항에 있어서, 상기 콘택홀 형성 후, The method of claim 1, wherein after forming the contact hole, 상기 콘택홀의 경계를 따라 장벽 금속막을 형성하는 단계를 더 포함하는 반도체 소자의 금속배선 형성방법. And forming a barrier metal film along a boundary of the contact hole.
KR1020050060170A 2005-07-05 2005-07-05 Method of forming a metal line in semiconductor device KR20070005070A (en)

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