KR20060030850A - 저 지터 듀얼-루프 ｎ분의 1 합성기를 위한 방법 및 장치 - Google Patents

저 지터 듀얼-루프 ｎ분의 1 합성기를 위한 방법 및 장치 Download PDF

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Publication number
KR20060030850A
KR20060030850A KR1020057020780A KR20057020780A KR20060030850A KR 20060030850 A KR20060030850 A KR 20060030850A KR 1020057020780 A KR1020057020780 A KR 1020057020780A KR 20057020780 A KR20057020780 A KR 20057020780A KR 20060030850 A KR20060030850 A KR 20060030850A
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KR
South Korea
Prior art keywords
circuit
control
loop
control value
loop circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020057020780A
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English (en)
Korean (ko)
Inventor
액셀 톰슨
윤텡 후앙
제럴 피 헤인
Original Assignee
실리콘 래버래토리즈 , 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/675,529 external-priority patent/US20050068118A1/en
Priority claimed from US10/675,543 external-priority patent/US7187241B2/en
Application filed by 실리콘 래버래토리즈 , 인코포레이티드 filed Critical 실리콘 래버래토리즈 , 인코포레이티드
Publication of KR20060030850A publication Critical patent/KR20060030850A/ko
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H03L1/022—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature
    • H03L1/026—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature by using a memory for digitally storing correction values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H03L7/235—Nested phase locked loops
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
KR1020057020780A 2003-05-02 2004-05-03 저 지터 듀얼-루프 ｎ분의 1 합성기를 위한 방법 및 장치 Withdrawn KR20060030850A (ko)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US46781303P 2003-05-02 2003-05-02
US60/467,813 2003-05-02
US10/675,529 2003-09-30
US10/675,529 US20050068118A1 (en) 2003-09-30 2003-09-30 Reconfigurable terminal
US10/675,543 US7187241B2 (en) 2003-05-02 2003-09-30 Calibration of oscillator devices
US10/675,543 2003-09-30

Publications (1)

Publication Number Publication Date
KR20060030850A true KR20060030850A (ko) 2006-04-11

Family

ID=33437074

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020057020780A Withdrawn KR20060030850A (ko) 2003-05-02 2004-05-03 저 지터 듀얼-루프 ｎ분의 1 합성기를 위한 방법 및 장치

Country Status (4)

Country Link
EP (1) EP1623503B1 (enExample)
JP (1) JP4691024B2 (enExample)
KR (1) KR20060030850A (enExample)
WO (1) WO2004100380A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100847799B1 (ko) * 2006-10-30 2008-07-23 지씨티 세미컨덕터 인코포레이티드 위상 동기 루프 및 그 온도 보상 방법

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7281176B2 (en) 2004-10-29 2007-10-09 Silicon Laboratories Inc. Determining signal quality and selecting a slice level via a forbidden zone
US7577224B2 (en) 2004-12-28 2009-08-18 Silicon Laboratories Inc. Reducing phase offsets in a phase detector
US7609798B2 (en) 2004-12-29 2009-10-27 Silicon Laboratories Inc. Calibrating a phase detector and analog-to-digital converter offset and gain
US7512203B2 (en) 2005-03-30 2009-03-31 Silicon Laboratories Inc. Data cleaning with an asynchronous reference clock
US20060267701A1 (en) * 2005-05-27 2006-11-30 Robert Eilers Method and system for dynamically calculating values for tuning of voltage-controlled crystal oscillators
US7259628B2 (en) 2005-06-30 2007-08-21 Silicon Laboratories Inc. Signal dependent biasing scheme for an amplifier
US8378751B2 (en) * 2009-02-13 2013-02-19 Qualcomm Incorporated Frequency synthesizer with multiple tuning loops
JP5381268B2 (ja) * 2009-04-15 2014-01-08 パナソニック株式会社 受信装置と、これを用いた受信モジュール及び電子機器
JP2015128220A (ja) 2013-12-27 2015-07-09 セイコーエプソン株式会社 発振回路、発振器、電子機器、移動体及び発振器の周波数調整方法
EP3076552B1 (en) * 2015-03-30 2019-01-30 Nxp B.V. Digital synchronizer
EP3076553B1 (en) 2015-03-30 2021-04-14 Nxp B.V. Clock synchronizer
JP6484354B2 (ja) * 2015-06-16 2019-03-13 テレフオンアクチーボラゲット エルエム エリクソン（パブル） 電子回路、位相ロックループ、送受信機回路、無線局、及び周波数分割の方法
US10873335B2 (en) 2019-05-02 2020-12-22 Apple Inc. Divider control and reset for phase-locked loops
CN110289857B (zh) * 2019-05-20 2022-11-29 昇显微电子(苏州)有限公司 一种时钟生成电路
CN113391539B (zh) * 2021-06-16 2022-08-26 北京康斯特仪表科技股份有限公司 一种rtc时钟校准方法及工业现场校验装置
US11764795B2 (en) 2021-11-29 2023-09-19 Qualcomm Incorporated Fractional phase locked loop (PLL) with digital control driven by clock with higher frequency than PLL feedback signal
US20250247102A1 (en) * 2024-01-29 2025-07-31 Apple Inc. Phase interpolator circuitry with post-distortion linearization

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU6339594A (en) * 1993-06-09 1994-12-15 Alcatel N.V. Synchronized clock
EP0630129A2 (de) * 1993-06-09 1994-12-21 Alcatel SEL Aktiengesellschaft Verfahren zur Erzeugung eines synchronisierten Taktes mit einer Schaltungsanordnung für einen regelbaren Oszillator
US5604468A (en) * 1996-04-22 1997-02-18 Motorola, Inc. Frequency synthesizer with temperature compensation and frequency multiplication and method of providing the same
US6404246B1 (en) * 2000-12-20 2002-06-11 Lexa Media, Inc. Precision clock synthesizer using RC oscillator and calibration circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100847799B1 (ko) * 2006-10-30 2008-07-23 지씨티 세미컨덕터 인코포레이티드 위상 동기 루프 및 그 온도 보상 방법

Also Published As

Publication number Publication date
JP4691024B2 (ja) 2011-06-01
WO2004100380A1 (en) 2004-11-18
EP1623503A1 (en) 2006-02-08
JP2006526946A (ja) 2006-11-24
EP1623503B1 (en) 2012-03-14

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PA0105 International application

Patent event date: 20051101

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid