KR20060011537A - Method for isolation in semiconductor device - Google Patents

Method for isolation in semiconductor device Download PDF

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KR20060011537A
KR20060011537A KR1020040060424A KR20040060424A KR20060011537A KR 20060011537 A KR20060011537 A KR 20060011537A KR 1020040060424 A KR1020040060424 A KR 1020040060424A KR 20040060424 A KR20040060424 A KR 20040060424A KR 20060011537 A KR20060011537 A KR 20060011537A
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South Korea
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pad
film
nitride film
trench
forming
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KR1020040060424A
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Korean (ko)
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서원선
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주식회사 하이닉스반도체
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Priority to KR1020040060424A priority Critical patent/KR20060011537A/en
Publication of KR20060011537A publication Critical patent/KR20060011537A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Abstract

본 발명은 패드질화막의 스트립공정시에 라이너질화막 손실에 의해 초래되는 모우트의 발생 및 확장을 방지할 수 있는 반도체소자의 소자분리 방법을 제공하기 위한 것으로, 본 발명은 반도체 기판 상부에 패드산화막, 희생패드막 및 패드질화막의 순서로 적층된 패드패턴을 형성하는 단계, 상기 패드질화막을 하드마스크로 상기 반도체 기판을 식각하여 트렌치를 형성하는 단계, 상기 트렌치 표면 상에 측벽산화막을 형성하는 단계, 상기 측벽산화막을 포함한 전면에 라이너질화막을 형성하는 단계, 상기 라이너질화막 상에 상기 트렌치를 갭필하는 갭필절연막을 형성하는 단계, 상기 패드질화막 표면이 드러날 때까지 상기 갭필절연막을 평탄화시키는 단계, 상기 패드질화막을 스트립하는 단계, 및 상기 희생패드막과 상기 패드산화막을 차례로 스트립하는 단계를 포함하고, 이와 같이 본 발명은 패드질화막과 패드산화막 사이에 희생패드막을 도입하여 패드질화막 스트립공정시 침투 경로를 길게 하므로써 라이너질화막의 과도한 손실을 억제한다.
The present invention is to provide a device isolation method of a semiconductor device that can prevent the generation and expansion of the moot caused by the loss of the liner nitride film during the stripping process of the pad nitride film, the present invention provides a pad oxide film, Forming a stacked pad pattern in the order of a sacrificial pad film and a pad nitride film, forming a trench by etching the semiconductor substrate with the pad nitride film as a hard mask, and forming a sidewall oxide film on the trench surface; Forming a liner nitride film on the entire surface including a sidewall oxide film, forming a gap fill insulating film gap gap filling the trench on the liner nitride film, and planarizing the gap fill insulating film until the pad nitride film surface is exposed; Stripping, and sequentially stripping the sacrificial pad film and the pad oxide film. Comprising the step of, and thus the present invention inhibit the undue loss of the nitride liner By holding the penetration pad nitride strip process route by introducing sacrificial pad film between the pad nitride layer and the pad oxide film.

소자분리, 모우트, 트렌치, 라이너질화막, 패드폴리실리콘막, 스트립Device Separation, Mout, Trench, Liner Nitride, Pad Polysilicon, Strip

Description

반도체소자의 소자분리 방법{METHOD FOR ISOLATION IN SEMICONDUCTOR DEVICE} Device Separation Method for Semiconductor Devices {METHOD FOR ISOLATION IN SEMICONDUCTOR DEVICE}             

도 1a 내지 도 1e는 종래기술에 따른 반도체소자의 소자분리 방법을 도시한 공정 단면도,1A to 1E are cross-sectional views illustrating a device isolation method of a semiconductor device according to the prior art;

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체소자의 소자분리 방법을 도시한 공정 단면도.
2A to 2G are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21 : 반도체 기판 22 ; 패드산화막21: semiconductor substrate 22; Pad oxide film

23 : 패드폴리실리콘막 24 : 패드질화막23: pad polysilicon film 24: pad nitride film

25 : 트렌치 26 : 측벽산화막25 trench 26 sidewall oxide film

27, 27a : 라이너질화막 28 : 갭필절연막
27, 27a: liner nitride film 28: gap fill insulating film

본 발명은 반도체 제조 기술에 관한 것으로, 특히 반도체소자의 소자분리(Isolation; ISO) 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to an isolation method (ISO) of a semiconductor device.

최근 소자의 개발 공정에 있어서 가장 많은 문제점으로 지적되는 사항이 캐패시터의 리프레시 타임(Refresh time)을 개선하는 공정이다. DRAM과 같은 메모리의 경우 주기적인 리프레시는 소자의 제조공정에서 대단히 중요한 역할을 하고 있으며, 이러한 사항은 소자 개발에서 양산으로 이관되는 시점에 있어서 매우 중요한 역할을 하고 있다. 실제로 리프레시 타임의 확보를 양산의 성패를 좌우하는 중요한 관건이 된다.Recently, the most problematic point in the device development process is to improve the refresh time of the capacitor. In the case of memories such as DRAMs, periodic refreshes play a very important role in the device manufacturing process, which plays a very important role in the transition from device development to mass production. In fact, securing refresh time is an important factor in determining the success of mass production.

이러한 리프레시 타임 확보를 위하여 소자분리(Isolation; 이하 'ISO'라고 약칭함) 공정에서부터 많은 공정 개발 및 공정 물질 연구가 이루어져 왔는데 그 중에서 최근에 많은 연구가 진행되고 있으며 또한 차세대 공정에 적용되고 있는 물질이 바로 라이너질화막(Liner nitride)이다.In order to secure such a refresh time, many process developments and process materials researches have been conducted from the isolation process (hereinafter abbreviated as 'ISO'). It is a liner nitride film.

도 1a 내지 도 1e는 종래기술에 따른 반도체소자의 소자분리 방법을 도시한 공정 단면도이다.1A to 1E are cross-sectional views illustrating a device isolation method of a semiconductor device according to the prior art.

도 1a에 도시된 바와 같이, 반도체 기판(11) 상부에 패드산화막(12)과 패드질화막(13)을 적층한 후, 소자분리마스크(도시 생략)를 식각배리어로 패드질화막(13)과 패드산화막(12)을 식각하여 트렌치가 형성될 반도체 기판(11) 표면을 노출시킨다.As shown in FIG. 1A, after the pad oxide film 12 and the pad nitride film 13 are stacked on the semiconductor substrate 11, the pad nitride film 13 and the pad oxide film are etched with an element isolation mask (not shown). The 12 is etched to expose the surface of the semiconductor substrate 11 on which the trench is to be formed.

이어서, 미도시된 소자분리마스크를 제거하고, 계속해서 패드질화막(13)을 하드마스크로 이용하여 노출된 반도체 기판(11)을 식각하여 소자분리영역이 형성될 트렌치(14)를 형성한다.Subsequently, the device isolation mask (not shown) is removed, and the exposed semiconductor substrate 11 is etched using the pad nitride layer 13 as a hard mask to form the trench 14 in which the device isolation region is to be formed.

도 1b에 도시된 바와 같이, 트렌치(14) 형성시 발생된 식각손상을 제거해주기 위해 측벽산화 공정을 진행하여 트렌치(14)의 바닥 및 측벽에 측벽산화막(15)을 형성한다.As shown in FIG. 1B, the sidewall oxidation process is performed to remove the etch damage generated when the trench 14 is formed to form the sidewall oxide layer 15 on the bottom and sidewalls of the trench 14.

이어서, 측벽산화막(15)이 형성된 결과물의 전면에 라이너질화막(16)을 형성한다.Subsequently, the liner nitride film 16 is formed on the entire surface of the resultant sidewall oxide film 15 formed thereon.

도 1c에 도시된 바와 같이, 라이너질화막(16) 상부에 트렌치(15)를 갭필할때까지 갭필절연막(17)을 증착한다. 이때, 갭필절연막(17)은 주로 고밀도플라즈마(High Density Plasma; HDP) 방식으로 증착한 산화막이다.As shown in FIG. 1C, the gap fill insulating layer 17 is deposited on the liner nitride layer 16 until the trench 15 is gap filled. At this time, the gap fill insulating film 17 is mainly an oxide film deposited by a high density plasma (HDP) method.

다음으로, 패드질화막(13)을 연마정지막으로 이용한 CMP(Chemical Mechanical Polishing) 공정을 진행하여 갭필절연막(17)을 평탄화시킨다. 이때, 라이너질화막(16) 중에서 패드질화막(13) 상부에 형성된 부분이 연마된다.Next, a CMP (Chemical Mechanical Polishing) process using the pad nitride film 13 as a polishing stop film is performed to planarize the gap fill insulating film 17. At this time, the portion formed on the pad nitride film 13 in the liner nitride film 16 is polished.

도 1d에 도시된 바와 같이, 패드질화막(13)의 스트립(Strip) 공정을 진행한다. 이때, 패드질화막(13)은 인산(H3PO4) 용액을 이용하여 스트립하는데, 갭필절연막(17)과 패드질화막(13) 사이의 경계부분에 형성된 라이너질화막(16)이 인산용액에 의해 손실되어 꺼짐('X') 현상이 발생된다.As shown in FIG. 1D, a strip process of the pad nitride layer 13 is performed. At this time, the pad nitride film 13 is stripped by using a phosphoric acid (H 3 PO 4 ) solution, and the liner nitride film 16 formed at the boundary between the gap fill insulating film 17 and the pad nitride film 13 is lost by the phosphoric acid solution. Off ('X') occurs.

도 1e에 도시된 바와 같이, 패드산화막(12)을 제거한다. 이때, 패드산화막(12)은 불산(HF) 용액을 이용하여 제거하며, 갭필절연막(17)도 일부가 제거되어 활성영역과의 단차가 감소한다. As shown in FIG. 1E, the pad oxide film 12 is removed. In this case, the pad oxide film 12 is removed using a hydrofluoric acid (HF) solution, and a part of the gap fill insulating film 17 is also removed to reduce the step difference with the active region.                         

상술한 바와 같이, 종래기술은 STI(Shallow Trench Isolation) 공정을 이용하여 트렌치(14) 내부에 갭필절연막(17)을 갭필하므로써 소자분리막을 형성하고 있고, 리프레시 특성 개선을 위해 라이너질화막(16)을 적용하고 있다.As described above, the prior art forms a device isolation film by gap filling the gap fill insulating film 17 inside the trench 14 by using a shallow trench isolation (STI) process, and the liner nitride film 16 is formed to improve refresh characteristics. It is applied.

그러나, 종래기술은 패드질화막(13) 스트립시, 라이너질화막이 일부 손실되어 아래로 꺼지는 현상이 발생하고, 이 꺼짐 현상으로 인해 후속 패드산화막(12)을 제거하기 위한 공정시 모우트(Moat; 도 1e의 M 참조)가 발생하는 문제가 있다. 여기서, 모우트는 소자분리영역의 모서리가 활성영역의 표면보다 낮아지는 현상을 일컫는 것이다. However, in the prior art, when the pad nitride film 13 is stripped, a phenomenon in which the liner nitride film is partially lost and turned off occurs, and the off phenomenon causes a moat during a process for removing the subsequent pad oxide film 12. 1e (see M of 1e) occurs. Here, the moat refers to a phenomenon in which the edge of the isolation region is lower than the surface of the active region.

위와 같은 모우트는 패드질화막 스트립 공정시 라이너질화막의 손실이 증가하는 경우 확장되는 특성이 있으며, 후속 게이트전극 패터닝시 게이트전극 잔막(Residue)과 같은 소자 특성 열화의 원인이 되므로 반드시 억제되어야 한다.The above-mentioned mot is extended when the loss of the liner nitride film is increased during the pad nitride film strip process, and must be suppressed because it causes deterioration of device characteristics such as gate electrode residual film during subsequent gate electrode patterning.

상술한 모우트의 원인이 되는 라이너질화막의 손실을 줄이기 위해서 패드질화막 스트립 공정시 라이너질화막이 손실되지 않도록 타겟을 조절하면, 패드질화막의 언스트립(Unstrip) 현상을 초래하게 되어, 또다른 소자불량을 발생시키는 문제가 있다.
Adjusting the target so that the liner nitride film is not lost during the pad nitride film strip process in order to reduce the loss of the liner nitride film that causes the above-mentioned mot, an unstrip phenomenon of the pad nitride film is caused, resulting in another device defect. There is a problem that occurs.

본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로, 패드질화막의 스트립공정시에 라이너질화막 손실에 의해 초래되는 모우트의 발생 및 확장을 방지할 수 있는 반도체소자의 소자분리 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and provides a device isolation method of a semiconductor device that can prevent the generation and expansion of the moot caused by the loss of the liner nitride film during the stripping process of the pad nitride film. Its purpose is to.

상기 목적을 달성하기 위한 본 발명의 소자분리 방법은 반도체 기판 상부에 패드산화막, 희생패드막 및 패드질화막의 순서로 적층된 패드패턴을 형성하는 단계, 상기 패드질화막을 하드마스크로 상기 반도체 기판을 식각하여 트렌치를 형성하는 단계, 상기 트렌치 표면 상에 측벽산화막을 형성하는 단계, 상기 측벽산화막을 포함한 전면에 라이너질화막을 형성하는 단계, 상기 라이너질화막 상에 상기 트렌치를 갭필하는 갭필절연막을 형성하는 단계, 상기 패드질화막 표면이 드러날 때까지 상기 갭필절연막을 평탄화시키는 단계, 상기 패드질화막을 스트립하는 단계, 및 상기 희생패드막과 상기 패드산화막을 차례로 스트립하는 단계를 포함하는 것을 특징으로 하며, 상기 희생패드막은 폴리실리콘막으로 형성하는 것을 특징으로 한다.The device isolation method of the present invention for achieving the above object is to form a pad pattern stacked in the order of a pad oxide film, a sacrificial pad film and a pad nitride film on the semiconductor substrate, etching the semiconductor substrate with the pad nitride film as a hard mask Forming a trench, forming a sidewall oxide film on the trench surface, forming a liner nitride film on the entire surface including the sidewall oxide film, and forming a gap fill insulating film for gap filling the trench on the liner nitride film; Planarizing the gap fill insulating layer until the surface of the pad nitride layer is exposed, stripping the pad nitride layer, and sequentially stripping the sacrificial pad layer and the pad oxide layer. It is formed by the polysilicon film.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2g는 본 발명의 실시예에 따른 반도체소자의 소자분리 방법을 도시한 공정 단면도이다.2A through 2G are cross-sectional views illustrating a device isolation method of a semiconductor device in accordance with an embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체기판(21)의 상부에 패드산화막(22)과 패드폴리실리콘막(23) 및 패드질화막(24)을 순차적으로 형성한다. 이때, 패드산화막(22)은 패드폴리실리콘막(23)과 패드질화막(24) 증착시 반도체 기판(21)이 받는 스트레스를 완충시켜주기 위한 것으로 100Å∼150Å 두께로 형성하고, 패드폴리실리 콘막(23)은 후속 라이너질화막의 꺼짐 현상을 방지하기 위해 도입된 희생패드막으로 50Å∼300Å 두께로 형성하며, 패드질화막(24)은 후속 갭필절연막의 CMP 공정시 연마정지막 역할을 수행함과 동시에 트렌치 형성시 하드마스크 역할을 수행하는 것으로, 500Å∼1000Å 두께로 형성한다. As shown in FIG. 2A, a pad oxide film 22, a pad polysilicon film 23, and a pad nitride film 24 are sequentially formed on the semiconductor substrate 21. At this time, the pad oxide film 22 is formed to have a thickness of 100 kPa to 150 kPa to buffer the stress of the semiconductor substrate 21 when the pad polysilicon film 23 and the pad nitride film 24 are deposited. 23) is a sacrificial pad film introduced to prevent turning off of the subsequent liner nitride film, and formed to have a thickness of 50 to 300 mm, and the pad nitride film 24 serves as a polishing stop film during the CMP process of the subsequent gap fill insulating film. To serve as a hard mask, to form a thickness of 500 ~ 1000Å.

다음으로, 패드질화막(24) 상에 감광막을 도포하고 노광 및 현상으로 패터닝하여 소자분리마스크(도시 생략)를 형성하고, 소자분리마스크를 식각배리어로 패드질화막(24), 패드폴리실리콘막(23) 및 패드산화막(22)을 차례로 식각하여 소자분리영역인 트렌치가 형성될 반도체 기판(21) 표면을 노출시킨다. 이어서, 소자분리마스크를 스트립하는데, 이때, 소자분리마스크는 잘 알려진 바와 같이 산소플라즈마를 이용하여 스트립한다.Next, a photoresist film is applied on the pad nitride film 24 and patterned by exposure and development to form a device isolation mask (not shown), and the device isolation mask is an etch barrier for the pad nitride film 24 and the pad polysilicon film 23. ) And the pad oxide film 22 are sequentially etched to expose the surface of the semiconductor substrate 21 on which the trench, which is an isolation region, is to be formed. The device isolation mask is then stripped, wherein the device isolation mask is stripped using oxygen plasma, as is well known.

다음으로, 패드질화막(24)을 하드마스크로 이용하여 노출된 반도체 기판(21) 을 소정 깊이로 식각하여 트렌치(25)를 형성한다.Next, the trench 25 is formed by etching the exposed semiconductor substrate 21 to a predetermined depth by using the pad nitride film 24 as a hard mask.

도 2b에 도시된 바와 같이, 트렌치(25) 형성을 위한 식각공정시 발생된 식각손상을 제거하기 위해 건식 산화(Dry oxidation) 방법으로 측벽산화(Wall oxidation)를 진행하여 50Å∼100Å 두께의 측벽산화막(26)을 형성한다.As shown in FIG. 2B, a sidewall oxide film having a thickness of 50 kPa to 100 kPa is subjected to a wall oxidation by a dry oxidation method in order to remove the etching damage generated during the etching process for forming the trench 25. (26) is formed.

위와 같은 측벽산화막(26) 형성시, 건식산화분위기에 패드폴리실리콘막(23)이 노출되므로, 패드폴리실리콘막(23)의 측면이 산화된다. 이하, 패드폴리실리콘막(23)의 측면산화 부분은 산화폴리실리콘막(23a)이라 약칭하기로 하며, 산화폴리실리콘막(23a)은 50Å∼100Å 두께를 갖는다.When the sidewall oxide film 26 is formed as described above, since the pad polysilicon film 23 is exposed to a dry oxidation atmosphere, the side surface of the pad polysilicon film 23 is oxidized. Hereinafter, the lateral oxide portion of the pad polysilicon film 23 will be abbreviated as a polysilicon oxide film 23a, and the polysilicon oxide film 23a has a thickness of 50 kPa to 100 kPa.

도 2c에 도시된 바와 같이, 측벽산화막(26)을 포함한 패드질화막(24) 상부에 라이너질화막(27)을 형성한다. 이때, 라이너질화막(27)은 LPCVD(Low Pressure Chemical Vapor Deposition) 방식을 이용하여 50Å∼100Å 두께로 증착한다.As shown in FIG. 2C, a liner nitride layer 27 is formed on the pad nitride layer 24 including the sidewall oxide layer 26. At this time, the liner nitride film 27 is deposited to a thickness of 50 kPa to 100 kPa using a low pressure chemical vapor deposition (LPCVD) method.

한편, 라이너질화막(27)은 PECVD(Plasma Enhanced Chemical Vapor Deposition) 또는 ALD(Atomica Layer Deposition)을 이용하여 형성할 수도 있다.The liner nitride layer 27 may be formed using a plasma enhanced chemical vapor deposition (PECVD) or an atom layer deposition (ALD).

도 2d에 도시된 바와 같이, 라이너질화막(27) 상부에 트렌치(25)를 갭필할 때까지 갭필절연막(28)을 증착한다. 이때, 갭필절연막(28)은 고밀도플라즈마 방식의 산화막 또는 TEOS 산화막으로 증착한다.As shown in FIG. 2D, the gap fill insulating layer 28 is deposited on the liner nitride layer 27 until the trench 25 is gap filled. At this time, the gap fill insulating film 28 is deposited by an oxide film of a high density plasma method or a TEOS oxide film.

다음으로, 패드질화막(24)을 연마정지막으로 이용한 CMP 공정을 진행하여 갭필절연막(28)을 평탄화시킨다. 이때, CMP 공정시 패드질화막(24) 위에 형성된 라이너질화막이 연마된다.Next, a CMP process using the pad nitride film 24 as the polishing stop film is performed to planarize the gap fill insulating film 28. At this time, the liner nitride film formed on the pad nitride film 24 during the CMP process is polished.

도 2e에 도시된 바와 같이, 산화막 습식 딥 공정을 통해 갭필절연막(28)을 추가로 식각한다. 이때, 갭필절연막(28)은 패드폴리실리콘막(23)의 측면까지 높이를 낮춘다.As shown in FIG. 2E, the gap fill insulating layer 28 is further etched through an oxide wet dip process. At this time, the gap fill insulating film 28 is lowered to the side of the pad polysilicon film 23.

이어서, 패드질화막(24)의 스트립 공정을 진행한다. 이때, 패드질화막(24)의 스트립 공정은 인산(H3PO4) 용액을 이용한다.Subsequently, the strip process of the pad nitride film 24 is performed. In this case, the strip process of the pad nitride layer 24 uses a phosphoric acid (H 3 PO 4 ) solution.

상기한 패드질화막(24)의 스트립 공정시, 패드폴리실리콘막(23)이 식각배리어 역할을 하고, 인산 용액에 대해 산화막질인 산화폴리실리콘막(23a)은 선택비를 가지므로 패드질화막(24) 스트립시에 제거되지 않는다.In the strip process of the pad nitride film 24, the pad polysilicon film 23 serves as an etching barrier, and the polysilicon oxide film 23a, which is an oxide film with respect to the phosphoric acid solution, has a selectivity. ) It is not removed when stripping.

위와 같은 패드질화막(24)의 스트립 공정시에 라이너질화막(27)이 패드질화 막(24)의 측면을 통해 식각되어 트렌치(25) 내부에 잔류하는데, 패드폴리실리콘막(23)의 측면에 형성된 산화폴리실리콘막(23a)이 인산용액의 침투 경로를 길게 해주는 역할을 하므로 라이너질화막(27)의 식각 손실을 감소시킨다. 즉, 인산용액이 라이너질화막까지 도달하는 길이를 길게 해주어 패드질화막(23)을 완전히 제거할때까지 인산용액을 도입하더라도 라이너질화막이 꺼지는 것을 방지한다.During the stripping process of the pad nitride layer 24 as described above, the liner nitride layer 27 is etched through the side of the pad nitride layer 24 to remain in the trench 25, and formed on the side of the pad polysilicon layer 23. Since the polysilicon oxide film 23a serves to lengthen the penetration path of the phosphate solution, the etch loss of the liner nitride film 27 is reduced. That is, the length of the phosphate solution to reach the liner nitride film is lengthened to prevent the liner nitride film from turning off even when the phosphoric acid solution is introduced until the pad nitride film 23 is completely removed.

특히, 패드폴리실리콘막(23)의 두께만큼 인산용액의 침투 경로는 더욱 길어지므로 라이너질화막(27)의 식각 손실이 감소하고, 이로써 잔류하는 라이너질화막(27a)의 꺼짐 현상이 억제된다. 일예로, 패드폴리실리콘막을 적용하지 않은 경우 패드질화막 스트립시에 라이너질화막이 꺼짐 두께가 20Å이라고 가정하면, 패드폴리실리콘막은 20Å보다 두껍게 형성해주므로써 라이너질화막의 과도한 식각손실을 방지한다.In particular, since the penetration path of the phosphate solution becomes longer by the thickness of the pad polysilicon film 23, the etching loss of the liner nitride film 27 is reduced, thereby suppressing the turning off of the remaining liner nitride film 27a. For example, when the pad polysilicon film is not applied, assuming that the liner nitride film is turned off at a thickness of 20 kPa when the pad nitride film strip is not formed, the pad polysilicon film is formed to be thicker than 20 kPa to prevent excessive etching loss of the liner nitride film.

한편, 패드질화막(24)을 충분히 제거하기 위해 과도식각을 수반한다고 하더라도 패드폴리실리콘막(23)의 높이만큼 마진이 증가하므로 라이너질화막(27a)의 과도한 손실을 방지할 수 있다. 예컨대, 아무리 패드질화막(24)의 과도식각 시간이 길더라도, 패드폴리실리콘막(23)을 도입하면 패드산화막(22)의 측면까지의 높이로 잔류시킬 수 있다.On the other hand, even if it involves excessive etching to sufficiently remove the pad nitride film 24, the margin increases by the height of the pad polysilicon film 23, thereby preventing excessive loss of the liner nitride film 27a. For example, no matter how long the overetching time of the pad nitride film 24 is long, the introduction of the pad polysilicon film 23 can leave the pad oxide film 22 at a height up to the side surface of the pad oxide film 22.

도 2f에 도시된 바와 같이, 패드폴리실리콘막(23)을 스트립한다. 이때, 패드폴리실리콘막(23)의 스트립은 HBr 또는 Cl 가스를 이용한다.As shown in Fig. 2F, the pad polysilicon film 23 is stripped. At this time, the strip of the pad polysilicon film 23 uses HBr or Cl gas.

위와 같은 패드폴리실리콘막(22) 스트립시에 패드산화막(22), 라이너질화막(27a), 측벽산화막(26)이 반도체기판(21)을 덮고 있기 때문에 어택이 발생하지 않 는다.Since the pad oxide film 22, the liner nitride film 27a, and the sidewall oxide film 26 cover the semiconductor substrate 21 at the time of stripping the pad polysilicon film 22 as described above, no attack occurs.

도 2g에 도시된 바와 같이, 패드산화막(22)을 스트립한다. 이때, 패드산화막(22)은 불산(HF) 용액을 이용하여 제거하며, 산화막질인 갭필절연막(28)도 불산용액에 의해 일부가 제거되어 활성영역과의 단차가 감소한다.As shown in FIG. 2G, the pad oxide film 22 is stripped. At this time, the pad oxide film 22 is removed using a hydrofluoric acid (HF) solution, and a portion of the gap fill insulating film 28, which is an oxide film, is also removed by the hydrofluoric acid solution, thereby reducing the step difference with the active region.

결국, 패드산화막(22)까지 스트립한 후의 소자분리 구조를 살펴보면, 트렌치(25) 표면 상에 측벽산화막(26)이 형성되고, 측벽산화막(26) 표면 상에 라이너질화막(27a)이 형성되며, 라이너질화막(27a) 상에 트렌치(25)를 갭필하는 갭필절연막(28)이 잔류한다. 위와 같은 소자분리 구조에서, 라이너질화막(27a)의 꺼짐 현상이 없는 것을 알 수 있다.As a result, looking at the device isolation structure after stripping up to the pad oxide layer 22, the sidewall oxide layer 26 is formed on the trench 25 surface, and the liner nitride layer 27a is formed on the sidewall oxide layer 26. A gap fill insulating film 28 for gap filling the trench 25 remains on the liner nitride film 27a. In the device isolation structure as described above, it can be seen that the liner nitride layer 27a is not turned off.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명은 패드산화막과 패드질화막 사이에 패드폴리실리콘막을 형성하여 후속 패드질화막 스트립공정시 침투 경로를 길게 하므로써 라이너질화막의 과도한 손실을 억제하여 라이너질화막의 꺼짐 현상을 방지하고, 이로써 모우트 발생 및 확장을 근본적으로 방지할 수 있는 효과가 있다.The present invention as described above forms a pad polysilicon film between the pad oxide film and the pad nitride film to lengthen the penetration path during the subsequent pad nitride film strip process, thereby suppressing excessive loss of the liner nitride film, thereby preventing the liner nitride film from being turned off, thereby generating moat. And expansion can be prevented fundamentally.

Claims (5)

반도체 기판 상부에 패드산화막, 희생패드막 및 패드질화막의 순서로 적층된 패드패턴을 형성하는 단계;Forming a pad pattern stacked on the semiconductor substrate in the order of a pad oxide film, a sacrificial pad film, and a pad nitride film; 상기 패드질화막을 하드마스크로 상기 반도체 기판을 식각하여 트렌치를 형성하는 단계;Etching the semiconductor substrate using the pad nitride layer as a hard mask to form a trench; 상기 트렌치 표면 상에 측벽산화막을 형성하는 단계;Forming a sidewall oxide film on the trench surface; 상기 측벽산화막을 포함한 전면에 라이너질화막을 형성하는 단계;Forming a liner nitride film on the entire surface including the sidewall oxide film; 상기 라이너질화막 상에 상기 트렌치를 갭필하는 갭필절연막을 형성하는 단계;Forming a gap fill insulating film on the liner nitride film to gap fill the trench; 상기 패드질화막 표면이 드러날 때까지 상기 갭필절연막을 평탄화시키는 단계;Planarizing the gap fill insulating film until the pad nitride film surface is exposed; 상기 패드질화막을 스트립하는 단계; 및Stripping the pad nitride film; And 상기 희생패드막과 상기 패드산화막을 차례로 스트립하는 단계Stripping the sacrificial pad layer and the pad oxide layer in sequence 를 포함하는 반도체소자의 소자분리 방법.Device isolation method of a semiconductor device comprising a. 제1항에 있어서,The method of claim 1, 상기 희생패드막은, The sacrificial pad film, 폴리실리콘막으로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방 법.Device isolation method of a semiconductor device, characterized in that formed of a polysilicon film. 제2항에 있어서,The method of claim 2, 상기 폴리실리콘막은, 50Å∼300Å 두께로 형성하는 것을 특징으로 하는 반도체소자의 소자분리 방법.Wherein said polysilicon film is formed to a thickness of 50 mW to 300 mW. 제2항에 있어서,The method of claim 2, 상기 희생패드막으로 사용된 폴리실리콘막의 스트립은,The strip of polysilicon film used as the sacrificial pad film, 건식 식각 방법으로 진행하는 것을 특징으로 하는 반도체소자의 소자분리 방법.Device isolation method of a semiconductor device, characterized in that the dry etching method. 제4항에 있어서,The method of claim 4, wherein 상기 폴리실리콘막의 스트립은,The strip of polysilicon film, HBr 또는 Cl 가스를 이용하는 것을 특징으로 하는 반도체소자의 소자분리 방법.Device separation method of a semiconductor device, characterized in that using HBr or Cl gas.
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