KR20060002875A - Wafer carrier having improved processing characteristics - Google Patents

Abstract

A wafer carrier for supporting a plurality of wafers, including a plurality of slots provided in a cradle, the cradle being formed of silicon carbide and having an oxide layer overlying the silicon carbide.

Description

Wafer carrier with improved processing characteristics {WAFER CARRIER HAVING IMPROVED PROCESSING CHARACTERISTICS}

FIELD OF THE INVENTION The present invention relates generally to kiln furniture, and more particularly to a wafer carrier for supporting a wafer that undergoes processing, such as exposure to high temperature processing operations. In addition, the present invention relates generally to wafer processing using such wafer carriers.

As will be appreciated in the art, semiconductor processes generally employ workpieces to support and / or transport semiconductor wafers during various processing steps, including high temperature processes including annealing, chemical vapor deposition, oxidation, and the like. . In this regard, horizontal and vertical wafer carriers, also known in the art as wafer boats, are generally used to support a plurality of wafers spaced from each other at a constant pitch to form an array of wafers. In this regard, exposure of wafers to processing operations is generally known as " batch processing " in which a plurality of wafers are processed simultaneously.

With the reduction in transistor critical dimensions, die size and integrated circuit size, the actual diameter of the wafer being processed continues to increase. For example, the industry has moved from 101,6 mm (4 inches) to 152.4 mm (6 inches) wafers, and recently 203.2 mm (8 inches) wafers are commonly used. Moreover, 300 mm (12 inch) semiconductor manufacturing equipment (equipment) is coming. With the introduction of increased wafer size, new processing problems arise at many stages of the manufacturing process.

In addition, semiconductor wafers mainly composed of silicon include conventional integrated circuit structures, including logic and memory devices, as well as opto-electronic devices such as waveguide multiplexers and microelectromechanical systems (MEMS). It is used for formation. In this regard, device fabrication often employs an extended oxidation step in which semiconductor wafers are often oxidized for extended periods of time beyond those typically encountered in conventional semiconductor processing. For example, it is common to expose the wafers to processing operations simultaneously for several days, such as about 5-10 days. As mentioned above, often such processing operations involve the oxidation of the wafer.

In terms of extended process time, as well as increased wafer size, technical challenges arise that affect the robustness and quality of the device. In this regard, the inventors encountered a defect in the wafer after undergoing such processing operations such as local or even ultimate destruction of the wafer. Other defects include deformation and notch formation around the periphery at points that contact the wafer carrier, such as the bottom support of the wafer carrier, especially in the case of horizontal wafer boats.

Accordingly, there is a need in the art for improved wafer carriers or boats and especially for horizontal wafer carriers and for improved processing operations that provide improved device yield and low defects.

According to one aspect of the present invention, a wafer carrier for supporting a plurality of wafers is provided, the carrier comprising a plurality of slots provided in the cradle, the cradle comprising silicon carbide and an oxide layer covering the silicon carbide. Has

According to another aspect of the present invention, a wafer carrier having a plurality of slots having a specific width is provided. In particular, the portion of each slot has a width (w _s), w _s is at least about 1.30t _w, t _w is the thickness of the wafer.

According to another feature of the invention there is provided a wafer carrier for supporting a plurality of wafers, the wafer having a radius r _w , the wafer carrier comprising a plurality of slots for supporting the wafer, at least of each slot Some have a radius of curvature r _s that is greater than about 1.15 r _w . According to a variant of this aspect of the invention, r _s may have a negative value while r _w has a positive value.

According to another aspect of the present invention, a plurality of wafers are loaded on a wafer carrier having one or all of the features described above, and the plurality of wafers are subjected to a processing operation on the wafer while being loaded on the wafer carrier. A method is provided. The processing operation may be that the wafer is exposed to an oxidizing environment to oxidize the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood with reference to the accompanying drawings, and numerous objects, features, and advantages thereof will be apparent to those skilled in the art.

1 is a perspective view of a horizontal wafer carrier according to an embodiment of the invention.

2 is a cross-sectional view of a horizontal wafer carrier in accordance with an embodiment of the present invention loaded with a silicon wafer.

3 is a graph depicting oxide growth curves on silicon carbide wafer carriers.

4 illustrates a radius of curvature of a slot in which a semiconductor wafer is loaded in accordance with an embodiment of the present invention.

5 illustrates a radius of curvature of a slot in which a semiconductor wafer is loaded in accordance with another embodiment of the present invention.

6 illustrates a radius of curvature of a slot in which a semiconductor wafer is loaded in accordance with another embodiment of the present invention.

Fig. 7 shows the thickness of the wafer with respect to the width of the slot in the cross section of the state loaded in the slot according to the embodiment of the present invention.

Like reference numerals in different drawings indicate similar or identical items.

According to an embodiment of the present invention, a specific wafer carrier is provided for supporting a plurality of wafers. In this regard, reference is made to FIG. 1, which shows a perspective view of a wafer carrier according to an embodiment of the invention. As shown, the wafer carrier 1 has a plurality of cradle arms 3 generally having an open structure and generally taking an arcuate shape and integrally formed with a plurality of support members for supporting the wafer. It includes a cradle (2) comprising a. In particular, first, second and third support members 10, 12, 14 are provided, each of which protrudes radially inward, thus providing a plurality of slots 16. Each slot 16 is arranged and oriented to be positioned along the same arc of fixed radius to support a single respective wafer. Each slot consists of first, second and third slot segments 18, 20, 22, respectively, each of which follows the first, second and third support members 10, 12, 14. Each is located.

As shown in FIG. 2, a cross-sectional view is provided showing the orientation of the wafer 30 bonded and stacked on the wafer carrier 1. The general orientation of the wafer carrier shown in FIGS. 1 and 2 is horizontal, in particular the orientation of the wafer carrier when used in a semiconductor manufacturing environment. As shown, the carrier generally supports the wafer in an upward vertical position.

As most clearly shown in FIG. 1, the slots 16 are arranged in a linear array and spaced apart from one another at a constant pitch. For example, the second slot segments 20 are shown in an array format spaced apart from one another at a constant pitch. As such, the wafer is held linearly by the carrier to form a horizontal stack of wafers. The pitch of the grooves, and therefore the pitch of the wafer, may vary depending on the particular application, but is generally in the range of about 2 to about 4 mm, nominally about 2.38 mm.

As shown in FIG. 2, the first, second and third support members 10, 12, 14 have a first, second and third support member sequentially positioned along the arc 32 and the second. The support member is positioned along an arc 32 having a radius equal to the radius r _W of the wafer such that the support member is circumferentially positioned between the first and third support members 10, 14. In this regard, since the second support member is disposed at the lowest position, that is, the six o'clock position, it generally supports a substantial portion of the weight of the wafer. The arc 32 spans an angle of less than 180 degrees to facilitate loading of the wafer. Generally, the support is positioned to form an arc 32 of about 150 degrees or less or generally about 130 degrees or less.

Although three support members are shown in FIGS. 1 and 2, the wafer carrier may have a different number of support members. For example, the second support member can be branched to form two separate support members having separate slot segments. In this case, the support member may be evenly spaced from the lowest six o'clock position.

As mentioned above, wafer carriers generally have an open design, which provides a number of advantages, as described in more detail below. Generally, a window formed between the cradle arm 3 and the support member provides at least 40% open area along the outer portion cylindrical surface of the cradle. Generally, the open area is less than about 50%. The open design of this wafer carrier advantageously improves the gas flow around the wafer carrier during the preliminary oxidation step, forming a compliant and relatively uniform oxide layer.

As for the material of the wafer carrier, as described above, the cradle is composed of silicon carbide. According to one embodiment, silicon carbide comprises recrystallized silicon carbide, a material known in the art. Generally, a green body containing semiconductor grade silicon carbide powder is mixed with a sintering aid and a binder, molded into a desired shape, dried, heated to burn-out the organic binder, and Heat treatment to densify and recrystallize. Following densification, processing steps can be used to reach the final dimensions of the wafer carrier.

Other types of silicon carbide may be used instead of or in combination with recrystallized silicon carbide. For example, the silicon carbide substrate may be formed by a conversion process in which the carbon preform is converted to silicon carbide by gas phase or liquid phase techniques. Generally, in this case, the preform is formed of a carbonaceous material such as semiconductor grade graphite. In addition, in the case of using porous silicon carbide for the substrate of the wafer carrier, the carrier may be impregnated with silicon. This compositional feature is known as Si-SiC or siliconized silicon carbide. In this regard, after the formation of a relatively porous silicon carbide substrate, the substrate is impregnated with molten silicon to densify the structure to an extent suitable for use in refractory applications such as in semiconductor processing environments. Siliconized silicon carbide may be coated with an additional layer of silicon carbide, such as chemical vapor deposition (CVD) silicon carbide.

In addition, the wafer carrier may be formed of freestanding SiC formed by CVD. In this case, an extended CVD process is performed to form the wafer carrier itself.

An oxide layer is provided to cover the silicon carbide of the wafer carrier. The oxide layer may be formed by oxidation of the carrier in an oxidizing environment, such as oxidizing the carrier in an elevated oxygen-containing environment, such as in the range of 950 to about 1300 ° C., more generally in the range of about 1000 to about 1250 ° C. Can be. Oxidation can be carried out in a dry or wet environment and is generally carried out at atmospheric pressure. The wet atmosphere can be produced by introducing steam and serves to increase the rate of oxidation and to improve the density of the oxide layer. In this regard, wet oxidation at 1150 ° C. can form a solid, thick (about 2-3 micron, etc.) oxide layer for about 12-48 hours. On the other hand, such a layer may take about 5 days, such as 10-20 days, to form according to the dry oxidation treatment. In general, the oxide layer is formed by oxidation, but it may also be deposited by reacting the TEOS source gas or the like. However, thermal growth layers may be desirable for durability and robustness.

In general, the oxide layer is silicon oxide, generally SiO ₂ . The silicon oxide layer may be in direct contact with the silicon carbide of the wafer carrier. Alternatively, an intermediate layer such as silicon may be present between the silicon carbide and the upper oxide layer, as in the case of silicon impregnated silicon carbide.

3 shows a growth curve of an oxide layer as a function of time on a silicon carbide wafer carrier. As shown, the oxide layer generally follows the parabolic growth curve. For reasons described below, according to one embodiment of the present invention, the oxide layer has a thickness on top of a relatively rapid growth portion of the curve. For example, the oxide layer may have a thickness of at least about 0.5 microns, or in particular at least about 0.75 microns, such as at least about 1.0 microns and even 1.5 microns. According to certain embodiments of the present invention, the oxide has a thickness of at least 2 microns, such as on the order of about 2 to about 3 microns. Note that the oxide layer according to an embodiment of the present invention is a layer provided on the wafer carrier as opposed to any natural oxide that may be present on the wafer carrier, but with a relatively small thickness. In addition, although the above-described oxide layer is generally formed by a thermal oxidation technique, other techniques such as direct deposition of the oxide layer may also be used.

Formation of oxide layers, such as by thermal pre-oxidation steps, has been found to improve process control in semiconductor manufacturing environments. In particular, the inventors have found that during normal oxidation treatment to form a relatively thick oxide layer on a wafer, the wafer tends to bond with the wafer carrier through the growth of the oxide layer forming the wafer carrier and / or the oxide layer on the wafer. It was recognized. During subsequent cooling of the wafer / wafer carrier assembly, the difference in shrinkage due to the difference in the coefficient of thermal expansion of the wafer and the carrier is considered to generate thermally induced stress in the wafer. Such differences in thermal expansion / contraction properties can be attributed to compositional and structural differences and ultimately can cause damage to the wafer. In the extreme case, the wafer may ultimately be destroyed by the cracking mechanism. By incorporation of a preliminary oxidation step to form an oxide layer on the carrier, the growth of the oxide layer on the carrier during the heat treatment of the wafer is weakened, and the tendency of bonding between the wafer and the carrier is reduced, resulting in process control and wafer yield. Improve.

According to another feature of the invention, the slot in the wafer carrier has a specific radius of curvature r _s which further improves process control and wafer yield, especially during the high temperature treatments described above.

As shown in connection with FIG. 2, the wafer has a nominal radius r _w . Current wafer facilities use 203.2 mm (8 inches) and moreover 300 mm (12 inches diameter) wafers. Thus, newer facilities may use wafers with a radius r _w on the order of about 150 mm, while older facilities may use smaller wafers and newer facilities may use larger wafers. According to a particular feature of one embodiment, the radius of curvature r _s of the slot is at least about 1.15 r _w . In other words, the radius of curvature of the slots for supporting the wafer is at least 15% greater than the radius of the wafer. In general, _s r is about 1.25r _w or more, such as 1.35r 1.50r _w and _w. Referring to FIG. 4, r _s is shown approximately twice the r _w . Moreover, the radius of curvature of the slot can approach a straight line (r _s = infinite). This particular embodiment is shown in FIG. 5. In this case, the portion of the slot in contact with the wafer extends along a straight line.

Moreover, the radius of curvature of the slots may have an opposite orientation, ie it may have a negative radius of curvature as compared to the radius r _w of the wafer. This is shown in FIG. 6 in which the slot is generally convex and has a radius extending in the opposite direction of the radius of the wafer from the point of contact between the wafer and the slot.

In this embodiment, each slot segment is not required to have the same radius of curvature. In general, however, at least a portion of the second slot segment along the second support member has a radial characteristic as described above.

By providing a slot with a radius of curvature r _s as described above, the potential oxidized junction area between the wafer and the carrier is minimized. As such, oxide bonds are formed between the wafer and the carrier, so that the minimized junction interface is weakened and more likely to break during processing (eg, during cooling), whereby as described above, Dampen thermal stress.

According to another embodiment of the present invention, at least some of the slots of the wafer carrier have a width w _s greater than the thickness t _w of the wafer. In particular, the width w _s is generally at least about 1.30 t _w . According to another embodiment, w _s are generally from about 1.35t _w or more, may be in the range of from about to about 1.50t 1.35t _{w w.} In this regard, FIG. 7 shows the width w _s of the slot relative to the thickness t _w of the wafer (not shown to scale). The actual thickness t _w of the wafer may be changed based on the wafer brand, the intended use, the wafer diameter, the composition (eg, silicon on insulator (SOI)), and the like. In general, however, wafers typically have a thickness in the range of about 0.45 mm to about 0.80 mm, more typically between about 0.50 to about 0.765 mm. By providing slots with the above relative widths, in contrast to narrower widths, such as on the order of 1.10 t _w to 1.25 t _w , the formation of a relatively thick oxide layer is facilitated by the extra space in the slots. In addition, by attenuating the extent to which the wafer is confined within the slot during oxide growth, wafer creep is not a problem. In this regard, using conventional techniques, the restraint of the wafer in the slot tends to creep the wafer to a high temperature, causing notch formation. Formation of the notch of the wafer around the outer circumference tends to form a mechanical interlocking structure, which is disadvantageous. In particular, upon cooling, the notch tends to engage with the slot and due to the different heat shrinkage characteristics of the wafer and the wafer carrier is a cause of mechanical stress on the wafer upon cooling.

In addition to the specific features of the embodiment of the wafer carrier as described above, the present invention also provides a plurality of wafer processes known as batch processes. In this regard, the wafer carrier is generally loaded with a plurality of wafers arranged in a linear array at a constant pitch. Thereafter, the wafer / wafer carrier assembly is placed in a furnace, such as a process tube, for high temperature processing. As mentioned above, one preferred processing operation is the formation of a relatively thick oxide layer on a wafer, particularly suitable for MEMS and photoelectric applications.

While embodiments of the invention have been specifically described above, it is understood that various changes may be made without departing from the scope of the claims of the invention.

Claims (34)

In the wafer carrier for supporting a plurality of wafers, A plurality of slots provided in the cradle, And the cradle includes silicon carbide and has an oxide layer covering the silicon carbide. The wafer carrier of claim 1, wherein the cradle comprises recrystallized silicon carbide. The wafer carrier of claim 1, wherein the cradle is silicon impregnated silicon carbide. The wafer carrier of claim 1, wherein the cradle comprises converted silicon carbide. The wafer carrier of claim 1, wherein the cradle comprises free-standing CVD SiC. The wafer carrier of claim 1, wherein the oxide layer comprises silicon oxide. The wafer carrier of claim 6, wherein the silicon oxide has a thickness of at least about 0.5 micron. The wafer carrier of claim 6, wherein the silicon oxide has a thickness of about 0.75 microns or more. The wafer carrier of claim 6, wherein the silicon oxide has a thickness of at least about 1.0 micron. The wafer carrier of claim 6, wherein the silicon oxide has a thickness of at least about 1.5 microns. The wafer carrier of claim 1, wherein the oxide layer is thermally grown. The wafer carrier of claim 1, wherein the oxide layer is deposited. The wafer carrier of claim 1, wherein the wafer carrier is a horizontal wafer carrier for supporting a wafer oriented generally in an upright vertical position. The wafer carrier of claim 1, wherein the slots are arranged in a linear array and spaced apart from each other at a constant pitch. A wafer carrier for supporting a plurality of wafers, the wafer having a thickness t _w , the wafer carrier comprising a plurality of slots for supporting an array of wafers, at least a portion of each slot having a slot width w _s And w _s is about 1.30 t _w or more. The wafer carrier of claim 15, wherein w _s is at least about 1.35 t _w . The wafer carrier of claim 15, wherein w _s is in a range from about 1.35 t _w to about 1.50 t _w . The apparatus of claim 1, wherein the cradle comprises at least first, second, and third support members, each of the support members being provided to support and contact the wafer, wherein each slot is configured to support the first, second, and first contacts. 3. A wafer carrier having first, second and third slot segments respectively extending along a support member. 19. The device of claim 18, wherein the first, second and third slot segments are located along an arc having a radius equal to the radius of the wafer, wherein the first, second and third support members are formed by the second support member. A wafer carrier sequentially positioned along an arc so as to be circumferentially positioned between the first and third support members. 20. The wafer carrier of claim 19, wherein said portion of each slot having a slot width w _s comprises at least a portion of said second slot segment. 20. The wafer carrier of claim 19, wherein the first, second, and third slot segments are spaced along the arc that is less than 180 degrees. 20. The wafer carrier of claim 19, wherein the first, second, and third slot segments are spaced along the arc that is no greater than 150 degrees. A wafer carrier for supporting a plurality of wafers, the wafer having a radius r _w , the wafer carrier including a plurality of slots for supporting the plurality of wafers, at least a portion of each slot having a radius of curvature r _s And r _s is at least about 1.15 r _w . The wafer carrier of claim 23, wherein r _s is at least about 1.25 r _w . The wafer carrier of claim 23, wherein r _s is at least about 1.35 r _w . The wafer carrier of claim 23, wherein r _s is at least about 1.50 r _w . The wafer carrier of claim 23, wherein r _s is infinite and at least a portion of each slot extends along a straight line. A wafer carrier for supporting a plurality of wafers, the wafer having a radius r _w , the wafer carrier comprising a plurality of slots for supporting an array of wafers, at least a portion of each slot having a radius of curvature r _s Wherein r _s is a negative value and r _w is a positive value. In the method for processing a plurality of wafers, Loading a plurality of wafers into a wafer carrier, Applying a processing operation to the wafer, And the wafer carrier comprises a plurality of slots provided in a cradle, the cradle comprising silicon carbide and having an oxide layer covering the silicon carbide. 30. The method of claim 29, wherein the processing operation comprises exposing the wafer to an oxidizing environment to oxidize the wafer. 30. The method of claim 29, wherein the oxide layer is formed by oxidation at a temperature higher than the temperature of the processing operation. In the method for processing a plurality of wafers, Loading a plurality of wafers into a wafer carrier, Applying a processing operation to the wafer, The wafer has a radius r _w , the wafer carrier comprises a plurality of slots for supporting a plurality of wafers, at least a portion of each slot having a radius of curvature r _s , wherein r _s is a plurality of at least about 1.15 r _w Wafer processing method. In the method for processing a plurality of wafers, Loading a plurality of wafers into a wafer carrier, Applying a processing operation to the wafer, The wafer has a thickness t _w , the wafer carrier comprises a plurality of slots for supporting the array of wafers, at least a portion of each slot having a slot width w _s , w _s being at least about 1.30 t _w A plurality of wafer processing methods. A wafer carrier for supporting a plurality of wafers, the wafer having a thickness t _w and a radius r _w , the wafer carrier including a plurality of slots for supporting the plurality of wafers, at least a portion of each slot being Having a slot width w _s and a radius of curvature r _s , w _s is at least about 1.30 t _w and r _s is at least about 1.15 r _w and the wafer carrier further comprises silicon carbide and an oxide layer covering the silicon carbide Wafer carrier.

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