JP2006521689A - Wafer carrier with improved processing characteristics - Google Patents

Abstract

A wafer carrier for supporting a plurality of wafers includes a plurality of slots provided in the cradle, and the cradle is made of silicon carbide and has an oxide layer covering the silicon carbide.

Description

  The present invention relates generally to kiln furniture, and more particularly to a wafer carrier that supports a wafer to withstand processes that are exposed to high temperature processing practices. Furthermore, the present invention relates generally to wafer processing utilizing such wafer carriers.

  Semiconductor processing is typically performed during various processing stages, including high temperature processing, including annealing, chemical vapor deposition, oxidation, etc., as understood in this field. A workpiece for supporting and / or transporting a semiconductor wafer is used. In addition, in this field, horizontal and vertical wafer carriers, known as wafer boats, typically form an array of wafers spaced apart from each other by a fixed pitch to support multiple wafers. It is used to do. Here, subjecting a wafer to a processing operation is widely known as batch processing ("batch processing") in which a plurality of wafers are processed simultaneously.

  With the reduction of transistor critical dimensions, die size and integrated circuit size, research continues to increase the actual diameter of the wafer being processed. For example, in manufacturing, moving from 4 to 6 inch wafers, 8 inch wafers are now commonly used. In addition, 12 inch (300 mm) semiconductor manufacturing plants (fabs) are becoming used. With the introduction of increased wafer sizes, new technical problems have arisen at many stages of the manufacturing process.

  In addition, semiconductor wafers made primarily of silicon are not only used to fabricate conventional integrated circuit configurations including logic and memory devices, but also include waveguide multiplexers and micro-electromechanical systems (micro-electromechanical systems). -mechanical systems (MEMS) are also being used in opto-electronic devices. By the way, the manufacture of devices sometimes makes use of an extended oxidation process step in which the semiconductor wafer is oxidized for an extended time beyond that normally performed in traditional semiconductor processes. For example, it is not uncommon for wafers to be subjected to processing on a daily basis such as 5-10 days. As mentioned above, the performance of the process often involves an oxidation process on the wafer.

  The extended processing time creates technical problems that affect device robustness and quality, as well as increased wafer size. In contrast, the inventors have encountered defects in the wafer after such processing has been performed, whether it is limited or catastrophic damage to the wafer. Other defects include wafer deformation and notching at the outer periphery, particularly at the contact points between the wafer and the wafer carrier, such as the bottom support of the wafer carrier in the case of a horizontal wafer container.

  Accordingly, there is a need in the art for improved wafer carriers and containers, particularly horizontal wafer carriers, and improved processing practices that provide improved device yield and low defectivity.

  According to one aspect of the present invention, a wafer carrier for supporting a plurality of wafers, the wafer carrier including a plurality of slots provided in a cradle, the cradle comprising silicon carbide and the silicon carrier A wafer carrier is provided having an oxide layer overlying the carbide. According to one aspect of the present invention, a wafer carrier for supporting a plurality of wafers, the wafer carrier including a plurality of slots provided in a cradle, the cradle comprising silicon carbide and the silicon carrier A wafer carrier is provided having an oxide layer overlying the carbide.

  According to another aspect of the invention, a wafer carrier having a plurality of slots having a predetermined width is provided. In particular, at least a portion of each slot has a width (Ws), which is greater than or equal to about 1.30 times the wafer thickness tw.

  According to yet another aspect of the present invention, a wafer carrier for supporting a plurality of wafers, the wafer having a radius rw, the wafer carrier including a plurality of slots for supporting the wafers, At least a portion of each slot has a radius of curvature rs, wherein the curvature rs is about 1.15 times greater than or equal to the radius of the wafer rw. According to a variation of this aspect of the invention, the curvature rs has a negative value and the radius rw of the wafer has a positive value.

  According to another aspect of the present invention, a plurality of wafers are mounted on a wafer carrier having any one or all of the configurations described above, and the wafers are mounted on the wafer carrier for performing processing. A method of processing a plurality of conforming wafers is provided. The implementation of the process exposes the wafer to an oxidizing environment to oxidize the wafer.

  BRIEF DESCRIPTION OF THE DRAWINGS The invention will be better understood and the numerous objects, configurations and advantages of the invention will become apparent to those skilled in the art by reference to the accompanying drawings.

  Note that the same reference numerals in different drawings indicate the same or the same thing.

  According to an embodiment of the present invention, a special wafer carrier is provided to support a plurality of wafers. Attention is now directed to FIG. 1, which shows a perspective view of a wafer carrier according to one embodiment of the present invention. As shown, the wafer carrier 1 includes a cradle 2, which generally has an open structure and a plurality of cradles that generally have an arcuate shape integrated with a plurality of support members to support the wafer. Arm 3 is included. In particular, the cradle is provided with first, second and third support members 10, 12 and 14, each support member projecting inward, and a plurality of slots 16 are provided along them. Yes. Each slot 16 is positioned and aligned to lie along the same arc of fixed radius to support one wafer each. Each slot 16 is composed of first, second and third slot segments 18, 20 and 22, respectively, and each slot segment is along the first, second and third support members 10, 12 and 14, respectively. Is positioned.

  As shown in FIG. 2, a cross-sectional view is provided that illustrates the application of a wafer 30 that is mated and mounted on a wafer carrier 1. The general application of the wafer carrier shown in FIGS. 1 and 2 is horizontal, the application of the wafer carrier in use, particularly in a semiconductor manufacturing plant environment. As shown, the carrier supports the wafer in a generally vertical position.

  As most clearly shown in FIG. 1, the slots 16 are arranged as a linear array and are spaced apart from each other by a constant pitch. For example, the second slot segments 20 are depicted as being spaced apart from each other by a fixed pitch in any arrangement scheme. Therefore, it is supported linearly by the wafer carrier and constitutes a horizontal stack of wafers. The pitch of the grooves, and thus the pitch of the wafer, will vary depending on the particular application, but is generally in the range of about 2 mm to 4 mm, nominally about 2.38 mm.

  As shown in FIG. 2, the first, second, and third support members 10, 12, and 14 are configured so that the second and third support members are continuously disposed along the arc 32 and the second The support members are arranged along an arc 32 having a radius equal to the radius of the wafer rw so as to surround the periphery of the first and third support members 10 and 14. Here, since the second support member is disposed at the bottommost portion of the wafer, that is, at the 6 o'clock position, the second support member generally supports a portion having a large weight of the wafer. become. The arc 32 is widened at an angle of 180 degrees or less in order to facilitate the placement of the wafer. Typically, the support is arranged to define an arc 32 of about 150 degrees or less, typically about 130 degrees.

  Although three support members are shown in FIGS. 1 and 2, the wafer carrier may have a different number of support members. For example, the second support member may be bifurcated to form two different support members having different slot segments. In such a case, the bifurcated support member is spaced an equal distance from the lowest 6 o'clock position.

  As noted above, wafer carriers typically have an opening structure that provides several advantages that are described in detail below. Typically, the window defined between the cradle arm 3 and the support member provides an open area of at least 40% of the area along the partial cylindrical surface outside the cradle. Typically, the open area is about 50% or more. This wafer carrier opening structure advantageously improves the gas supply around the wafer carrier during the pre-oxidation step in order to conform and form a relatively uniform oxide layer.

  Next, as described above with respect to the material of the wafer carrier, the cradle is made of silicon carbide. According to one embodiment, silicon carbide comprises recrystallized silicon, a material understood in the art. Typically, a green body containing semiconductor silicon carbide powder is mixed with sintering aids and binders, molded into the desired shape, dried, and the organic binder is removed. Heated to burn out and heated to densify and recrystallize the green body. The following densification and machining steps are used to reach the final dimensions of the wafer carrier.

  Other silicon carbide configurations can be utilized in place of or in conjunction with recrystallized silicon carbide. For example, a silicon carbide substrate is formed by a conversion process in which a carbon preform is converted to silicon carbide by gas phase or liquid phase techniques. In this case, the carbon preform is typically composed of a carbonaceous material such as semiconductor-grade graphite. Furthermore, when using porous silicon carbide as the base material for the wafer carrier, the carrier is impregnated with silicon. Such hybrid structures are known as Si-SiC or siliconized silicon carbide. Here, in a relatively porous silicon carbide substrate configuration, the substrate is impregnated with dissolved silicon to densify the structure for suitable use in refractory applications such as in a semiconductor processing environment. . The siliconized silicon carbide is further covered by a layer of silicon carbide, such as chemical vapor deposition (CVD) silicon carbide.

  Further, the wafer carrier is made of free-standing SiC (free-standing SiC) formed by CVD. In this case, the extended CVD process is performed to configure the wafer carrier itself.

  The oxide layer is provided so as to cover the silicon carbide of the wafer carrier. The oxide layer is formed by oxidation performed in an oxidizing environment, such as carrier oxidation in an oxygen-containing environment at a high temperature in the range of about 950 ° C. to 1300 ° C., typically about 1000 ° C. to 1250 ° C. Oxidation is carried out in a dry or moist atmosphere, typically at atmospheric pressure. A moist atmosphere is generated by introducing steam and serves to increase the proportion of oxygen and improve the density of the oxide layer. Here, the wet oxidation at 1150 ° C. forms a strong and thick (about 2 to 3 micrometer) oxide layer between about 12 and 48 hours. On the other hand, according to the dry oxidation method, a layer is formed on the order of 5 days such as 10 to 20 days. Typically, the oxide layer is formed by oxidation and grown by reacting a TEOS source gas. However, thermally grown layers are preferred in terms of durability and strength.

In general, the oxide layer is silicon oxide, generally SiO ₂ . The silicon oxide layer is in direct contact with the silicon carbide of the wafer carrier. Conversely, in the case of silicon-impregnated silicon carbide, an intermediate layer such as silicon is present between the silicon carbide and the covering oxide layer.

  FIG. 3 is a graph showing an oxide growth curve varying with time on a silicon carbide wafer carrier. As shown, the oxide layer generally follows a radial growth curve. As will be described below, according to one embodiment of the present invention, the oxide layer has a thickness above the relatively fast growth of the curve. For example, the oxide layer has a thickness greater than about 0.75 micrometers, such as greater than about 0.5 micrometers, in particular, about 1.0 micrometers, or even greater than 1.5 micrometers. Have. According to a particular embodiment of the invention, the oxide has a thickness of at least 2 micrometers, on the order of about 2 micrometers to 3 micrometers. It should be noted that the oxide layer of one embodiment according to the present invention is a layer provided on the wafer carrier that is present on the wafer carrier but is opposed to the relatively thin native oxide. I must. In addition, the oxide layer described above is typically formed by a thermal oxidation technique in which the oxide layer is deposited directly, although other techniques can be utilized.

  Formation of an oxide layer by a thermal pre-oxidation step has been found to improve process control in a semiconductor manufacturing plant environment. In particular, the present invention relates to the oxidation that the wafer forms on the wafer and / or the wafer carrier during the traditional oxidation to form a relatively thick oxide layer on the wafer. It has been recognized that there is a tendency to bond to the wafer carrier through the growth of the material layer. It is believed that during subsequent cooling of the wafer and / or wafer carrier structure, differences in shrinkage due to differences in the coefficient of thermal expansion of the wafer and carrier cause thermally induced stress on the wafer. Such thermal expansion / contraction characteristics depend on synthetic and structural differences and will ultimately damage the wafer.

  In extreme cases, the wafer becomes fatally useless by the cracking mechanism. By incorporating a pre-oxidation step to form an oxide layer on the carrier, during the heat treatment of the wafer, the growth of the oxide layer on the carrier is weakened, and the tendency for bonding of the wafer to the wafer carrier is reduced, Thereby, process control and wafer yield are improved.

  According to another configuration of the invention, the slot of the wafer carrier has a special radius of curvature rs that further improves process control and wafer yield, especially in the high temperature processing described above.

  Referring to FIG. 2, the wafer has a nominal radius rw. Currently, semiconductor manufacturing plants utilize wafers that are 8 inches, as well as larger 12 inches (diameter 300 mm). Thus, a new semiconductor manufacturing plant may utilize a wafer having a radius on the order of about 150 mm, although it may utilize a previous smaller wafer or a new generation of a larger semiconductor manufacturing plant. According to one particular embodiment, the radius of curvature rs of the slot is greater than 1.15 times the radius rw of the wafer. In another state, the radius of curvature of the slot that supports the wafer is at least 15% greater than the radius of the wafer. Typically, the slot curvature rs is about 1.25 times or more, such as 1.35 times or 1.50 times the wafer radius rw. Referring to FIG. 4, the radius of curvature rs of the slot is approximately twice the radius rw of the wafer. Furthermore, the radius of curvature of the slot may approach a straight line (rs = infinity). This particular embodiment is depicted in FIG. In this case, the portion of the slot that contacts the wafer extends along a straight line.

  Furthermore, the radius of curvature of the slots may be opposite in direction, that is, has a negative radius of curvature compared to the radius rw of the wafer. This is shown in FIG. 6, where the slot generally has a convex shape and has a radius that extends from the point where the wafer and the slot contact to oppose the wafer in the radial direction.

  In the embodiment described above, it is not necessary for each slot segment to have the same radius of curvature. Typically, however, at least a portion of the second slot segment along the second support member has the radius feature described above.

  As described above, by providing a slot portion having a radius of curvature rs, the potential oxidation bond area between the wafer and the carrier is minimized. Thus, for the extension of the oxide bond formed between the wafer and the carrier, the minimized bond interface is fragile and, more preferably, cracks during processing (cooling process), as described above. It will weaken the thermal stress that can cause crushing.

  According to another embodiment of the invention, at least some of the slots of the wafer carrier have a width Ws that is greater than the wafer thickness tw. In particular, the slot width Ws is generally at least about 1.30 times the wafer thickness tw. According to another embodiment, the slot width Ws is greater than or equal to about 1.35 times the wafer thickness tw and is in the range of about 1.35 times to 1.50 times. Here, FIG. 7 depicts the slot width Ws associated with the wafer thickness tw (scale not shown). The actual thickness tw of the wafer will vary depending on the brand of the wafer, the intended use, the diameter of the wafer, the structure (eg, silicon on insulator (SOI)), etc. Typically, however, the wafer generally has a thickness in the range of about 0.45 mm to 0.80 mm, particularly in the range of 0.5 mm to 0.765 mm. By facing the narrow width, such as 1.10 times to 1.25 times the wafer thickness tw, by providing a slot with the above-described relative width, the structure of the relatively thick oxide layer is: Made easy by the extra perforation of the slot. In addition, the degree of wafers that are strongly constrained in the slots during oxide growth is reduced and wafer creep is almost free of problems. Here, using traditional techniques, the restriction of the wafer in the slot tends to cause the wafer to creep at high temperatures that cause notching. The structure of the notches around the outer periphery of the wafer tends to form a mechanical connection structure that is disadvantageous. In particular, when cooled, the notches become connected to the slots and respond to mechanical stresses on the wafer by cooling according to different thermal expansion characteristics between the wafer and the wafer carrier.

  Further, as noted above, for a particular configuration of the wafer carrier embodiment, the present invention also provides a method for processing a plurality of wafers, known as batch processing. Here, a plurality of wafers are mounted on the wafer carrier, and are generally arranged as a linear array at a constant pitch. The wafer / wafer carrier structure is then placed in a furnace such as a processing tube for high temperature processing. As noted above, one desired process implementation is a structural arrangement of relatively thick oxide layers on the wafer, particularly suitable for MEMS and optoelectronic applications.

  Although the embodiments of the present invention have been described above, it will be understood that various modifications can be made without departing from the technical idea of the claims of the present application.

1 is a perspective view of a horizontal wafer carrier according to an embodiment of the present invention. 1 is a cross-sectional view of a horizontal wafer carrier on which a silicon wafer is placed according to an embodiment of the present invention. FIG. 6 is a graph of an oxide growth curve on a silicon carbide wafer carrier. It is a figure which shows the curvature radius of the slot by which the semiconductor wafer which concerns on one Example of this invention was mounted. It is a figure which shows the curvature radius of the slot by which the semiconductor wafer which concerns on the other Example of this invention is mounted. It is a figure which shows the curvature radius of the slot by which the semiconductor wafer which concerns on the further another Example of this invention is mounted. FIG. 6 is a diagram illustrating the thickness of a wafer in a cross section mounted in a slot, related to the width of the slot, according to one embodiment of the invention.

Claims (34)

A wafer carrier for supporting a plurality of wafers,
With a plurality of slots provided in the cradle,
The cradle includes a silicon carbide and has an oxide layer covering the silicon carbide.   2. The wafer carrier according to claim 1, wherein the cradle includes recrystallized silicon carbide.   The wafer carrier according to claim 1, wherein the cradle includes silicon-impregnated silicon carbide.   The wafer carrier according to claim 1, wherein the cradle comprises convertible silicon carbide.   The wafer carrier according to claim 1, wherein the cradle includes self-standing CVD-SiC.   The wafer carrier according to claim 1, wherein the oxide layer comprises silicon oxide.   The wafer carrier of claim 6, wherein the oxide layer has a thickness of about 0.5 micrometers or more.   7. The wafer carrier according to claim 6, wherein the oxide layer has a thickness of about 0.75 micrometers or more.   The wafer carrier of claim 6, wherein the oxide layer has a thickness of about 1.0 micrometers or more.   7. The wafer carrier according to claim 6, wherein the oxide layer has a thickness of about 1.5 micrometers or more.   The wafer carrier according to claim 1, wherein the oxide layer is thermally grown.   The wafer carrier according to claim 1, wherein the oxide layer is deposited.   2. The wafer carrier according to claim 1, wherein the wafer carrier is a horizontal wafer carrier that normally supports the wafer so as to be lifted in a vertical position.   2. The wafer carrier according to claim 1, wherein the slots are arranged as a linear array and are spaced apart from each other by a constant pitch. A wafer carrier for supporting a plurality of wafers,
The wafer has a thickness tw;
The wafer carrier comprises a plurality of slots for supporting the array of wafers;
At least a part of each slot has a slot width Ws, and the slot width Ws is about 1.30 times or more the thickness tw of the wafer.   16. The wafer carrier according to claim 15, wherein the width Ws of the slot is about 1.35 times or more the thickness tw of the wafer.   16. The wafer carrier according to claim 15, wherein a width Ws of the slot is in a range of about 1.35 times to 1.50 times a thickness tw of the wafer. The wafer carrier according to claim 1,
The cradle includes at least first, second and third support members;
Each of the first, second and third support members is provided to support and contact the wafer;
Each slot has first, second, and third slot segments extending along the first, second, and third support members, respectively. The wafer carrier according to claim 18,
The first, second and third slot segments are disposed along an arc having a radius equal to the radius of the wafer; and
The first, second, and third support members are positioned along the arc so that the second support member is positioned between the first support member and the second support member. Wafer carrier, characterized in that   20. The wafer carrier according to claim 19, wherein a part of each slot has a width Ws of a slot including at least a part of the second slot segment.   20. The wafer carrier according to claim 19, wherein the first, second and third slot segments are maintained at a constant interval along the arc of 180 degrees or less.   20. The wafer carrier according to claim 19, wherein the first, second and third slot segments are kept at a constant interval along the arc of 150 degrees or less. A wafer carrier for supporting a plurality of wafers having a radius rw,
The wafer carrier includes a plurality of slots for supporting the plurality of wafers,
At least a part of each slot has a radius of curvature rs, and the curvature rs is about 1.15 times or more of the radius rw of the wafer.   24. The wafer carrier of claim 23, wherein the curvature rs is at least about 1.25 times the radius rw of the wafer.   24. The wafer carrier according to claim 23, wherein the curvature rs is about 1.35 times or more the radius rw of the wafer.   24. The wafer carrier according to claim 23, wherein the curvature rs is about 1.50 times or more the radius rw of the wafer.   24. The wafer carrier according to claim 23, wherein the curvature rs is infinite, and at least a part of each slot extends along a straight line. A wafer carrier for supporting a plurality of wafers having a radius rw,
The wafer carrier includes a plurality of slots for supporting the plurality of wafers,
At least a part of each slot has a radius of curvature rs, the curvature rs is a negative value, and the radius rw of the wafer is a positive value. Mounting a plurality of wafers in a wafer carrier, the wafer carrier including a plurality of slots provided in the cradle, the cradle comprising silicon carbide and an oxide covering the silicon carbide A step having a layer;
A method of processing a plurality of wafers, comprising: causing the wafers to be subjected to processing.   30. The method of claim 29, wherein performing the processing comprises exposing the wafer to an oxidizing environment to oxidize the wafer.   30. The method of claim 29, wherein the oxide layer is formed by oxidizing at a temperature higher than the temperature at which the process is performed. Mounting a plurality of wafers in a wafer carrier, the wafer having a radius rw, the wafer carrier comprising a plurality of slots for supporting the plurality of wafers, wherein at least one of the slots; The portion has a radius of curvature rs, the curvature rs being greater than or equal to about 1.15 times the radius rw of the wafer;
A method of processing a plurality of wafers, comprising: causing the wafers to be subjected to processing. Mounting a plurality of wafers in a wafer carrier, the wafer having a thickness tw, the wafer carrier comprising a plurality of slots for supporting the array of wafers, wherein at least each of the slots A portion has a width Ws of the slot, the width Ws of the slot being about 1.30 times greater than the thickness tw of the wafer;
A method of processing a plurality of wafers, comprising: causing the wafers to be subjected to processing. A wafer carrier for supporting a plurality of wafers,
The wafer has a thickness tw and a radius rw;
The wafer carrier comprises a plurality of slots for supporting the plurality of wafers;
At least a portion of each slot has a slot width Ws and a radius of curvature rs, the slot width Ws being greater than or equal to about 1.30 times the wafer thickness tw, and the curvature rs. Is at least about 1.15 times the radius rw of the wafer,
The wafer carrier further comprises silicon carbide and an oxide layer covering the silicon carbide.

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