KR20060001061A - Phase change ram device using pn diode - Google Patents

Abstract

The present invention discloses a phase change memory device using a PN diode which reduces the leakage current between neighboring phase change (GST) cells. A phase conversion memory device using a PN diode according to the present invention, the substrate comprising: a substrate; A PN diode formed by alternately forming first, second and third P-type regions and first, second and third N-type regions on the substrate surface; Bit line contacts formed to contact the left and right P-type regions and the N-type regions of the PN diode, respectively; A bit line configured to interconnect the bit line contacts; A storage node contact configured to simultaneously contact any P-type and N-type region of the PN diode; A lower electrode formed to contact the storage node contact; A GST film formed in contact with one side of the lower electrode; An upper electrode formed on the GST film to constitute a GST cell; And a PN diode comprising a metal wiring formed to contact the upper electrode, wherein the GST cells are different from each other in the position of the GST film by varying the length of the lower electrode between neighboring GST cells. It is characterized in that it is formed to be arranged in a zig-zag form as a whole.

Description

Phase change RAM device using PN diode

1A to 1C are diagrams for explaining a phase change memory device using a conventional PN diode.

2 is a plan view illustrating a phase change memory device using a PN diode according to an embodiment of the present invention.

3A and 3B are cross-sectional views taken along lines A-A 'and B-B' of FIG. 2;

4 is a plan view illustrating a phase change memory device using a PN diode according to another embodiment of the present invention.

5A and 5B are cross-sectional views taken along lines A-A 'and B-B' of FIG. 4.

Explanation of symbols on the main parts of the drawings

1: silicon wafer 2: investment oxide film

3: silicon layer 10: SOI substrate

11: first oxide film 12: bit line contact

13 bit line 14 second oxide film

15a, 15b: Storage node contacts 16a, 16b: Lower electrode

17: GST film 18: third oxide film                 

19: upper electrode 20: fourth oxide film

21: Metallization G1, G2: GST Cell

P1, P2, P3: P type region N1, N2, N3: N type region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory element, and more particularly, to a phase change memory element using a PN diode having reduced leakage current between neighboring cells.

Generally, a memory device is a volatile random access memory (RAM) device that loses input information when the power is cut off, and a ROM that keeps the input data stored even when the power is cut off. ) Are largely divided into elements. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM is a very good memory device as is well known, high charge storage capability is required for periodic refresh operation, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased. In addition, the flash memory device requires a higher operating voltage than a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.                         

Accordingly, many studies have been conducted to develop new memory devices having characteristics of non-volatile memory devices and simple structures. For example, a phase change RAM device is proposed. It became.

The phase change memory device uses a difference in resistance between crystalline and amorphous phases due to a phase change from the crystalline state to the amorphous state between the electrodes through the current flow between the lower electrode and the upper electrode. It is a storage element for determining the information stored in the.

In other words, the phase-conversion memory device uses a chalcogenide film as a phase-conversion film, which is a compound film composed of germanium (Ge), stevidium (Sb), and tellurium (Te). GST film), a phase change occurs between an amorphous state and a crystalline state by an applied current, that is, Joule heat, wherein the resistivity of the phase change film having an amorphous state is in a crystalline state. Since it is higher than the specific resistance of the phase change film having a value, the current flowing through the phase change film in the read mode is sensed to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

In addition, the conventional phase-change memory element uses a PN diode to form an amount of current of 1 mA or more necessary for causing a phase change of the GST film to occur.

1A to 1C are diagrams for describing a phase change memory device using a conventional PN diode. FIG. 1 is a plan view, FIG. 2 is a cross-sectional view taken along line AA ′ of FIG. 1, and FIG. It is a schematic diagram for explaining the operation.                         

1A and 1B, a phase-conversion memory device using a conventional PN diode includes a silicon on insulator (SOI) substrate 10 having a buried oxide film 2 and a silicon layer 3 stacked on a silicon wafer 1. Several P-type regions P1, P2, P3 and N-type regions N1, N2, N3 are alternately formed on the surface of the silicon layer 3 of the silicon layer 3 to form a PN diode, and the first P-type regions (left and right sides) A bit line contact 12 is formed to contact P1 and the third N-type region N3, respectively, and a bit line 13 is formed to interconnect the bit line contacts 12. A storage node contact 15 is formed in contact with the 3 P-type region P3 and the second N-type region N2 at the same time, and a lower electrode 16 is formed on the storage node contact 15. A GST film 17 is formed on the side of the lower electrode 16, and an upper electrode 19 is formed on the GST film 17 to form GST cells G1 and G2, and the upper electrode ( 19) on the upper part The upper electrode group 19 and the contacts make the metal wire 21 has a structure formed thereon.

In the phase change memory device using the PN diode, the GST film 17 is transferred from the amorphous state to the crystalline state by allowing a current to flow from the lower electrode 16 to the upper electrode 18 through the GST film 17. The change occurs to amplify the low and high according to the current during the read operation.

That is, as shown in FIG. 1C, in a write operation, a forward current flows from a node in a high state to a node b in a low state through the PN diode P1N1P2N2, thereby forming a lower electrode. (16) The phase change of the GST layer 17 in contact with the edge occurs, and in the read operation, the node "b" from the node "high" to the node "c" in the state "low" through the PN diode (P3N3). The current flow in the forward direction is formed, and at this time, the current intensity varies according to the degree to which the resistance is increased or decreased by the phase change of the GST film 17, thereby amplifying.

In FIGS. 1A to 1C, reference numeral 11 denotes a first oxide film, 14 a second oxide film, 18 a third oxide film, 20 a fourth oxide film, Rd a read operation PN diode, and Denotes a write operation PN diode, respectively.

However, the above-described phase change memory device using the PN diode has a structure in which the GST cells in which the GST film is disposed are formed in a line on the same vertical line, so that the interval between neighboring GST cells is small, and thus, the neighboring As the leakage current between the GST cells increases, the current flow between the lower electrode and the upper electrode is not concentrated, resulting in a decrease in operating characteristics.

On the other hand, in order to secure more current flow, the length of the diode must be reduced. In this case, the diode breakdown voltage in the reverse direction is lowered, and the sensing margin during the read operation is reduced.

Accordingly, an object of the present invention is to provide a phase conversion memory device using a PN diode which reduces leakage current between neighboring GST cells.

Another object of the present invention is to provide a phase conversion memory device using a PN diode in which operating characteristics are secured by reducing leakage current between neighboring GST cells.

In order to achieve the above object, the present invention, a substrate; A PN diode formed by alternately forming first, second, and third P-type regions and first, second, and third N-type regions on the substrate surface; Bit line contacts formed to contact the left and right P-type regions and the N-type regions of the PN diode, respectively; A bit line configured to interconnect the bit line contacts; A storage node contact configured to simultaneously contact any P-type and N-type region of the PN diode; A lower electrode formed to contact the storage node contact; A GST film formed in contact with one side of the lower electrode; An upper electrode formed on the GST film to constitute a GST cell; And a PN diode comprising a metal wiring formed to contact the upper electrode, wherein the GST cells are different from each other in the position of the GST film by varying the length of the lower electrode between neighboring GST cells. Accordingly, a phase change memory device using a PN diode is formed so as to be arranged in a zig-zag shape as a whole.

Here, the lower electrode is characterized in that the lower electrode of the odd or even row is formed to extend shorter than the lower electrode of the even or odd row, the GST film is the same side of the different lower electrode It is characterized in that it is formed in contact with.

In addition, the present invention, a substrate; A PN diode formed by alternately forming first, second, and third P-type regions and first, second, and third N-type regions on the substrate surface; Bit line contacts formed to contact the left and right P-type regions and the N-type regions of the PN diode, respectively; A bit line formed to interconnect the bit line contacts; A storage node contact configured to simultaneously contact any P-type and N-type region of the PN diode; A lower electrode formed to contact the storage node contact; A GST film formed in contact with one side of the lower electrode; An upper electrode formed on the GST film to constitute a GST cell; And a PN diode comprising a metal wiring formed to contact the upper electrode, wherein the storage node contact is to be contacted with an N-type region and a P-type region at different positions between neighboring GST cells. The present invention provides a phase conversion memory device using a PN diode, wherein the GST cells are arranged in a zig-zag form.

Herein, the storage node contacts are formed so that the storage node contacts in the odd or even row are in contact with the second N-type region and the third P-type region at the same time, and the storage node contacts in the even or odd row are in the first N region. And contact with the mold region and the second P-type region at the same time.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be briefly described. According to the present invention, unlike the conventional structure in which the GST cells in which the GST film is disposed are arranged side by side on the same vertical line, the ZST cells in which the GST film is disposed are zig-zag. -Zag). And, for this purpose, the present invention changes the shape of some lower electrodes, or changes the position of the storage node contact.

In this way, the spacing between neighboring GST cells in relation to the arrangement of the GST cells in a zigzag form becomes wider, so that the leakage current between neighboring GST cells is significantly reduced, so that the lower electrode and As the current flows between the upper electrodes is concentrated, the present invention improves the operating characteristics of the phase change memory device.

2, 3A, and 3B are diagrams for describing a phase change memory device using a PN diode according to an embodiment of the present invention. 2 is a plan view, FIG. 3A is a cross-sectional view taken along the line AA ′ of FIG. 2, and FIG. 3B is a cross-sectional view taken along the line BB ′ of FIG. 2. 2, 3A and 3B, the same parts as those in Figs. 1A and 1B are denoted by the same reference numerals.

First, the phase change memory device using the PN diode according to the present invention is formed on the surface of the silicon layer 3 of the SOI substrate 10 having a laminated structure of the silicon wafer 1, the buried oxide film 2, and the silicon layer 3. In order to form an arbitrary amount of current required for the phase change of the GST film, several structures of P-type regions (P1, P2, P3) and N-type regions (N1, N2, N3) are alternately formed to form a PN diode. In addition, a bit line contact 12 is formed to contact the first P-type region P1 and the third N-type region, respectively, and the bit line 13 to interconnect the bit line contacts 12. Is formed and a storage node contact 15 is formed to be in contact with the second N-type region N2 and the third P-type region P3 at the same time, and the lower electrode 16a to contact the storage node contact 15. , 16b is formed, and the GST film 17 is formed in a pattern form in contact with the side surfaces of the lower electrodes 16a and 16b. In addition, an upper electrode 19 is formed on the GST layer 17 to form GST cells G1 and G2, and a metal wiring contacting the upper electrodes 19 of the GST cells G1 and G2. 21) has a formed structure.

In the phase conversion memory device using the PN diode according to the exemplary embodiment of the present invention, the lower electrode 16b is patterned to a relatively larger size so that the GST cells G1 and G2 are arranged in a zigzag form. The GST film and the upper electrode are also formed to be disposed on the lower electrode portion extending.

That is, as shown, the lower electrodes 16a in the odd-numbered rows of the neighboring GST cells G1 and G2 are formed in the same manner as in the prior art, but the lower electrodes 16b in the even-numbered rows are formed in the odd-numbered rows. It is formed to have a relatively larger size than the lower electrode 16a and to be extended. In addition, since the GST film 17 is formed to be in contact with one side surface of the lower electrodes 16a and 16b, respectively, as a result, the GST cells G1 and G2 are not arranged on the same vertical line but are in a zigzag form. It is formed to be arranged.

In this case, with respect to the arrangement of the GST cells G1 and G2 in a zigzag arrangement, the spacing between neighboring GST cells G1 and G2 is increased than that of the conventional one, and thus, the neighboring GST cells G1 and G2. The leakage current between the lines is greatly reduced, which causes the current flow between the lower electrodes 16a and 16b and the upper electrode 19 to be concentrated, thereby improving the characteristics of the phase change memory device.

3A and 3B, reference numeral 11 denotes a first oxide film, 14 a second oxide film, 18 a third oxide film, and 20 a fourth oxide film, respectively.

4, 5A, and 5B are diagrams for describing a phase change memory device using a PN diode according to another exemplary embodiment of the present invention. 4 is a plan view, FIG. 5A is a cross-sectional view taken along the line AA ′ of FIG. 4, and FIG. 5B is a cross-sectional view taken along the line BB ′ of FIG. 4. 4, 5A and 5B, the same parts as in the previous embodiment are denoted by the same reference numerals.

According to this embodiment, the GST cells G1 and G2 are formed to be arranged in a zigzag form as in the previous embodiment, and for this purpose, the positions of some storage node contacts 15b are changed.

That is, as shown, in the neighboring GST cells G1 and G2, the storage node contact 15a of the odd-numbered row is the second N-type region N2 and the third P-type region P3 as in the prior art. Are simultaneously contacted with each other, but the storage node contacts 15b of the even-numbered rows are simultaneously contacted with the first N-type region N1 and the second P-type region. The stacked patterns of the lower electrode 16, the GST film 17, and the upper electrode 19 are formed on the storage node contacts 15a and 15b, so that the GST cells G1 and G2 are the same. It is not arranged on a vertical line but is arranged to be arranged in a zigzag form.

Therefore, the phase conversion memory device using the PN diode according to another embodiment of the present invention can also greatly reduce the leakage current between neighboring GST cells by widening the distance between neighboring GST cells than that of the conventional one, thus, Device characteristics can be improved.

As described above, the present invention can reduce the leakage current between the GST cells by increasing the interval between the neighboring GST cells by forming the GST cells arranged in a zigzag form, and thus, the lower electrode in the GST cells Since the current flow between the upper electrode and the upper electrode can be concentrated, the characteristics of the phase change memory device can be improved.

As mentioned above, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (5)

Board; A PN diode formed by alternately forming first, second, and third P-type regions and first, second, and third N-type regions on the substrate surface; Bit line contacts formed to contact the left and right P-type regions and the N-type regions of the PN diode, respectively; A bit line configured to interconnect the bit line contacts; A storage node contact configured to simultaneously contact any P-type and N-type region of the PN diode; A lower electrode formed to contact the storage node contact; A GST film formed in contact with one side of the lower electrode; An upper electrode formed on the GST film to constitute a GST cell; And a metal wiring formed to contact the upper electrode. The GST cells are formed to be arranged in a zig-zag form as a whole by changing the positions of the GST layers by different lengths of the lower electrodes between neighboring GST cells. Phase change memory device. 2. The phase change memory device as claimed in claim 1, wherein the lower electrode is formed such that the lower electrodes of odd or even rows are shorter than the lower electrodes of even or odd rows. The phase conversion memory device using a PN diode according to claim 1, wherein the GST film is formed to contact the same side surface of different lower electrodes. Board; A PN diode formed by alternately forming first, second, and third P-type regions and first, second, and third N-type regions on the substrate surface; Bit line contacts formed to contact the left and right P-type regions and the N-type regions of the PN diode, respectively; A bit line configured to interconnect the bit line contacts; A storage node contact configured to simultaneously contact any P-type and N-type region of the PN diode; A lower electrode formed to contact the storage node contact; A GST film formed in contact with one side of the lower electrode; An upper electrode formed on the GST film to constitute a GST cell; And a metal wiring formed to contact the upper electrode. The storage node contacts are formed to simultaneously contact N-type regions and P-type regions at different positions between neighboring GST cells, so that the GST cells are arranged in a zig-zag form as a whole. Phase change memory device using a diode. 5. The storage node contact as claimed in claim 4, wherein the storage node contacts are formed so that the storage node contacts in the odd or even row are in contact with the second N-type region and the third P-type region at the same time. Is a phase conversion memory device using a PN diode, characterized in that the first N-type region and the second P-type region to contact at the same time.

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