KR20070069763A - Phase change ram device - Google Patents

Abstract

A phase change RAM device is provided to enhance cell efficiency by changing a design of an active region and adjusting a position of a gate. An isolation layer(21) is formed within a semiconductor substrate(20) to define an active region(22) including two I-shaped patterns(22a) and +-shaped pattern(22b). A plurality of gates(23) are formed on the isolation layer including the active region and are arranged on the active region perpendicular to the I-shaped patterns and +-shaped pattern. A source region(24) is formed within the active region corresponding to one side of the gate. A drain region(25) is formed within the active region corresponding to the other side of the gate. A phase change cell is formed with a stack structure of a lower electrode, a phase change layer, and an upper electrode.

Description

Phase change memory device

1 is a plan view for explaining a conventional phase conversion memory element.

2A to 2C are plan views illustrating the phase change memory device according to the present invention.

3 and 4 are diagrams for explaining an interval between a source terminal and a drain terminal and an interval between the drain terminals in the phase conversion memory device according to the present invention;

Explanation of symbols on the main parts of the drawings

20 semiconductor substrate 21 device isolation film

22: active area 22a: I-shaped pattern

22b: + pattern 23: gate

24 source region 25 drain region

30: unit cell

The present invention relates to a phase change memory device, and more particularly, to a phase change memory device having improved cell efficiency.

The memory device is a volatile random access memory (RAM) device that loses input information when the power supply is cut off, and a read only memory (ROM) device that maintains the storage state of the input information even when the power supply is turned off. It is largely divided. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM has a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased. In addition, the flash memory device requires a high operating voltage compared to a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies are being conducted to develop a new memory device having a characteristic of the nonvolatile memory device and having a simple structure, and as an example, a phase change memory device (Phase Change RAM) Was proposed.

The phase change memory device utilizes a difference in resistance between crystalline and amorphous phases due to the phase change of the phase conversion film interposed between the electrodes from the crystal state to the amorphous state through the current flow between the lower electrode and the upper electrode. It is a storage element for determining stored information. In other words, the phase conversion memory device uses a chalcogenide film as a phase conversion film, and the chalcogenide film is a compound film made of germanium (Ge), stevidium (Sb), and tellurium (Te). A phase change occurs between the amorphous state and the crystalline state due to the applied current, that is, the joule heat, from which the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. In the read mode, the current flowing through the phase change layer is sensed to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

On the other hand, such a phase-change memory element requires a current flow of 1 mA or more for stable phase change of the phase-conversion film. Therefore, the conventional phase change memory device, unlike the conventional semiconductor device, forms a wide width of the transistor, and adopts an open bit line structure.

1 is a plan view illustrating a conventional phase change memory device. As shown in FIG. 1, the active region 12 is defined by the device isolation film 11 in the semiconductor substrate 10, and the device isolation film ( The gate 13 is formed on the active region 12 including 11, and the source region 14 and the drain region 15 are formed in the substrate active regions on both sides of the gate 13. Here, the active region 12 is long in the width direction of the gate 13, unlike in a conventional semiconductor device, in order to obtain a high current flow.

Although not shown, the phase conversion cell including the lower electrode, the phase conversion film, and the upper electrode is formed to be connected to the drain terminal contacting the drain region, and a ground voltage is applied to the source region through the source terminal.

However, in the conventional phase change memory device as described above, the width of the transistor, i.e., the width of the active region, must be made long in connection with requiring high current flow, so that the cell efficiency is not good. However, there is a limit to achieving high integration.

Accordingly, an object of the present invention is to provide a phase change memory device having improved cell efficiency.

In order to achieve the above object, the present invention, a semiconductor substrate; A portion formed in the semiconductor substrate and having a gate and a source / drain region on which a transistor is to be formed is composed of two I-shaped patterns having a larger width than a portion where only a source region is to be formed and a + -shaped pattern disposed therebetween. An isolation layer defining an active region to be formed; A plurality of gates formed on the device isolation layer including the active region and disposed on both sides of an active region portion perpendicular to the I-shaped pattern and the + -shaped pattern, respectively; A source region integrally formed in the substrate active region on one side of the gate; A drain region separated from each other in the substrate active region on the other side of the gate; And a phase conversion cell formed of a stacked structure of a lower electrode, a phase conversion film, and an upper electrode formed to contact the drain region.

The gate may be formed on both the active region and the device isolation layer adjacent thereto.

In the phase change memory device of the present invention, the spacing between the active region portion where the source region is to be formed and the active region portion where the drain region is to be formed is equal to the spacing between the active regions where the drain region is to be formed, or the source region is The interval between the active region to be formed and the active region where the drain region is to be formed is smaller than the interval between the active regions where the drain region is to be formed, or the interval between the active region where the source region is to be formed and the active region where the drain region is to be formed is a drain region. It is wider than the gap between active regions to be formed.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be described. In the present invention, the device isolation layer is formed in a form in which an active region is defined in a gate width direction in a shared bit line structure rather than an open bit line structure. Form.

In particular, the active region is connected in the gate width direction by two gate units, and the drain region portion in which the phase change film and the upper electrode are formed is separated from the neighboring drain region portion, while the ground voltage is applied. In the case of the source region to be connected, all of them are connected, that is, integrally formed. At this time, both the integrated source region and the separated drain region are formed through an ion implantation process of n-type impurities.

2A to 2C are plan views illustrating the phase change memory device according to the present invention.

FIG. 2A is a plan view illustrating a device isolation film and an active region defined by the phase change memory device according to the present invention. As shown in FIG. 2A, a device isolation film 21 is formed in a semiconductor substrate 20 to form an active region ( 22 is limited. In the device isolation layer 21, two I-shaped patterns 22a having a larger width than a portion where a source region in which a transistor including a gate and a source / drain region are to be formed are formed. ) And a + -shaped pattern 22b disposed therebetween.

FIG. 2B is a plan view illustrating a state in which a gate is formed on an active region including an isolation layer, and as illustrated, the gate 23 is a vertical active region in the I-shaped pattern 20a and the + -shaped pattern 20b. The gate 23 is formed to be disposed on each of both sides of the portion, and the gate 23 is disposed on both the active region 22 and the portion of the isolation layer adjacent thereto.

FIG. 2C is a plan view showing a source region and a drain region formed in the substrate active regions on both sides of the gate. As illustrated, a source region 24 is formed in the substrate active region on one side of the gate 23. The drain region 25 is formed in the substrate active region on the other side of the gate 23.

Here, the source region 24 is formed integrally, while the drain region 25 is formed in a separate form. In other words, the portion to which the ground voltage is applied, that is, the source terminal is formed integrally in communication with the gate 23 direction, while the portion contacting the phase change film, that is, the drain terminal is separated from each other. Is formed. At this time, both the source region 24 and the drain region 25 are formed through an ion implantation process of n-type impurities.

Although not shown, a phase change cell having a stacked structure of a lower electrode, a phase change film, and an upper electrode is formed on each drain region 25 formed separately.

In Fig. 2C, reference numeral 30 denotes a unit cell composed of one transistor 1T and one variable resistor 1R.

Meanwhile, in the above-described phase change memory device of the present invention, the active region in which the source region is to be formed and the active region in which the drain region is to be formed are, as shown in FIG. 2A, the active region and the drain region in which the source region is to be formed. The spacing a between the active regions to be formed is preferably equal to the spacing b between the active regions where the drain region is to be formed. If necessary, as shown in FIG. 3, the active region where the source region is to be formed is formed. The spacing a between the active region where the region and the drain region are to be formed may be formed to have a narrower spacing than the spacing b between the active regions where the drain region is to be formed. Conversely, as shown in FIG. The gap a between the active region to be formed and the active region where the drain region is to be formed may be formed to have a wider interval than the gap b between the active regions where the drain region is to be formed.

According to the phase change memory device of the present invention as described above, since the cell is configured with a separate bit line structure by changing the design of the active region, the width of the active region is increased so that the high current flow required for the phase change of the phase conversion film can be obtained. It is possible to integrate more unit cells in a limited area while obtaining one. Therefore, the present invention can integrate more unit cells for the same area, thereby improving cell efficiency.

As described above, the present invention can increase the cell efficiency by changing the design of the active region and adjusting the position of the gate, thereby implementing a highly integrated phase change memory device.

Hereinbefore, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and those skilled in the art to which the present invention pertains have many modifications and variations without departing from the spirit of the present invention. It will be appreciated that it can be added.

Claims (5)

Semiconductor substrates; A portion formed in the semiconductor substrate and having a gate and a source / drain region on which a transistor is to be formed is composed of two I-shaped patterns having a larger width than a portion where only a source region is to be formed and a + -shaped pattern disposed therebetween. An isolation layer defining an active region to be formed; A plurality of gates formed on the device isolation layer including the active region and disposed on both sides of an active region portion perpendicular to the I-shaped pattern and the + -shaped pattern, respectively; A source region integrally formed in the substrate active region on one side of the gate; A drain region separated from each other in the substrate active region on the other side of the gate; And A phase conversion cell formed of a stacked structure of a lower electrode, a phase change film, and an upper electrode formed to contact the drain region; Phase change memory device comprising a. The method of claim 1, And the gate is formed on both the active region and the device isolation layer adjacent thereto. The method of claim 1, And an interval between an active region portion in which the source region is to be formed and an active region portion in which a drain region is to be formed is equal to the interval between active regions where a drain region is to be formed. The method of claim 1, And an interval between the active region where the source region is to be formed and the active region where the drain region is to be formed is smaller than the interval between the active regions where the drain region is to be formed. The method of claim 1, And an interval between the active region where the source region is to be formed and the active region where the drain region is to be formed is wider than the interval between the active regions where the drain region is to be formed.

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