KR20070069765A - Phase change ram device - Google Patents

Abstract

A phase change memory device is provided to enlarge an interval between metal pads by forming an active region in an S-shape. An isolation film(21) is formed on a semiconductor substrate(20) to define an S-shaped active region(22). Two gates(23) are disposed in the active region comprising the isolation film. A source region(24) is formed in the active region outside each gate, and a drain region(25) is formed in the active region between the gates. A first contact plug(26) is formed on the source region, and a second contact plug(27) is formed on the drain region. Metal pads(28a) are formed on the first and second contact plugs in the same size. A phase change cell(31) is formed on the second contact plug, and has a lower electrode and an upper electrode(30).

Description

Phase change memory device

1 is a cross-sectional view illustrating a conventional phase change memory device.

2A to 2F are plan views illustrating the phase change memory device according to the present invention.

Explanation of symbols on the main parts of the drawings

20 semiconductor substrate 21 device isolation film

22: active area 23: gate

24 source region 25 drain region

26: first contact plug 27: second contact plug

28a, 28b: metal pad 29: lower electrode

30: upper electrode 31: phase change cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory element, and more particularly, to a phase change memory element in which the shape of the active region is changed to stabilize the manufacturing process.

The memory device is a volatile random access memory (RAM) device that loses input information when the power supply is cut off, and a read only memory (ROM) device that maintains the storage state of the input information even when the power supply is turned off. It is largely divided. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM has a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased. In addition, the flash memory device requires a high operating voltage compared to a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies are being conducted to develop a new memory device having a characteristic of the nonvolatile memory device and having a simple structure, and as an example, a phase change memory device (Phase Change RAM) Was proposed.

The phase change memory device utilizes a difference in resistance between crystalline and amorphous phases due to the phase change of the phase conversion film interposed between the electrodes from the crystal state to the amorphous state through the current flow between the lower electrode and the upper electrode. It is a storage element for determining stored information. In other words, the phase conversion memory device uses a chalcogenide film as a phase conversion film, and the chalcogenide film is a compound film made of germanium (Ge), stevidium (Sb), and tellurium (Te). A phase change occurs between the amorphous state and the crystalline state due to the applied current, that is, the joule heat, from which the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. In the read mode, the current flowing through the phase change layer is sensed to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

1 is a cross-sectional view illustrating a conventional phase change memory device, which will be described below.

Gates 3 are formed on an active region of the semiconductor substrate 1 defined by an isolation layer (not shown), and source / drain regions 4a and 4b are formed in the substrate surface on both sides of the gate 3. Formed. The first insulating film 5 is formed on the entire surface of the substrate to cover the gates 3, and a region to which a power supply voltage is applied (hereinafter, referred to as a "Vss line") is formed. Contact plugs 6a and 6b are formed in portions of the first insulating layer in the region where the phase change cell is to be formed.

The second insulating film 7 is formed on the first insulating film 5 including the contact plugs 6a and 6b, and the first insulating film portion of the region where the phase change cell is to be formed by a damascene process. A metal pad 8 having a dot shape is formed in the inside, and a power supply voltage line 9 is formed in the first insulating film portion of the region to which the power supply voltage is to be applied.

Subsequently, a third insulating film 10 is formed on the second insulating film 7 including the metal pad 8 and the power supply voltage line 9, and in the third insulating film portion of the region where the phase change cell is to be formed. The lower electrode 11 having a plug shape is formed to contact the metal pad 8, and the phase conversion film 12 and the upper electrode 13 are formed on the lower electrode 11 and the portion of the third insulating layer adjacent thereto. ) Are stacked one by one, and as a result, a phase change cell 14 including a plug type lower electrode 11, a phase change film 12, and an upper electrode 13 is formed.

The fourth insulating layer 15 is formed on the third insulating layer 10 to cover the phase change cell 14, and the plug 16 is in contact with the upper electrode in the fourth insulating layer 15. The bit line 17 is formed on the fourth insulating film 15 including the plug 16.

A conventional phase change memory device having such a structure is sensed by a current flow from a power supply voltage line to a bit line through a transistor according to the state of the phase change film.

However, the above-described conventional phase change memory device cannot enlarge the space of the metal pad formed on the first contact plug because the active region has an I-shape, and thus the adjacent metal pads There is a high possibility of bridge between the two, and also, there is a problem that the phase change film and the upper electrode formed larger than the metal pad also have a high possibility of bridging with the neighboring phase change film and the upper electrode.

In addition, since the size of the metal pad formed by the damascene process is not constant, the difficulty of the exposure process and the degree of etching during the etching process may be different, resulting in excessive etching of the lower insulating layer.

Accordingly, an aspect of the present invention is to provide a phase change memory device which prevents generation of bridges between neighboring metal pads and bridges between neighboring phase change films and upper electrodes. The purpose is.

Another object of the present invention is to provide a phase change memory device capable of stabilizing a manufacturing process.

In order to achieve the above object, the present invention, a semiconductor substrate; An isolation layer formed in the semiconductor substrate such that an active region is defined by an S-shaped array; A gate formed such that two are disposed on an active region including the device isolation layer; Source regions formed in portions of the substrate active regions outside the gates and drain regions formed in portions of the substrate active regions between the gates; A first contact plug formed on the source region and a second contact plug formed on the drain region; Metal pads each having the same size on the first contact plug and the second contact plug; And a phase conversion cell formed on the second contact plug and having a stack structure of a plug type lower electrode and a phase conversion film and an upper electrode sequentially disposed on the lower electrode.

Here, the first contact plug and the second contact plug are formed in a bar type.

The metal pad is formed to be disposed on an intermediate portion of the first contact plug and the second contact plug.

The phase change cells are arranged in a zigzag form.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be described. In the present invention, in forming an isolation layer defining an active region, the active region is limited to an S-shaped array instead of the conventional I-shape.

In this case, the present invention can increase the distance between the metal pads formed on the contact plug. In addition, the transistor width should be about 1 μm in relation to the writing current required for the phase change being about 1 μm. When the active region is limited to an S shape as in the present invention, the drain end of the transistor That is, it is possible to form a metal pad in the middle portion of the contact plug of the node connected to the phase-change cell to concentrate the current flow, so that a write current of about 1 mA can be easily obtained.

In addition, in the case of defining the active region in an S-shape, since the phase change film and the upper electrode are arranged in a zigzag form, the burden on the distance between neighboring phase change films and the upper electrodes can also be lessened. The invention can effectively prevent the generation of bridges between adjacent metal pads, as well as between phase change layers and upper electrodes.

In addition, in the case where the active region is defined to have an S shape, the present invention can form the metal pads at the drain and source ends of the transistors in the same size, thereby providing a stable exposure process for the metal pads formed by the damascene process. In the etching process, the etching rate of the lower insulating film may be the same, and thus, the manufacturing process may be stabilized.

2A to 2F are plan views illustrating the phase change memory device according to the present invention.

First, FIG. 2A is a plan view illustrating an active region in a phase change memory device according to an exemplary embodiment of the present invention. As shown in FIG. 2A, an isolation region 21 is formed in a semiconductor substrate 20 to define an active region 22. The isolation layer 21 is formed such that the active region 22 has an S-shape and is continuously arranged. In this case, the active region 22 is limited so that the interval between the active regions 22 in the gate direction and the active regions 22 in the direction perpendicular to the gate direction are the same in order to efficiently unit cell size. do.

Next, FIG. 2B is a plan view illustrating a state in which gate and source / drain regions are formed on an active region including an isolation layer. As illustrated, two gates 23 may be formed on one active region 22. In this case, the gate 23 is formed of a first portion (a) and a first node (a) forming a metal pad so that a power voltage is applied subsequently, and a metal pad not being formed. The two portions (b) and the third portion (c) in which the phase change film and the upper electrode are formed are formed to be different from each other. A drain region 25 is formed in the substrate active region between the gates 23, and a source region 24 is formed in the remaining active region portion, that is, the active region portion outside the gate 23.

Subsequently, FIG. 2C is a plan view showing a state in which contact plugs are formed on the source and drain regions, and as shown in FIG. Two contact plugs 27 are formed. In this case, in order to make the phase conversion memory device have a high current of about 1 mA, the transistor width must be increased. To this end, the present invention uses each of the first contact plug 26 and the second contact plug 27. It is formed as a bar type (Bar type) rather than the hole type (hole type) of.

Next, FIG. 2D is a plan view showing a state in which a metal pad is formed, and as shown in FIG. 2D, the first contact plug 26 and the second contact plug formed on the source region 24 and the drain region 25, respectively. 27, metal pads 28a and 28b are formed respectively. In this case, the metal pads 28a and 28b, in particular, the metal pads 28b on the drain region 25 are preferably formed in the middle portion of the second contact plug 27 so as to concentrate the current flow. .

Here, the present invention can form the metal pads (28a, 28b) of the same size, accordingly, it is possible to proceed a stable exposure process when forming the metal pads (28a, 28b), in particular, in the damascene process The etching degree of the lower insulating film may be stably controlled when the insulating film is etched to limit the region where the metal pad of the metal pad is to be formed. In addition, the present invention allows sufficient space between neighboring metal pads 28a and 28b by allowing the active region to have an S-shape, so that the bridge between neighboring metal pads 28a and 28b is sufficient. Process margins can be increased, for example to effectively prevent occurrence.

Next, FIG. 2E is a plan view showing a state in which the lower electrode is formed on the metal pad, and as shown, the lower electrode 29 of the phase change cell is formed on the metal pad 28b at the drain end. In this case, the lower electrode 29 is formed in the form of a plug, the size is 100nm or less, preferably to have a size of 50 ~ 100nm.

FIG. 2F is a plan view illustrating a state in which phase change cells are configured. As shown in FIG. 2, a phase change film (not shown) and an upper electrode 30 are sequentially formed on each lower electrode. The phase change cell 31 which consists of a laminated structure of the conversion film and the upper electrode 30 is comprised. Here, the phase change cell 31 according to the present invention is disposed in a zig-zag shape as a whole, so that the gap between phase change cells can be sufficiently secured, and in particular, the metal pad of the drain stage. Since 28b is disposed in the middle portion of the second contact plug 27, it is possible to concentrate the current flow from the source terminal to the drain terminal.

As described above, the present invention can keep the spacing between the metal pads wide by changing the shape of the active region from the conventional I-shape to the S-shape, thereby increasing the process margin and increasing the metal The pads can be formed in the same size, so that the exposure process and the etching process can be stabilized.

As described above, the present invention can increase the spacing between the metal pads by changing the shape of the active region from the conventional I shape to the S shape, as well as the size of the metal pads as a whole. Margin of a subsequent exposure process and an etching process can be ensured, and stabilization of a manufacturing process can be aimed at by this.

Hereinbefore, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and those skilled in the art to which the present invention pertains have many modifications and variations without departing from the spirit of the present invention. It will be appreciated that it can be added.

Claims (4)

Semiconductor substrates; An isolation layer formed in the semiconductor substrate such that an active region is defined by an S-shaped array; A gate formed such that two are disposed on an active region including the device isolation layer; Source regions formed in portions of the substrate active regions outside the gates and drain regions formed in portions of the substrate active regions between the gates; A first contact plug formed on the source region and a second contact plug formed on the drain region; Metal pads each having the same size on the first contact plug and the second contact plug; And A phase conversion cell formed on the second contact plug and having a stack structure of a phase conversion film and an upper electrode sequentially disposed on the lower electrode in a plug shape and the lower electrode; Phase change memory device comprising a. The method of claim 1, And the first contact plug and the second contact plug are formed in a bar type. The method of claim 1, And the metal pad is formed to be disposed on an intermediate portion of the first contact plug and the second contact plug. The method of claim 1, And the phase change cell is arranged in a zigzag form.

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