KR20070069766A - Phase change ram device - Google Patents

Abstract

A phase change memory device is provided to increase the number of contacts of a source terminal more than that of a drain terminal by forming an active region in a diamond shape. An isolation film is formed on a semiconductor substrate(20) to define a diamond-shaped active region(22). Two gates(23) are disposed in the active region comprising the isolation film. A source region(24) is formed in the active region between the gates, and a drain region(25) is formed in the active region outside each gate. Plural first contact plugs are arranged in row on the source region, and plural second contact plugs are arranged in row on the drain region. A first bar-type metal pad(28) is in contact with the first contact plugs, and second bar-type metal pad(29) is in contact with the second contact plug. A phase change cell(31) is formed on the second contact plug, and has a lower electrode and an upper electrode(31). A third contact plug is formed on the phase change upper electrode, and a metal wiring(32) is in contact with the third contact plug.

Description

Phase change memory device

1A to 1D are plan views illustrating a conventional phase change memory device.

2A to 2F are plan views illustrating a phase change memory device according to an embodiment of the present invention.

3 is a plan view for explaining a phase change memory device according to another embodiment of the present invention;

Explanation of symbols on the main parts of the drawings

20 semiconductor substrate 21 device isolation film

22: active area 23: gate

24 source region 25 drain region

26,26a: first contact plug 27,27a: second contact plug

28: first metal pad 29: second metal pad

30: lower electrode 31: upper electrode

32: metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase change memory element, and more particularly, to a phase change memory element in which the amount of current is greatly increased by changing the shape of the active region.

The memory device is a volatile random access memory (RAM) device that loses input information when the power supply is cut off, and a read only memory (ROM) device that maintains the storage state of the input information even when the power supply is turned off. It is largely divided. The volatile RAM devices may include DRAM and SRAM, and the nonvolatile ROM devices may include flash memory devices such as EEPROM (Elecrtically Erasable and Programmable ROM). have.

However, although the DRAM has a very good memory device as is well known, high charge storage capability is required, and for this purpose, it is difficult to achieve high integration since the electrode surface area must be increased.

In addition, the flash memory device requires a high operating voltage compared to a power supply voltage in connection with a structure in which two gates are stacked, and thus requires a separate boost circuit to form a voltage required for write and erase operations. Therefore, there is a difficulty in high integration.

Accordingly, many studies are being conducted to develop a new memory device having a characteristic of the nonvolatile memory device and having a simple structure, and as an example, a phase change memory device (Phase Change RAM) Was proposed.

The phase change memory device utilizes a difference in resistance between crystalline and amorphous phases due to the phase change of the phase conversion film interposed between the electrodes from the crystal state to the amorphous state through the current flow between the lower electrode and the upper electrode. It is a storage element for determining stored information. In other words, the phase conversion memory device uses a chalcogenide film as a phase conversion film. The chalcogenide film is a compound film made of germanium (Ge), stevidium (Sb), and tellurium (Te). A phase change occurs between the amorphous state and the crystalline state due to the applied current, that is, the joule heat, from which the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. In the read mode, the current flowing through the phase change layer is sensed to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

Hereinafter, a conventional phase change memory device will be briefly described with reference to FIGS. 1A to 1D.

FIG. 1A is a plan view showing a state where a contact plug is formed, and as shown, gates 3 are formed on an active region 3 of a semiconductor substrate 1 defined by an isolation layer 2, Source / drain regions 5a and 5b are formed in the substrate surface on both sides of the gate 4. On the source region 5a and the drain region 5b, several first and second contact plugs 6a and 6b are formed in hole types, respectively.

FIG. 1B is a plan view showing a state where a metal pad is formed. As shown in the drawing, the upper portion of the source region 5a and the upper portion of the drain region 5b may be in contact with the contact plugs 6a and 6b formed at each region. Bar type metal pads 7a and 7b are formed.

FIG. 1C is a plan view illustrating a state in which a lower electrode is formed, and as shown, a plug-type lower electrode 8 is formed on a metal pad 7b of a drain region 5b in which a phase change cell is to be formed. .

FIG. 1D is a plan view illustrating a state in which a phase change cell and a metal wiring are formed, and as illustrated, a phase change film (not shown) and an upper electrode 9 are sequentially formed on each lower electrode in a pattern form. As a result, a phase change cell including a plug type lower electrode and a phase change film and an upper electrode 9 formed thereon in turn is constituted. In addition, a metal wiring 10 corresponding to the bit line is formed to include the third contact plug (not shown) to contact the upper electrodes 9 of each phase conversion cell.

The conventional phase change memory device having such a structure requires a large amount of current to change the phase of the phase change film, so that the transistor width is large. Here, there will be many factors that affect the amount of current in the transistor, but in particular, the contact resistance of the source terminal greatly affects. For example, when the widths of the transistors are the same, the smaller the resistance of the source terminal, the larger the amount of current.

However, in the conventional phase change memory device described above, since the active region has a rectangular shape, that is, a shape in which the width direction is long, the contact resistance of the source terminal and the contact resistance of the drain terminal have to be the same. Therefore, the effect of lowering the contact resistance of the source terminal relatively lower than that of the drain terminal is not obtained at all. Therefore, the structure of the conventional phase conversion memory device has difficulty in increasing the amount of current required for the phase change of the phase conversion film. have.

Accordingly, an object of the present invention is to provide a phase change memory device capable of reducing the contact resistance of a source terminal relatively lower than that of a drain terminal.

Another object of the present invention is to provide a phase change memory device capable of effectively increasing the amount of current required for the phase change of the phase change film by lowering the contact resistance of the source end than that of the drain end.

In order to achieve the above object, the present invention, a semiconductor substrate; An isolation layer formed in the semiconductor substrate to define an active region having a rhombus shape; A gate formed such that two are disposed on an active region including the device isolation layer; A source region formed in an active region portion between the gates and a drain region formed in an active region portion outside each gate; A plurality of first contact plugs formed in a row on the source region and several second contact plugs formed in a row on the drain region along the gate direction; A bar type first metal pad formed to contact the first contact plugs on the source region and a bar type second metal pad formed to contact the second contact plugs on the drain region; A phase conversion cell formed on the second metal pad and formed of a stacked structure of a lower electrode, a phase conversion film, and an upper electrode; A third contact plug formed on the phase change upper electrode; And a metal wiring formed to contact the third contact plug.

Here, the number of the first contact plugs is greater than that of the second contact plugs.

The lower electrode is formed in a plug shape and is formed to be disposed on an intermediate portion of the second metal pad.

The upper electrode including the phase change layer is formed to overlap the lower electrode and the gate.

In addition, in order to achieve the above object, the present invention, a semiconductor substrate; An isolation layer formed in the semiconductor substrate to define an active region having a rhombus shape; A gate formed such that two are disposed on an active region including the device isolation layer; A source region formed in an active region portion between the gates and a drain region formed in an active region portion outside each gate; A first contact plug formed in a bar type on the source region along the gate direction and a second contact plug formed in a bar type on the drain region; A first metal pad formed on the first contact plug and a second metal pad formed on the drain region; A phase conversion cell formed on the second metal pad and formed of a stacked structure of a lower electrode, a phase conversion film, and an upper electrode; A third contact plug formed on the phase change upper electrode; And a metal wiring formed to contact the third contact plug.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention will be described. In the present invention, in forming an isolation layer for defining an active region, the active region is formed to have a diamond shape instead of a conventional rectangular shape.

In this case, the phase change memory device of the present invention increases the contact width of the source terminal corresponding to the region where the phase change cell is not formed while increasing the transistor width, and the contact number at the drain terminal corresponding to the region where the phase change cell is formed. In this case, the contact resistance of the source can be made relatively lower than the contact resistance of the drain terminal, and as a result, the amount of current of the transistor required for the phase change of the phase conversion film can be increased.

In particular, in the case where the active region is limited to a rhombus shape as in the present invention, assuming that the width of the active region is the same as before, the same amount of current can be ensured even if the size of the active region is reduced, so that the unit cell size is reduced. As a result, the cell efficiency can be increased, and the size of the active region is the same as in the prior art, and the width of the transistor is increased, so that the current amount can be equalized even when the operating voltage is relatively low.

2A to 2F are plan views illustrating the phase change memory device according to the present invention.

First, FIG. 2A is a plan view illustrating a state in which a transistor is formed, and as shown, an isolation layer 21 is formed in a semiconductor substrate 20 to define an active region 22. In this case, the active region 22 is defined. ) Is defined to have a rhombus shape rather than a conventional rectangular shape. Several gates 23 are formed on the rhombic active region 22 including the device isolation layer 21 so as to be disposed two.

The source region 24 and the drain region 25 are formed on the surface of the substrate active region 22 on both sides of the gate 23. More specifically, the source region 24 is a region where no phase change cell is formed, and is formed in a portion of the substrate active region between the gates 23, and the drain region 25 is a region where the phase change cell is to be formed. As shown in FIG. 3, the substrates are formed in portions of the substrate active region outside the gates 23. At this time, since the active region 22 has a rhombus shape, the source region 24 has a larger size than the drain region 25.

Next, FIG. 2B is a plan view illustrating a state in which contact plugs are formed, and as illustrated, several first contact plugs 26 and several second contacts on the source region 24 and the drain region 25, respectively. The contact plug 27 is formed. At this time, since the active region 22 has a rhombus shape, the number of first contact plugs 26 formed in the source region 24 is larger than that of the second contact plugs 27 formed in the drain region 25. Is formed. Accordingly, the phase change memory device of the present invention can relatively lower the contact resistance in the source region 24 because the number of contacts in the source region 24 is larger than the number of contacts in the drain region 25. Thus, the amount of current in the transistor can be effectively increased.

2C is a plan view illustrating a metal pad formed therein, and as illustrated, the first contact plugs 26 formed on the source region 24 and the second contact plugs formed on the drain region 25 (FIG. 2C). The bar type metal pads 28 and 29 are formed to contact the 27. In this case, the number of the first contact plugs 26 formed on the source region 24 is greater than the number of the second contact plugs 27 formed on the drain region 25. ) And the first metal pad 28 formed to contact the second metal pad 28 has a larger size than the second metal pad 29 formed to contact the second contact plugs 27.

Next, FIG. 2D is a plan view showing a state in which a lower electrode is formed, and as shown, a lower electrode 30 is formed on the second metal pad 29 on the drain region 25 where the phase change cell is to be formed. . In this case, the lower electrode 30 is formed in a plug shape, the size of which is 100 nm or less, preferably 50 to 100 nm. In addition, the lower electrode 30 is formed to be disposed in the middle portion of the bar type second metal pad 29 so as to concentrate current.

FIG. 2E is a plan view showing a state in which phase change cells are configured. As shown in FIG. 2, a phase change film (not shown) and an upper electrode 31 are sequentially formed on each lower electrode, and thus, at each drain terminal. The phase change cell 31 which consists of a laminated structure of the lower electrode, the phase conversion film, and the upper electrode 31 is comprised.

FIG. 2F is a plan view showing a state in which metal wirings are formed, and as shown in FIG. 2F, the metal wirings 32 corresponding to the bit lines are connected to the upper electrodes of the phase change cells 31 formed at the respective drain ends thereof. It is formed in the direction perpendicular to).

As described above, according to the present invention, by limiting the active region to a rhombus shape, the contact resistance of the source terminal can be lower than that of the drain terminal, so that the current required for the phase change of the phase conversion film can be effectively increased.

Meanwhile, in the above-described embodiment of the present invention, although the contact plugs formed on the source region and the drain region are formed in the hole type, as illustrated in FIG. 3, the source plug 24 on the source region 24 and the drain region 25 is formed. It is also possible to form the contact plugs 26a and 27a in a bar type.

In this case, although there are disadvantages in that seams are generated in relation to the use of tungsten as the contact plug material in the phase-change memory device, the contact resistance is increased compared to the case of forming a contact plug in the hole type. It can further reduce, so that the amount of current in the transistor can be increased more effectively.

Here, although not shown and described in detail, other configurations except for the contact plugs 26a and 27a in the phase change memory device according to another embodiment of the present invention are the same as those of the previous embodiment.

As described above, according to the present invention, by limiting the active region to a rhombus shape, the number of contacts of the source terminal can be made larger than that of the drain terminal, and the contact resistance of the source can be made relatively lower than that of the drain terminal. Therefore, the present invention can increase the amount of current required for the phase change of the phase change film, thereby lowering the operating voltage, thereby improving the characteristics and reliability of the phase change memory element.

In addition, the present invention can reduce the size of the active region by limiting the active region to a rhombus shape, thereby increasing the cell efficiency.

Hereinbefore, the present invention has been described with reference to some examples, but the present invention is not limited thereto, and a person skilled in the art to which the present invention pertains has many modifications and variations without departing from the spirit of the present invention. It will be appreciated that it can be added.

Claims (9)

Semiconductor substrates; An isolation layer formed in the semiconductor substrate to define an active region having a rhombus shape; A gate formed such that two are disposed on an active region including the device isolation layer; A source region formed in an active region portion between the gates and a drain region formed in an active region portion outside each gate; A plurality of first contact plugs formed in a row on the source region and several second contact plugs formed in a row on the drain region along the gate direction; A bar type first metal pad formed to contact the first contact plugs on the source region and a bar type second metal pad formed to contact the second contact plugs on the drain region; A phase conversion cell formed on the second metal pad and formed of a stacked structure of a lower electrode, a phase conversion film, and an upper electrode; A third contact plug formed on the phase change upper electrode; And A metal wire formed to contact the third contact plug; Phase change memory device comprising a. The method of claim 1, And the number of the first contact plugs is larger than that of the second contact plugs. The method of claim 1, And the lower electrode is formed in a plug shape. The method of claim 3, wherein And the lower electrode is formed to be disposed on an intermediate portion of the second metal pad. The method of claim 1, And the upper electrode including the phase change layer is formed to overlap the lower electrode and the gate. Semiconductor substrates; An isolation layer formed in the semiconductor substrate to define an active region having a rhombus shape; A gate formed such that two are disposed on an active region including the device isolation layer; A source region formed in an active region portion between the gates and a drain region formed in an active region portion outside each gate; A first contact plug formed in a bar type on the source region along the gate direction and a second contact plug formed in a bar type on the drain region; A first metal pad formed on the first contact plug and a second metal pad formed on the drain region; A phase conversion cell formed on the second metal pad and formed of a stacked structure of a lower electrode, a phase conversion film, and an upper electrode; A third contact plug formed on the phase change upper electrode; And A metal wire formed to contact the third contact plug; Phase change memory device comprising a. The method of claim 6, And the lower electrode is formed in a plug shape. The method of claim 7, wherein And the lower electrode is formed to be disposed on an intermediate portion of the second metal pad. The method of claim 6, And the upper electrode including the phase change layer is formed to overlap the lower electrode and the gate.

Images