KR20060000993A - Shift register, display apparatus having the same, and method of driving the same - Google Patents

Abstract

The present invention relates to a shift register, a display device having the same, and a method of driving a shift register, wherein a plurality of stages are disposed and a shift resist sequentially outputting gate signals of respective stages to a gate line, wherein each stage is an adjacent stage. A first pull-up driving controller configured to receive a gate signal and output a control signal, a pull-up driver configured to receive a first clock signal from an external source and output the first clock signal as a gate signal in response to the control signal; According to the present invention, a shift register driving circuit capable of responding to a trend of decreasing margin margin of the panel may be formed using a small number of switching elements.

Shift register, stage, carry signal, gate signal, clock signal

Description

SHIFT REGISTER, DISPLAY APPARATUS HAVING THE SAME, AND METHOD OF DRIVING THE SAME}

1 is a conceptual diagram schematically showing the configuration of a TFT substrate of a poly-TFT LCD.

2 is a conceptual diagram schematically showing the configuration of a TFT substrate of a conventional a-Si LCD.

3 is a conceptual diagram schematically illustrating a display device having a shift register according to an exemplary embodiment of the present invention.

4 is a block diagram of a shift register according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of each stage of the shift register shown in FIG.

6 is a block diagram of a shift register according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of each stage of the shift register shown in FIG.

FIG. 8 is an output timing diagram of the shift register shown in FIGS. 6 and 7.

<Description of the symbols for the main parts of the drawings>

100: display panel 200: timing control unit

300: gray scale generator 400: power generator                 

500: shift register 510: first pull-up drive control unit

520 and 522: pull-up driving unit 530: second pull-up driving control unit

550, 552: pull-down driving unit 600: data driving circuit

The present invention relates to a shift register of a display device and a display device using the same. In particular, a shift for generating a scan signal for scanning a gate line in a gate line driving circuit of an AMTFT-LCD (Active Matrix Thin Film Transistor Liquid Crystal Display) It is about registers.

Recently, information processing devices have been rapidly developed to have various forms, various functions, and faster information processing speed. Information processed in such an information processing device has an electrical signal form. In order for the user to visually check the information processed by the information processing device, a display device serving as an interface is required.

Recently, a liquid crystal display device has a light weight, a small size, high resolution, low power, and an environment-friendly advantage compared to a typical CRT display device, and is capable of full color and is emerging as a next-generation display device.

A liquid crystal display device converts a change in optical properties such as birefringence and light scattering characteristics of a liquid crystal cell that emits light by applying a voltage to a specific molecular array of liquid crystal, and converts it into another molecular array. A display using modulation of light by a liquid crystal cell.

The liquid crystal display is largely divided into twisted nematic (TN) and super-twisted nematic (STN) methods, and due to the difference in driving method, an active matrix display method using a switching element and a TN liquid crystal and a passive matrix using STN liquid crystal There is a passive matrix display method.

The main difference between these two methods is that the active matrix display method is used for TFT-LCD, which uses a TFT as a switch to drive the LCD, and the passive matrix display method does not use transistors, so a complicated circuit is required. Do not

TFT-LCD is divided into a-Si TFT LCD and poly-Si TFT LCD. Poly-Si TFT LCD has low power consumption and low price, but has a disadvantage of complicated TFT manufacturing process compared to a-Si TFT. Thus, poly-Si TFT LCDs are mainly applied to small display devices such as those of IMT-2000 phones.

The a-Si TFT LCD has large area and high yield, and is mainly applied to large screen display devices such as notebook PCs, LCD monitors, and HDTVs.

As shown in FIG. 1, a poly-Si TFT LCD forms a data driving circuit 12 and a gate driving circuit 14 on a glass substrate 10 on which a pixel array is formed, and a terminal portion 16 and an integrated printed circuit. The substrate 20 is connected with the film cable 18. Such a structure can reduce manufacturing cost and minimize power loss by integrating a driving circuit.                         

However, as shown in FIG. 2, the a-Si TFT LCD forms the data driving chip 34 on the flexible printed circuit board 32 by a COF (CHIP ON FLIM) method, and the flexible printed circuit board 32. The data printed circuit board 36 is connected to the data line terminal part of the pixel array through the through circuit. In addition, the gate driving chip 40 is formed on the flexible printed circuit board 38 by a COF method, and the gate printed circuit board 42 and the gate line terminal portion of the pixel array are connected through the flexible printed circuit board 40. .

In recent years, a technique for removing a gate printed circuit board by using an integrated printed circuit board technology for mounting a gate power supply unit on a data printed circuit board has been introduced. Korean Patent Publication No. 2000-66493, filed by the present applicant, discloses an LCD module employing an integrated printed circuit board with a gate printed circuit board removed.

However, even if the integrated printed circuit board is adopted, the flexible printed circuit board on which the gate driving circuit is formed is used as it is. Therefore, since a plurality of flexible printed circuit boards are assembled to glass substrates, a-Si TFT LCDs are more complicated than OLB (OUTER LEAD BONING) processes compared to poly-Si TFT LCDs, resulting in expensive manufacturing costs.

Therefore, in recent years, a-Si TFT LCDs, like poly-Si TFT LCDs, have been trying to develop a technique for reducing the number of assembly processes by simultaneously forming a gate driving circuit on a glass substrate with a pixel array.

U. S. Patent No. 5,517, 542 discloses a description of a shift register of a gate driving circuit.

In the patent, the shift register of the gate driving circuit uses three clock signals. Each stage of the shift register uses two clock signals of the three clock signals, is enabled by using the output signal of the previous stage as an input signal, and remains disabled by feeding back the output of the second next stage.

Each stage of the patent provides a capacitor charge method for the voltage applied to the gate of the pull-down transistor to maintain the disabled state. Therefore, there is a fear of a malfunction in which the pull-down transistor is turned off in the disabled state when the gate threshold voltage of the pull-down transistor becomes higher than the charge voltage of the capacitor due to the stress of the pull-down transistor.

The patent employs a power supply circuit that raises the VDD supply voltage in proportion to the increase in the threshold voltage of the pull-down transistor in order to compensate for the malfunction caused by the increase in the threshold voltage.

The first object of the present invention is to solve this conventional problem, and to provide a shift register with high reliability.

Moreover, the 2nd object of this invention is to provide the display apparatus provided with the said shift register which has high reliability.

Further, a third object of the present invention is to provide a shift register driving method having high reliability.

According to an exemplary embodiment of the present invention, a shift register includes a plurality of stages, and sequentially outputs gate signals of respective stages to a gate line, and each stage receives gate signals of an adjacent stage. A first pull-up driving controller configured to output a control signal; A pull-up driver configured to receive a first clock signal from an external source and output the first clock signal as a gate signal in response to the control signal; And a pull-down driver configured to deactivate the gate line in response to a second clock signal.

A display device having a shift register according to the present invention includes a display panel having a plurality of gate lines, a plurality of data lines, a plurality of display elements, and a plurality of switching elements; A timing controller for outputting image data and a plurality of control signals; A shift register sequentially outputting a gate signal to the plurality of gate lines; And a data driving circuit outputting a data signal to the plurality of data lines, wherein the shift register is configured of a plurality of stages corresponding to the plurality of gate lines, and each stage controls gate signals of an adjacent stage. A first clock signal is output as a signal to the gate line as a signal, and the gate line is inactivated in response to a second clock signal.

The shift register driving method according to the present invention is applied to a shift register in which a plurality of stages are arranged and sequentially output gate signals of respective stages to a gate line. The shift register driving method includes: receiving a gate signal of an adjacent stage and outputting a control signal; Receiving a first clock signal from an external source and outputting the first clock signal as a gate signal in response to the control signal; And deactivating the gate line in response to a second clock signal.

According to the present invention, a shift register with high reliability can be implemented by using two clock signals as input signals of each stage of the shift register.

Further, according to the present invention, the shift register with high reliability can be implemented by using the carry signal of the previous stage as the input signal of each stage of the shift register.

In addition, according to the present invention, it is possible to implement a display device having a shift register with high reliability.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention.

Hereinafter, a shift register and a display device having the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a conceptual diagram illustrating a display device having a shift register according to the present invention.

Referring to FIG. 3, the display device includes a display panel 100, a timing controller 200, a gray scale generator 300, a power generator 400, a shift register 500, and a data driving circuit 600. do.

The timing controller 200 receives digital image data and a control signal supplied from the outside, generates a plurality of control signals for controlling the shift register 500 and the data driving circuit 600, and the control signals. As a result, the digital image data is supplied to the data driving circuit (CD) 600. The control signal supplied from the timing controller 200 to the shift register 500 is supplied along a wiring on the display panel through, for example, a flexible printed cable (FPC) or TCP. For example, the control signal is transmitted to the first end of the shift register 500 along the wiring on the display panel 100 through one end of the FPC or TCP forming the data driving circuit 600.

In addition, the data driving circuit 600 converts the digital image data supplied from the timing controller 200 into an analog voltage according to the control signal and supplies it to a plurality of data lines formed on the display panel.

In addition, the shift register 500 generates a driving pulse (gate signal) for controlling a plurality of gate lines formed on the display panel.

In addition, the power generator 400 supplies a power voltage necessary for the timing controller 200, the gray voltage unit 300, the shift register 500, and the data driving circuit 600. For example, the power generation unit 400 generates a digital power supply voltage DVdd, an analog power supply voltage AVdd, and gate on / off voltages GVon and GVoff, respectively, and supplies them to the components. The gate off voltage Gvoff may have a ground voltage level or a negative voltage.

The display panel 100 includes a plurality of gate lines, a plurality of data lines, a plurality of display elements, and a switching element for controlling the display elements, and the gray scale generator 300 is a reference for color expression. The voltage is generated to configure a plurality of reference voltages according to the analog voltage input from the outside. In general, different numbers of reference voltages are configured according to product characteristics, that is, resolution and size.

4 is a diagram showing the first embodiment showing the configuration of the shift register 500. As shown in FIG.

Referring to FIG. 4, the shift register 500 outputs N stages ASRC1, ASRC2, ASRC3, N outputting N gate signals (or scan signals) GOUT 1, GOUT 2,... GOUT N. ASRCN and a dummy stage ASRC + X for outputting the dummy gate signal GDUMMY. The dummy stage outputs the dummy gate signal GDUMMY to disable the previous stage, and may provide the dummy gate signal GDUMMY to all stages of the previous stage as well as the specific stage. Here, the shift register 500 is coplanar with a display panel (not shown) having a switching element (not shown) formed in a region defined by a plurality of gate lines (not shown) and data lines (not shown). Is formed.

The first stage ASRC1 of the shift register 500 controls the first and second clock signals CK and CKB provided from the outside through a clock generator (not shown) for generating a plurality of clocks. The scan start signal STV is received through the terminal IN1 and the output signal GOUT 2 provided from the second stage ASRC2 through the second control terminal IN2 is output to the first gate line. The output terminal GOUT 1 and the first power supply voltages Voff and VSS are output through the output terminal OUT, and the output signal GOUT 1 is output to the first control terminal IN1 of the second stage ASRC2. . The plurality of clock generators generate a plurality of clock signals that are out of phase with each other. For example, when two clocks are used, clocks that are inverted in phase are used. Use a clock with a delayed phase. The VSS may have a ground voltage level or a negative voltage.

The second stage ASRC2 receives the first and second clock signals CK and CKB provided from the outside through a clock generator that generates the plurality of clocks, and the first stage through the first control terminal IN1. The output signal GOUT 1 of the ASRC1 and the output signal GOUT 3 of the third stage ASRC3 are respectively received through the second control terminal IN2 and output signal GOUT 2 and the second gate line. The first power voltages Voff and VSS are output through the output terminal OUT, and the output signal GOUT 2 is output to the first control terminal IN1 of the third stage ASRC3.

In the same manner as described above, the N-th stage ASRCN receives the first and second clock signals CK and CKB provided from the outside through a clock generator that generates the plurality of clocks. Through the gate signal provided from the previous stage and the dummy gate signal GDUMMY provided from the dummy stage ASRC + X through the second control terminal IN2, respectively, and output signal GOUT N to the N-th gate line. ) And the first power voltages Voff and VSS are output through the output terminal OUT, and the output signal GOUT N is output to the first control terminal IN1 of the dummy stage ASRC + X.

The first and second clock signals CK and CKB are alternately applied to each stage of the shift register 500. That is, the first clock signal CK is applied to the first stage ASRC1 through the first clock terminal CK1, and the second clock signal CKB is applied through the second clock terminal CK2. The second clock signal CKB is applied to the second stage ASRC2 through the first clock terminal CK1, and the first clock signal CK is applied through the second clock terminal CK2. do.

FIG. 5 is a circuit diagram of each stage of the shift register 500 shown in FIG.

Referring to FIG. 5, each stage of the shift register 500 includes a first pull-up driving controller 510, a pull-up driving unit 520, a second pull-up driving control unit 530, and a pull-down driving unit 550. The following describes only the Mth stage (specific stage) among the plurality of stages.

The first pull-up driving controller 510 includes a first transistor T1 in which a drain electrode and a gate electrode are commonly connected, and an output signal of the M-1 stage is input, and the node X is input by the input output signal. The first control signal CNTR1 is outputted to the. Here, when the M stage is the first stage, the start signal STV is input to the first transistor T1 of the first pull-up driving controller 510. The first transistor T1 is formed of an NMOS transistor.

The pull-up driver 520 has a gate electrode connected to the node X and controlled by the first control signal CNTR1, a drain electrode receives the first clock signal CK, and a source electrode of the pull-down driver 550. ) And a second transistor T2 connected to the output terminal OUT. In addition, a first capacitor C1 (not shown) is formed between the drain electrode and the gate electrode of the second transistor T2, and a second capacitor C2 is disposed between the gate electrode and the source electrode of the second transistor T2. ) Is formed. Here, the first capacitor C1 and the second capacitor C2 are formed of parasitic capacitors or additionally added capacitors. Preferably, since the second capacitor C2 stores the first control signal CNTR1 of the node X and performs a boot strapping function, an overlap area between the gate electrode and the source electrode is determined by the gate electrode. The capacitance is larger than that of the first capacitor by increasing the overlap area with the drain electrode. The second transistor T2 is formed of an NMOS transistor.

The second pull-up driving controller 530 may include a gate electrode provided with an output signal GOUT M + 1 output from an output terminal OUT of the M + 1 stage, and a drain electrode connected to a node X so as to receive a second signal. The third electrode T3 is connected to the gate electrode of the transistor T2, and the source electrode includes a third transistor T3 connected to the first power supply voltages Voff and VSS. When the gate electrode is turned on by the output signal GOUT M + 1 output from the output terminal OUT of the M + 1 stage, the first power voltage Voff and VSS become the gate of the second transistor T2. Control the electrode. The third transistor T3 is formed of a NOMS transistor.

The output terminal OUT is connected to the first pull-up driving controller 510 of the M + 1 stage and the second pull-up driving controller 530 of the M-1 stage and output signal GOUT M of the M stage. Will print

The pull-down driver 550 receives a second clock signal CKB, a gate electrode receives first power supply voltages Voff and VSS, and a source electrode of the pull-up driver 520. And a fourth transistor T4 connected to the source electrode of the transistor T2 and the output terminal OUT. The pull-down driver 550 is controlled by the second clock signal CKB to disable the gate output terminal OUT. In addition, deterioration of the fourth transistor T4 may be prevented by using the control signal of the gate electrode as a clock signal.

The first and second clock signals CK and CKB are alternately applied to each stage through the first clock stage CK1 or the second clock stage CK2. In addition, although each stage is described as receiving an output signal of the nearest stage, that is, the previous or next stage, it is also possible to receive the output signal of another adjacent stage, for example, the next or next adjacent stay. For example, in the case of the M stage, the gate signal of the stage M + 2 or M-2 or more may be input.

FIG. 6 shows a second embodiment showing the structure of the shift register 500. As shown in FIG.

Referring to FIG. 6, the shift register 500 includes N stages and dummy gate signals GDUMMY that output N gate signals (or scan signals) GOUT 1, GOUT 2,..., GOUT N. ) Is provided with one dummy stage. Here, the shift register 500 is formed on the display panel 100 as in the first embodiment.

The first stage ASRC1 of the shift register 500 is provided from the outside through a clock generator for generating a plurality of clocks so that the first clock signal CK is supplied to the first clock terminal CK1 and the second clock terminal ( The second clock signal CKVB is input through CK2, the scan start signal STV is input through the first control terminal IN1, and the output signal GOUT 2 of the second stage is input to the first gate line. The output signal GOUT 1 and the first power voltage Voff and VSS are output through the output terminal OUT, and the carry signal terminal of the first stage ASRC1 is received by receiving the first clock signal CK. The carry signal is output to the first control terminal IN1 of the second stage ASRC2 through CR.

The second stage receives a second clock signal CKB through the first clock terminal CK1, a first clock signal CK through the second clock terminal CK2, and a carry signal of the first stage. The output signal GOUT 2 and the first power supply voltage Voff and VSS are output to the second gate line through the output terminal OUT by receiving the output signal GOUT 3 of the third stage. The signal CKB is input to output a carry signal to the first control terminal IN1 of the third stage ASRC3 through the carry signal terminal CR of the second stage ASRC2.

In the same manner as described above, the N-th stage of the shift register 500 is configured to pass the first and second clock signals CK and CKB through the first clock stage CK1 or the second clock stage CK2. And the carry signal of the (N-1) th stage and the dummy gate signal GDUMMY of the dummy stage, and output the output signal GOUT N and the first power supply voltage Voff and VSS to the Nth gate line. Output through terminal (OUT). The carry signal is output to the first control terminal IN1 of the dummy stage ASRC + X.

The first and second clock signals CK and CKB are alternately applied to each stage through the first clock stage CK1 or the second clock stage CK2. In addition, although each stage is described as receiving an output signal of the nearest stage, that is, the previous or next stage, it is also possible to receive the output signal of another adjacent stage, for example, the next or next adjacent stage. . For example, in the case of the Nth stage, a gate signal of a stage N + 2 or an N-2 or more stage may be input.

FIG. 7 is a circuit diagram of each stage of the shift register 500 shown in FIG.

Referring to FIG. 7, each stage of the shift register 500 according to the present invention includes a first pull-up driving controller 510, a pull-up driving unit 522, a second pull-up driving control unit 530, and a pull-down driving unit 552. do. The following describes only the Mth stage among the plurality of stages.

The first pull-up driving controller 510 includes a first transistor T1 in which a drain electrode and a gate electrode are commonly connected, and a carry signal of the (M-1) stage is input, and the input signal is output by the input output signal. The first control signal CNTR1 is output to the node X. Here, when the M stage is the first stage, the start signal STV is input to the first transistor T1 of the first pull-up driving controller 510. The first transistor T1 is formed of an NMOS transistor.

The pull-up driving unit 522 has a gate electrode connected to the node X, controlled by the first control signal CNTR1, a drain electrode receiving the first clock signal CK, and a source electrode of the output terminal OUT. Is connected to the node X and is controlled by the first control signal CNTR1, the drain electrode receives the first clock signal CK, and the source electrode is the Mth. A fifth transistor T5 connected to the first pull-up driving controller 510 of the +1 stage is included. The fifth transistor T5 receives the first clock signal CK to generate a carry signal, and an output signal GOUT 1 output through the output terminal OUT is a gate of the display panel 100. In order to prevent the input of the input stage 510 of the next stage by being delayed by the resistors and capacitors of the lines, the carry signal is directly input to the input terminal 510 of the next stage without going through the output terminal OUT. In addition, a first capacitor C1 (not shown) is formed between the drain electrode and the gate electrode of the second transistor T2, and a second capacitor C2 is disposed between the gate electrode and the source electrode of the second transistor T2. ) Is formed. Here, the first capacitor C1 and the second capacitor C2 are formed of parasitic capacitors or additionally added capacitors. Preferably, since the second capacitor C2 stores the first control signal CNTR1 of the node X to perform boot strapping, the second capacitor C2 has an overlap area between the gate electrode and the source electrode. The capacitance is larger than that of the first capacitor by increasing the overlap area between the drain electrode and the drain electrode. The second transistor T2 is formed of an NMOS transistor.

The second pull-up driving controller 530 may include a gate electrode provided with an output signal GOUT M + 1 output from an output terminal OUT of the M + 1th stage, and a drain electrode connected to the node X so as to be connected to the second node X. The third electrode T3 is connected to the gate electrode of the transistor T2 and the fifth transistor T5, and the source electrode includes a third transistor T3 connected to the first power supply voltages Voff and VSS. When the gate electrode is turned on by the output signal GOUT M + 1 output from the output terminal OUT of the M + 1th stage, the first power voltage Voff and VSS become the second transistor T2 and the first transistor. The gate electrode of the transistor T5 is controlled. The third transistor T3 is formed of an NMOS transistor.

The output terminal OUT is connected to the second pull-up driving controller 530 of the M-1 stage and outputs an output signal GOUT M of the Mth stage.

The pull-down driver 552 receives a second clock signal CKB, a gate electrode receives first power supply voltages Voff and VSS, and a source electrode receives a second transistor of the pull-up driver 522. The fourth transistor T4 and the gate electrode connected to the source electrode and the output terminal OUT of the T2 receive the second clock signal CKB, and the drain electrode provides the first power supply voltages Voff and VSS. The source electrode includes a sixth transistor T6 connected to the node Y. The pull-down driver 552 is controlled by the second clock signal CKB to disable the gate output terminal OUT and the node Y. In addition, deterioration of the fourth transistor T4 and the sixth transistor T6 can be prevented by using the control signal of the gate electrode as the clock signal.

As described above, each stage of the shift register 500 includes first and second clock signals CK and CKB for each stage through the first clock stage CK1 or the second clock stage CK2. Alternate with each other. In addition, although each stage is described as receiving an output signal of the nearest stage, that is, the previous or next stage, it is also possible to receive the output signal of another adjacent stage, for example, the next or next adjacent stage. For example, in the case of the M stage, the gate signal of the stage M + 2 or M-2 or more may be input.

FIG. 8 is an output timing diagram according to the shift register 500 shown in FIGS. 6 and 7 described above.

Referring to FIG. 8, output signals GOUT 1, GOUT 2,... From each stage of the shift register 500 are generated in synchronization with a clock signal.

It is apparent to those skilled in the art that the shift register can be applied to various flat panel display devices such as liquid crystal display devices and organic EL devices.

In the above, preferred embodiments of the present invention have been described in detail, but the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the present invention.

As described above, according to the present invention, the first clock signal CK and the second clock signal CKB are input to each stage of the shift register, and a small number of switching is performed by using the gate output signal of the adjacent stage. The device can be used to form a shift register driving circuit that can reduce the outer margin of the panel.

According to the present invention, a shift register with high reliability can be implemented by using two clock signals as input signals of each stage of the shift register.

Further, according to the present invention, the shift register with high reliability can be implemented by using the carry signal of the previous stage as the input signal of each stage of the shift register.

In addition, according to the present invention, it is possible to implement a display device having a shift register with high reliability.

Claims (20)

A plurality of stages are arranged, the shift register for sequentially outputting the gate signals of each stage to the gate line, each stage is A first pull-up driving controller configured to receive a gate signal of an adjacent stage and output a control signal; A pull-up driver configured to receive a first clock signal from an external source and output the first clock signal as a gate signal in response to the control signal; And And a pull-down driver configured to deactivate the gate line in response to a second clock signal. The method of claim 1, And a second pull-up driving controller connected to the pull-up driving unit and operating according to a gate signal of a next stage. The method of claim 2, And the second pull-up driving controller includes a third transistor supplying a first power voltage to a gate electrode of the pull-up driving unit. The method of claim 1, And the pull-down driver includes a fourth transistor configured to output a first power voltage according to a second clock signal. The method of claim 4, wherein And the first power supply voltage is a gate-off voltage level. The method of claim 1, The first pull-up driving controller includes a first transistor in which a drain electrode and a gate electrode are connected in common and a gate signal of a previous stage is input thereto. The method of claim 1, The pull-up driving unit includes a second transistor having a drain electrode and a gate electrode connected in common to receive the first clock signal, and a source electrode connected to the pull-down driving unit. The method of claim 7, wherein And the pull-up driver further comprises a fifth transistor configured to output a carry signal in response to a first clock signal. The method of claim 8, And a carry signal generated by the fifth transistor is input to an input terminal of a next stage. The method of claim 1, And the first and second clock signals are out of phase with each other. The method of claim 10, And the first and second clock signals are out of phase with each other. The method according to claim 10 or 11, wherein And the first and second clock signals are alternately input to each stage. A display device for displaying image data input from the outside, A display panel having a plurality of gate lines, a plurality of data lines, a plurality of display elements, and a plurality of switching elements; A timing controller for outputting image data, a plurality of gate control signals, and a plurality of data control signals; A shift register configured to sequentially output gate signals to the plurality of gate lines according to the plurality of gate control signals; And A data driving circuit configured to output data signals to the plurality of data lines according to the plurality of data control signals, The shift register includes a plurality of stages corresponding to the plurality of gate lines, each stage outputs a first clock signal as a gate signal to the gate line using a gate signal of an adjacent stage as a control signal, and a second stage. A display device for inactivating the gate line in response to a clock signal. The display device of claim 13, wherein the shift register is formed on the panel. The display device of claim 13, wherein the plurality of gate control signals are supplied to a shift register through a wiring formed on the display panel. The display device of claim 13, wherein the first and second clock signals are out of phase with each other.     14. The method of claim 13, wherein the first and second clock signals are inverted in phase with each other. Display device made with gong. The method according to claim 16 or 17, And the first and second clock signals are alternately input to each stage. A method of driving a shift register in which a plurality of stages are arranged and sequentially outputs gate signals of respective stages to a gate line, Receiving a gate signal of an adjacent stage and outputting a control signal; Receiving a first clock signal from an external source and outputting the first clock signal as a gate signal in response to the control signal; And And inactivating the gate line in response to a second clock signal. 20. The method of claim 19, wherein the first and second clock signals are out of phase with each other.

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