CN103514851A - Liquid crystal display and shift register thereof - Google Patents
Liquid crystal display and shift register thereof Download PDFInfo
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- CN103514851A CN103514851A CN201310409640.3A CN201310409640A CN103514851A CN 103514851 A CN103514851 A CN 103514851A CN 201310409640 A CN201310409640 A CN 201310409640A CN 103514851 A CN103514851 A CN 103514851A
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Abstract
The invention discloses a liquid crystal display and a shift register of the liquid crystal display. The shift register comprises multiple levels of shift register bodies which are connected together in series. Due to the fact that the manufactured channel length of transistors in charge of stopping outputting of a scanning signal in the shift register bodies is larger than that of transistors in charge of outputting the scanning signal in the shift register bodies, the degree of influences, on the transistors in charge of outputting the scanning signal in the shift register bodies, of leak currents, located in a subcritical area, of the transistors in charge of stopping outputting of the scanning signal in the shift register bodies, is abated, and therefore the shift register can output the scanning signal normally.
Description
The application is for dividing an application, and the application number of its female case is: 200910159002.4, and the applying date is: on July 29th, 2009, application is artificial: Youda Photoelectric Co., Ltd, denomination of invention is: liquid crystal display and shift LD device thereof.
Technical field
The present invention relates to a kind of flat-panel screens, and particularly relevant for a kind of liquid crystal display and shift LD device thereof.
Background technology
In recent years, along with semiconductor science and technology is flourish, portable type electronic product and flat-panel screens product also rise thereupon.And in the middle of the type of numerous flat-panel screens, liquid crystal display (Liquid Crystal Display, LCD), based on the advantage such as its low voltage operating, radiationless line scattering, lightweight and volume be little, has become the main flow of each display product immediately.Also also because of like this, invariably ordering about Zhe Gejia manufacturer will be towards more microminiaturized and low cost of manufacture development for the development technique of liquid crystal display.
In order to reduce the cost of manufacture of liquid crystal display, existing partly manufacturer develops at display panels and adopts amorphous silicon (amorphous silicon, a-Si), under the condition of technique, the shift register of the turntable driving IC inside that the scan-side that was originally disposed at display panels can be used (shift register) shifts and is directly configured on the glass substrate (glass substrate) of display panels.Therefore, being originally disposed at the turntable driving IC that the scan-side of display panels used can omit, so as to reaching the object of the cost of manufacture that reduces liquid crystal display.
Generally speaking, the shift register being directly produced on the glass substrate of display panels mainly can be comprised of many N-type transistors.Wherein, part N-type transistor is in order to be responsible for a corresponding row pixel in the operating period of shift register, output scanning signal was with unlatching display panels, and all the other N-type transistors are in order to be responsible for stopping output scanning signal during the not operation of shift register.
Yet, in practice, due in order to be responsible for output scanning signal with all identical in order to be responsible for stopping the transistorized passage length of N-type (channel length) of output scanning signal.Therefore, with this understanding, in order to be responsible for the N-type transistor of output scanning signal probably can be subject to being responsible for stopping output scanning signal N-type transistor leakage current of (sub-threshold region) in subcritical district impact and cause normally output scanning signal.Thus, shift register can lose efficacy with the related normally show image picture of liquid crystal display that affects.
Summary of the invention
In view of this, the invention provides a kind of shift LD device, it comprises multi-stage serial connection shift register together.Wherein, i level shift register comprises precharge unit, pull-up unit, and drop-down unit, and i is positive integer.The first sweep signal that precharge unit is exported in order to receive (i-1) level shift register, and export according to this charging signals.Pull-up unit couples precharge unit, in order to receive described charging signals and the first clock signal, and exports according to this second sweep signal.Drop-down unit couples precharge unit and pull-up unit, the 3rd sweep signal of exporting in order to receive the second clock signal and (i+1) level shift register, and determine whether described the second sweep signal is pulled down to a reference potential according to this.
In an one exemplary embodiment of the present invention, in precharge unit, pull-up unit and drop-down unit, there is respectively at least one transistor.Wherein, the transistor in drop-down unit has first passage length, and transistor in precharge unit and pull-up unit has respectively second channel length, and described first passage length is greater than described second channel length.
In an one exemplary embodiment of the present invention, described first passage length is essentially 1.01 times to 4 times of described second channel length.
The present invention separately provides a kind of liquid crystal display, it comprise display panels with in order to the backlight module of the required backlight of display panels to be provided.Wherein, display panels comprises the shift LD device that substrate and the invention described above provide, and the shift LD device that the invention described above provides is for to be directly configured on the substrate of display panels.
Will be appreciated that, above-mentioned general description and following embodiment are only exemplary and illustrative, and it can not limit the scope that institute of the present invention wish is advocated.
Accompanying drawing explanation
Fig. 1 illustrates the system block diagrams into the liquid crystal display 100 of the present invention's one one exemplary embodiment;
Fig. 2 illustrates the calcspar into the shift LD device SRD of the present invention's one one exemplary embodiment;
Fig. 3 A illustrates the i level shift register SR into the present invention's one one exemplary embodiment
icalcspar;
Fig. 3 B illustrates the i level shift register SR into the present invention's one one exemplary embodiment
icircuit diagram;
Fig. 4 A illustrates as the diagrammatic cross-section of N-type transistor T 3 with T4;
Fig. 4 B illustrates as the diagrammatic cross-section of N-type transistor T 1 with T2;
Fig. 5 illustrates the i level shift register SR into the present invention's one one exemplary embodiment
ithe experimental waveform figure of middle node Q.
Wherein, Reference numeral
Embodiment
With detailed reference to one exemplary embodiment of the present invention, the example of described one exemplary embodiment is described in the accompanying drawings.In addition, all may part, in drawings and the embodiments, use the identical or similar portions of the element/member/symbology of same numeral.
Fig. 1 illustrates the system block diagrams into the liquid crystal display 100 of the present invention's one one exemplary embodiment.Please refer to Fig. 1, liquid crystal display 100 comprises display panel 101, source electrode driver 103, timing control unit 105, and in order to the backlight module 107 of the required backlight of display panel 101 to be provided.In display panel 101 viewing area AA, there are a plurality of pixels (represent with M * N in figure, M, N are all positive integer) of arranging with matrix.In addition, for example, a side on the substrate of display panel 101 (not illustrating, is glass substrate) more directly disposes shift LD device SRD.Shift LD device SRD is controlled by timing control unit 105, in order to sequence output scanning signal SS
1～SS
nfirst row pixel in the AA of Yi Cong viewing area is opened into last row pixel one by one.
Clearer, Fig. 2 illustrates the calcspar into the shift LD device SRD of the present invention's one one exemplary embodiment.Please merge with reference to Fig. 1 and Fig. 2, shift LD device SRD comprises the shift register SR that N level circuit structure is identical in fact and be serially connected each other
1～SR
n.In this one exemplary embodiment, due to shift register SR
1～SR
ncircuit structure identical in fact with principle of work, therefore at this only for i level shift register SR
iexplain as follows.
Fig. 3 A illustrates the i level shift register SR into the present invention's one one exemplary embodiment
icalcspar.Fig. 3 B illustrates the i level shift register SR into the present invention's one one exemplary embodiment
icircuit diagram.Please merge the B with reference to Fig. 1～Fig. 3, i level shift register SR
icomprise precharge unit 301, pull-up unit 303, and drop-down unit 305.Wherein, precharge unit 301 is in order to receive (i-1) level shift register SR
i-1the sweep signal SS exporting
i-1, and export according to this charging signals CV.In this one exemplary embodiment, except the 1st grade of shift register SR
1in precharge unit 301 for outside the start signal STV that receives timing control unit 105 and provide, the sweep signal that the precharge unit 301 in all the other shift registers is exported for receiving upper level shift register.
For instance, the 2nd grade of shift register SR
2in precharge unit 301 for receiving the 1st grade of shift register SR
1the sweep signal SS exporting
1, 3rd level shift register SR
3in precharge unit 301 for receiving the 2nd grade of shift register SR
2the sweep signal SS exporting
2, the rest may be inferred to N level shift register SR
nin precharge unit 301 for receiving (N-1) level shift register SR
n-1the sweep signal SS exporting
n-1.
Continue referring to Fig. 3 A, pull-up unit 303 couples precharge unit 301, the clock signal CK providing in order to receive charging signals CV that precharge unit 301 exports and time schedule controller 105, and output scanning signal SS according to this
i.Drop-down unit 305 couples precharge unit 301 and pull-up unit 303, the clock signal XCK and (i+1) level shift register SR that in order to receive time schedule controller 105, provide
i+1the sweep signal SS exporting
i+1, and whether determine by sweep signal SS according to this
ibeing pulled down to reference potential Vss(is for example earthing potential, but is not restricted to this).Wherein, the clock signal CK that time schedule controller 105 provides and the phase differential of XCK are 180 degree.
In this, continue referring to Fig. 3 B, in this one exemplary embodiment, precharge unit 301 has N-type transistor T 1.Wherein, the grid of N-type transistor T 1 be coupled in source electrode together with to receive (i-1) level shift register SR
i-1the sweep signal SS exporting
i-1, the drain electrode of N-type transistor T 1 is in order to export charging signals CV.
In addition, pull-up unit 303 has N-type transistor T 2 and capacitor C.Wherein, the grid of N-type transistor T 2 couples the drain electrode of N-type transistor T 1, the clock signal CK that the source electrode of N-type transistor T 2 provides in order to receive time schedule controller 105, and the drain electrode of N-type transistor T 2 is in order to output scanning signal SR
i.Capacitor C is coupled between the grid and drain electrode of N-type transistor T 2.
Moreover drop-down unit 305 has N-type transistor T 3 and T4.Wherein, the grid of N-type transistor T 3 couples the drain electrode of N-type transistor T 2 in order to the clock signal XCK providing that receives time schedule controller 105, the source electrode of N-type transistor T 3, and the drain electrode of N-type transistor T 4 is coupled to reference potential Vss.The grid of N-type transistor T 4 is in order to receive (i+1) level shift register SR
i+1the sweep signal SS exporting
i+1, N-type transistor T 4 source electrode couple the grid of N-type transistor T 2, the drain electrode of N-type transistor T 4 is coupled to reference potential Vss.
In this one exemplary embodiment, N-type transistor T 1 has identical passage length (channel length) with T2, and N-type transistor T 3 has identical passage length with T4.But the passage length of N-type transistor T 3 and T4 is greater than the passage length of N-type transistor T 1 and T2.
Clearer, Fig. 4 A illustrates as the diagrammatic cross-section of N-type transistor T 3 with T4, and Fig. 4 B illustrates as the diagrammatic cross-section of N-type transistor T 1 with T2.Please merge with reference to Fig. 4 A and Fig. 4 B, from Fig. 4 A and Fig. 4 B, can know and find out, label D is expressed as the drain electrode of N-type transistor T 1～T4, the source electrode that label S is expressed as N-type transistor T 1～T4, and label G is expressed as the grid of N-type transistor T 1～T4.In addition, label L1 is expressed as the passage length of N-type transistor T 3 and T4, and label L2 is expressed as the passage length of N-type transistor T 1 and T2.
Hence one can see that, at this so-called " passage length ", refer to the distance between the transistorized drain electrode of N-type and source electrode, and under better situation, the passage length L1 of N-type transistor T 3 and T4 can be 1.01 times to 4 times of the passage length L2 of N-type transistor T 1 and T2 in fact, but is not restricted to this.That is to say, N-type transistor T 3 can be looked closely actual design demand and determine with respect to N-type transistor T 1 and the multiple of the passage length L2 of T2 with the passage length L1 of T4, after appearance, describes in detail again.
Based on above-mentioned, as i level shift register SR
i precharge unit 301 receive (i-1) level shift register SR
i-1the sweep signal SS exporting
i-1time, N-type transistor T 1 can be unlocked that node Q is carried out to precharge.Thus, when clock signal CK activation that time schedule controller 105 provides, voltage on node Q can be subject to clock signal CK coupling effect (coupling effect) impact and drawn high, so as to the nmos pass transistor T2 of pull-up unit 303 can be unlocked, thus output scanning signal SS
ito open corresponding i row pixel in the AA of viewing area.
And then, at precharge unit 301 and pull-up unit 303, be responsible for output scanning signal SS
iafterwards, the N-type transistor T 3 of drop-down unit 305 can be unlocked because of the clock signal XCK activation that time schedule controller 105 provides.Thus, sweep signal SS
ican be pulled down to reference potential Vss to close corresponding i row pixel in the AA of viewing area.
In addition, when the N-type transistor T 3 of drop-down unit 305 is by sweep signal SS
iafter being pulled down to reference potential Vss, due to (i+1) level shift register SR
i+1the sweep signal SS exporting
i+1can feed back to i level shift register SR
ithe N-type transistor T 4 of drop-down unit 305.Thus, i level shift register SR
ithe nmos pass transistor T4 of drop-down unit 305 can be unlocked, thereby node Q is discharged, to avoid node Q to be responsible for output scanning signal SS at precharge unit 301 and pull-up unit 303
ibe subject to afterwards the coupling of clock signal CK.Hence one can see that, when precharge unit 301 and pull-up unit 303 are responsible for output scanning signal SS
iafterwards, output scanning signal SS can be responsible for stopping in drop-down unit 305
i.
Accordingly, when timing control unit 105 provides start signal STV to the 1st grade of shift register SR
1 precharge unit 301, and provide respectively the clock signal CK of phase differential 180 degree and XCK to all shift register SR
1～SR
npull-up unit 303 during with drop-down unit 305, the shift register SR in shift LD device SRD
1～SR
ncan sequence output scanning signal SS
1～SS
nfirst row pixel in the AA of ，Yi Cong viewing area is opened into last row pixel one by one, and source electrode driver 103 can provide corresponding display data to the row pixel that is shifted LD device SRD and opens.Thus, add the backlight that backlight module 107 provides, display panel 101 can show image picture.
The content of addressing according to prior art is known, due in order to be responsible for output scanning signal with all identical in order to be responsible for stopping the transistorized passage length of N-type of output scanning signal.Therefore, with this understanding, in order to be responsible for the impact of N-type transistor that the N-type transistor of output scanning signal probably can be subject to being responsible for the stopping output scanning signal leakage current in subcritical district, cause normally output scanning signal.Thus, shift register can lose efficacy with the related normally show image picture of liquid crystal display that affects.
Also also because of so, as shift register SR
1～SR
nthe passage length all (that is L1=L2) under identical condition of N-type transistor T 1～T4, in order to be responsible for output scanning signal SS
1～SS
nn-type transistor T 1 probably can be subject to being responsible for stopping output scanning signal SS with T2
1～SS
nn-type transistor T 3 cause normally output scanning signal SS with the impact of the leakage current of T4 in subcritical district
1～SS
n.Thus, shift register SR
1～SR
ncan lose efficacy with the related normally show image picture of liquid crystal display 100 that affects.
In view of this, the passage length L2 of the ratio precharge unit 301 that this one exemplary embodiment is made the passage length L1 of the N-type transistor T 3 of drop-down unit 305 and T4 especially and the N-type transistor T 1 of pull-up unit 303 and T2 is large (that is L1 > L2) also, and the N-type transistor T 3 of drop-down unit 305 and the passage length L1 of T4 can be in fact precharge unit 301 and the N-type transistor T 1 of pull-up unit 303 and the passage length L2 of T2 1.01 times to 4 times.
Clearer, Fig. 5 illustrates the i level shift register SR into the present invention's one one exemplary embodiment
ithe experimental waveform figure of middle node Q.Please merge with reference to Fig. 3 and Fig. 5, from Fig. 5, can know and find out, when time T pre, node Q can be carried out precharge.In addition, three curve A, B and C in the interval of time T out, have been illustrated respectively.Wherein, curve A is expressed as the N-type transistor T 3 of drop-down unit 305 and the passage length L1 of T4 equals under the N-type transistor T 1 of precharge unit 301 and pull-up unit 303 and the condition of the passage length L2 of T2 (that is L1=L2), and N-type transistor T 1 and T2 are subject to the effect of N-type transistor T 3 and the leakage current of T4 in subcritical district.Curve B is expressed as the N-type transistor T 3 of drop-down unit 305 and the passage length L1 of T4 and is slightly larger than under precharge unit 301 and the N-type transistor T 1 of pull-up unit 303 and the condition of the passage length L2 of T2 (that is L1 > L2), and N-type transistor T 1 and T2 are subject to the effect of N-type transistor T 3 and the leakage current of T4 in subcritical district.Curve C is expressed as the N-type transistor T 3 of drop-down unit 305 and the passage length L1 of T4 under precharge unit 301 and the N-type transistor T 1 of pull-up unit 303 and the condition of the passage length L2 of T2 (that is L1 > > L2), and N-type transistor T 1 and T2 are subject to the effect of N-type transistor T 3 and the leakage current of T4 in subcritical district.
Hence one can see that, when the N-type transistor T 3 of drop-down unit 305 and the passage length L1 of T4 equal precharge unit 301 with the N-type transistor T 1 of pull-up unit 303 and the passage length L2 of T2, N-type transistor T 1 is subject to N-type transistor T 3 with T2 can be more serious with the effect of the leakage current of T4 in subcritical district, that is curve A is maximum in voltage drop (voltage drop) amplitude of time T out.Therefore, i level shift register SR
ivery possible normal output scanning signal SS
i.
In addition, when the N-type transistor T 3 of drop-down unit 305 and the passage length L1 of T4 are more greater than precharge unit 301 with the N-type transistor T 1 of pull-up unit 303 and the passage length L2 of T2, N-type transistor T 1 is subject to N-type transistor T 3 with T2 and can more eases up with the effect of the leakage current of T4 in subcritical district, that is curve B and C can more and more ease up for curve A in the voltage drop amplitude of time tout.Therefore, can guarantee i level shift register SR
ibe able to normal output scanning signal SS
i.
In sum, the present invention is mainly that in the ratio shift register by the transistorized passage length of the N-type of being responsible for stopping output scanning signal in shift register is made, to be responsible for the transistorized passage length of N-type of output scanning signal also large, so as to being responsible for the effect of N-type transistor that the N-type transistor of output scanning signal is subject to being responsible in shift register the stopping output scanning signal leakage current in subcritical district in the shift register that eases up, thereby guarantee that shift register is able to normal output scanning signal.
In addition, although above-mentioned one exemplary embodiment has proposed a certain circuit of precharge unit, pull-up unit and drop-down unit in shift register, implement aspect, the present invention is not restricted to this.That is to say, as long as can be had by differentiation other circuit embodiments of precharge unit, pull-up unit and drop-down unit in shift register, the present invention just can strengthen the transistorized passage length of all or part N-type in its drop-down unit, so as to being responsible for the effect of N-type transistor that the N-type transistor of output scanning signal is subject to being responsible in shift register the stopping output scanning signal leakage current in subcritical district in the shift register that eases up.
Certainly; the present invention also can have other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (18)
1. a shift LD device, is characterized in that, comprising:
Multi-stage serial connection shift register together, wherein i level shift register comprises:
One precharge unit, at least has a first transistor, receives one first sweep signal that i-1 level shift register is exported, and exports according to this charging signals, and i is positive integer;
One pull-up unit, at least has a transistor seconds, couples this precharge unit, receives this charging signals and one first clock signal, and exports according to this one second sweep signal; And
One drop-down unit, at least there is one the 3rd transistor AND gate 1 the 4th transistor, couple this precharge unit and this pull-up unit, receive one the 3rd sweep signal that one second clock signal and (i+1) level shift register are exported, and determine whether this second sweep signal is pulled down to a reference potential according to this
Wherein, the 3rd transistor AND gate the 4th transistor in this drop-down unit has a first passage length, described the first transistor in this precharge unit and this pull-up unit and transistor seconds have respectively a second channel length, this first passage length is greater than this second channel length, and described first passage length is 1.01 times to 4 times of described second channel length, so as to guaranteeing that shift register is able to normal output scanning signal.
2. shift LD device according to claim 1, is characterized in that, this first transistor in this precharge unit is one first N-type transistor,
Wherein, together with the transistorized grid of this first N-type is coupled in source electrode, to receive this first sweep signal, the transistorized drain electrode of this first N-type is in order to export this charging signals.
3. shift LD device according to claim 2, is characterized in that, this transistor seconds in this pull-up unit is one second N-type transistor,
Wherein, the transistorized grid of this second N-type couples the transistorized drain electrode of this first N-type, and the transistorized source electrode of this second N-type is in order to receive this first clock signal, and the transistorized drain electrode of this second N-type is in order to export this second sweep signal.
4. shift LD device according to claim 3, is characterized in that, has more an electric capacity in this pull-up unit, and it is coupled between the transistorized grid of this second N-type and drain electrode.
5. shift LD device according to claim 3, is characterized in that, the 3rd transistor in this drop-down unit is one the 3rd N-type transistor,
Wherein, the transistorized grid of the 3rd N-type is in order to receive this second clock signal, and the transistorized source electrode of the 3rd N-type couples the transistorized drain electrode of this second N-type, and the transistorized drain electrode of the 3rd N-type is coupled to this reference potential.
6. shift LD device according to claim 5, is characterized in that, the 4th transistor in this drop-down unit is one the 4th N-type transistor,
Wherein, the transistorized grid of the 4th N-type is in order to receive the 3rd sweep signal, and the transistorized source electrode of the 4th N-type couples the transistorized grid of this second N-type, and the transistorized drain electrode of the 4th N-type is coupled to this reference potential.
7. shift LD device according to claim 6, is characterized in that, this first with this second N-type transistor there is respectively this second channel length, and the 3rd with the 4th N-type transistor there is respectively this first passage length.
8. shift LD device according to claim 7, it is characterized in that, the 3rd with transistorized this first passage length of the 4th N-type be greater than this first with transistorized this second channel length of this second N-type, and the 3rd with transistorized this first passage length of the 4th N-type be essentially this first with 1.01 times to 4 times of transistorized this second channel length of this second N-type.
9. shift LD device according to claim 1, is characterized in that, this first with the phase differential of this second clock signal be 180 degree.
10. a liquid crystal display, is characterized in that, comprising:
One display panels, comprises a substrate and a shift LD device, and this shift LD device is directly configured on this substrate, and has multi-stage serial connection shift register together, and wherein i level shift register comprises:
One precharge unit, at least has a first transistor, receives one first sweep signal that i-1 level shift register is exported, and exports according to this charging signals, and i is positive integer;
One pull-up unit, at least has a transistor seconds, couples this precharge unit, receives this charging signals and one first clock signal, and exports according to this one second sweep signal; And
One drop-down unit, at least there is one the 3rd transistor AND gate 1 the 4th transistor, couple this precharge unit and this pull-up unit, receive one the 3rd sweep signal that one second clock signal and i+1 level shift register are exported, and determine whether this second sweep signal is pulled down to a reference potential according to this
Wherein, the 3rd transistor AND gate the 4th transistor in this drop-down unit has a first passage length, described the first transistor in this precharge unit and this pull-up unit and transistor seconds have respectively a second channel length, this first passage length is greater than this second channel length, and described first passage length is 1.01 times to 4 times of described second channel length, so as to guaranteeing that shift register is able to normal output scanning signal; And
One backlight module, provides this display panels required backlight.
11. liquid crystal display according to claim 10, is characterized in that, this first transistor in this precharge unit is one first N-type transistor,
Wherein, together with the transistorized grid of this first N-type is coupled in source electrode, to receive this first sweep signal, the transistorized drain electrode of this first N-type is in order to export this charging signals.
12. liquid crystal display according to claim 11, is characterized in that, this transistor seconds in this pull-up unit is one second N-type transistor,
Wherein, the transistorized grid of this second N-type couples the transistorized drain electrode of this first N-type, and the transistorized source electrode of this second N-type is in order to receive this first clock signal, and the transistorized drain electrode of this second N-type is in order to export this second sweep signal.
13. liquid crystal display according to claim 12, is characterized in that, have more an electric capacity in this pull-up unit, and it is coupled between the transistorized grid of this second N-type and drain electrode.
14. liquid crystal display according to claim 12, is characterized in that, the 3rd transistor in this drop-down unit is one the 3rd N-type transistor,
Wherein, the transistorized grid of the 3rd N-type is in order to receive this second clock signal, and the transistorized source electrode of the 3rd N-type couples the transistorized drain electrode of this second N-type, and the transistorized drain electrode of the 3rd N-type is coupled to this reference potential.
15. liquid crystal display according to claim 14, is characterized in that, the 4th transistor in this drop-down unit is one the 4th N-type transistor,
Wherein, the transistorized grid of the 4th N-type is in order to receive the 3rd sweep signal, and the transistorized source electrode of the 4th N-type couples the transistorized grid of this second N-type, and the transistorized drain electrode of the 4th N-type is coupled to this reference potential.
16. liquid crystal display according to claim 15, is characterized in that, this first with this second N-type transistor there is respectively this second channel length, and the 3rd with the 4th N-type transistor there is respectively this first passage length.
17. liquid crystal display according to claim 16, it is characterized in that, the 3rd with transistorized this first passage length of the 4th N-type be greater than this first with transistorized this second channel length of this second N-type, and the 3rd with transistorized this first passage length of the 4th N-type be essentially this first with 1.01 times to 4 times of transistorized this second channel length of this second N-type.
18. liquid crystal display according to claim 10, is characterized in that, this first with the phase differential of this second clock signal be 180 degree.
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| CN103915074A (en) * | 2014-03-31 | 2014-07-09 | 上海天马有机发光显示技术有限公司 | Shifting register unit, grid driving device and display panel |
| CN104599624A (en) * | 2015-03-02 | 2015-05-06 | 京东方科技集团股份有限公司 | Shifting register, driving method thereof and grid drive circuit |
| CN108010494A (en) * | 2016-10-31 | 2018-05-08 | 乐金显示有限公司 | Gate drivers and the display device using the gate drivers |
| WO2020118847A1 (en) * | 2018-12-11 | 2020-06-18 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
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| CN103915074A (en) * | 2014-03-31 | 2014-07-09 | 上海天马有机发光显示技术有限公司 | Shifting register unit, grid driving device and display panel |
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| US9799262B2 (en) | 2015-03-02 | 2017-10-24 | Boe Technology Group Co., Ltd. | Shift register and driving method thereof, gate driving circuit |
| CN108010494A (en) * | 2016-10-31 | 2018-05-08 | 乐金显示有限公司 | Gate drivers and the display device using the gate drivers |
| WO2020118847A1 (en) * | 2018-12-11 | 2020-06-18 | 深圳市华星光电半导体显示技术有限公司 | Display device and driving method thereof |
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Application publication date: 20140115 |