CN107331295B

CN107331295B - Display panel

Info

Publication number: CN107331295B
Application number: CN201610284602.3A
Authority: CN
Inventors: 程长江; 江建学; 陈柏锋
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2016-04-29
Filing date: 2016-04-29
Publication date: 2020-10-27
Anticipated expiration: 2036-04-29
Also published as: CN107331295A

Abstract

A display panel includes a substrate, a plurality of data lines, a plurality of gate lines, a power line, and a gate driving circuit. The power line is coupled to a voltage source. The gate driving circuit is disposed in a visible area of the display panel, coupled to the gate lines and the power lines, and generates a plurality of gate driving signals according to a start pulse. The gate line is formed of a first metal layer on the substrate, the data line is formed of a second metal layer over the first metal layer, the power line is formed of a third metal layer over the second metal layer, and a projection area of at least one of the data lines on the substrate overlaps a projection area of the power line on the substrate.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel including a gate driving circuit disposed in a visible region.

Background

In a general display, a driving circuit is an important driving element. In the conventional technology, a driving chip is used as a driving circuit of a panel. In recent years, an Integrated Gate driver (Integrated Gate driver) has been developed, in which a Gate driver circuit is formed on a panel, and this technology is also called a Gate driver on panel (GOP).

Since the development of GOP technology, it is common practice to integrate GOP circuits in the frame regions on both sides of the substrate. However, this method occupies the frame space on both sides of the panel, so that the frame has a considerable width. However, for the products such as mobile communication devices, wearable devices, and vehicle center control panels, the design of very narrow frames and non-rectangular panels is becoming a product trend, so if the narrow frames and non-rectangular panels are required to be implemented on the display module, the conventional way of designing the GOP circuit on the frame has certain limitations and difficulties.

Therefore, a novel circuit design and layout is needed to achieve the very narrow frame design requirement.

Disclosure of Invention

The invention discloses a display panel, which comprises a plurality of data lines, a plurality of gate lines, a power line and a gate driving circuit. The power line is coupled to a voltage source. The gate driving circuit is disposed in a visible area of the display panel, coupled to the gate lines and the power lines, and generates a plurality of gate driving signals according to a start pulse. The gate line is formed of a first metal layer on a substrate, the data line is formed of a second metal layer over the first metal layer, the power line is formed of a third metal layer over the second metal layer, and a projection area of at least one of the data lines on the substrate overlaps a projection area of the power line on the substrate.

The invention also discloses a display panel, which comprises a plurality of gate lines, a plurality of clock signal lines and a gate driving circuit. The clock signal line is used for providing a plurality of clock signals. The gate driving circuit is disposed in a visible area of the display panel, coupled to the gate lines and the clock signal lines, and generates a plurality of gate driving signals according to a start pulse. The gate lines and the clock signal lines are formed of a first metal layer on a substrate, and the gate lines are parallel to the clock signal lines.

The present invention also discloses a display panel, which includes a plurality of data lines, a plurality of gate lines, a plurality of clock signal lines, a power line and a gate driving circuit. The clock signal line is used for providing a plurality of clock signals. The power line is coupled to a voltage source. The gate driving circuit is disposed in a visible area of the display panel, coupled to the gate lines, the clock signal line and the power line, and generates a plurality of gate driving signals according to a start pulse. The gate line and the clock signal line are formed by a first metal layer, the gate line is parallel to the clock signal line, the data line is formed by a second metal layer, and the power line is formed by a third metal layer.

Drawings

FIG. 1 is a block diagram of a display device according to an embodiment of the invention.

Fig. 2 is a diagram illustrating a gate driving circuit structure disposed in a visible area of a display panel according to an embodiment of the first aspect of the present invention.

Fig. 3 is a top view of an exemplary electronic device according to an embodiment of the invention.

Fig. 4 is a block diagram of a primary driving unit according to an embodiment of the first aspect of the present invention.

Fig. 5 is a circuit diagram showing a digital driving unit according to a first embodiment of the first aspect of the present invention.

Fig. 6 is a diagram illustrating signal waveforms according to an embodiment of the invention.

Fig. 7 is a top view of a layout of a block of a pixel matrix according to an embodiment of the invention.

Fig. 8A is a layout perspective view showing a block of the pixel matrix according to an embodiment of the invention.

Fig. 8B is a cross-sectional layout diagram illustrating a driving unit circuit region in the visible region of the display panel according to an embodiment of the invention.

Fig. 9A is a top view of an exemplary electronic device according to an embodiment of the invention.

Fig. 9B is a cross-sectional view illustrating a layout of a non-driving unit circuit region in a visible region of a display panel according to an embodiment of the invention.

Fig. 10A is a circuit diagram showing a digital driving unit according to a second embodiment of the first aspect of the present invention.

Fig. 10B is a circuit diagram showing a digital driving unit according to a third embodiment of the first aspect of the present invention.

Fig. 11A is a schematic diagram illustrating a gate driving circuit and clock signals according to a fourth embodiment of the first aspect of the present invention.

Fig. 11B is a diagram showing signal waveforms according to the fourth embodiment of the first aspect of the present invention.

Fig. 12 is a block diagram illustrating an nth-stage driving unit according to an embodiment of the second aspect of the present invention.

Fig. 13A is a circuit diagram showing a several-stage driving unit according to the first embodiment of the second aspect of the present invention.

Fig. 13B is a diagram showing signal waveforms according to the first embodiment of the second aspect of the present invention.

Fig. 14A is a circuit diagram showing a several-stage driving unit according to a second embodiment of the second aspect of the present invention.

Fig. 14B is a diagram showing signal waveforms according to the second embodiment of the second aspect of the present invention.

Fig. 15A is a circuit diagram showing a several-stage driving unit according to a third embodiment of the second aspect of the present invention.

Fig. 15B is a circuit diagram showing a several-stage driving unit according to a fourth embodiment of the second aspect of the present invention.

Fig. 16A is a diagram showing signal waveforms according to a sixth embodiment of the second aspect of the present invention.

Fig. 16B is a diagram showing another signal waveform according to the sixth embodiment of the second aspect of the present invention.

Fig. 16C is a diagram showing still another signal waveform according to the sixth embodiment of the second aspect of the present invention.

FIG. 17 is a schematic diagram illustrating a gate driving circuit structure disposed in a viewing area of a display panel according to another embodiment of the invention.

Fig. 18 is a layout top view showing a block of a pixel matrix according to another embodiment of the invention.

FIG. 19A is a waveform diagram illustrating exemplary clock and gate driving signals when parasitic capacitance is small.

FIG. 19B is a waveform diagram illustrating an exemplary clock signal and gate driving signal when parasitic capacitance is large.

Fig. 20 is a diagram showing the structure of a gate driving circuit according to the first embodiment of the third aspect of the present invention.

Fig. 21 is a diagram showing signal waveforms according to the first embodiment of the third aspect of the present invention.

FIG. 22 shows an example of ripple of the gate driving signal.

[ notation ] to show

100-a display device;

101-a display panel;

102-an input unit;

110 to a gate drive circuit;

120-a data driving circuit;

130-pixel matrix;

140-control chip;

200. 200', 1700, AA to visible area;

200-1, 200-2, 200-3, 210, 220, 2201-ripple waves;

310. 320-driving unit circuit area;

500. 1500, GOP _ E, GOP _ F, GOP _ M-drive unit;

501. 1501-pull-up control circuit;

502. 1502-a pull-up output circuit;

503. 1503 to a pull-down control circuit;

504. 1504-1, 1504-2 pull-down output circuits;

active-semiconductor Active layer;

BP1, BP2, BP 3-insulation layer;

cb (n), Cb (n +1), Cccom, Ccp, Cxcg, Cxcv-capacitances;

CE-common electrode;

CK. CK1, CK2, CK3, CK4, CK5, CKA, CKB, CKC, CKD, CKA _ E, CKB _ E, CKA _ F, CKB _ F, CKA _ M, CKB _ M, CLK to a clock signal line;

DL, DL (1), DL (2), DL (3), DL (4), DL (5), DL (6) to data lines;

GE-grid electrode;

GI to a gate dielectric layer;

GL, GL (1), GL (2), GL (3), GL (4), GL (n-1), GL (n +1) -gate lines;

m1, M2, M3-metal layer;

GOUT-grid drive signal; PFA to a planarization layer;

PE-pixel electrode;

RESET to RESET signal;

SD-source/drain;

STV, STV1, STV 2-initial pulse;

t1(n), T1(n +1), T2(n), T2(n +1), T3(n), T3(n +1), T4(n-1), T4(n), T4(n +1), T4a (n), T4a (n +1) -transistors;

VSS to power line.

Detailed Description

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

FIG. 1 is a block diagram of a display device according to an embodiment of the invention. As shown, the display device 100 may include a display panel 101, a data driving circuit 120 and a control chip 140. The display panel 101 includes a gate driving circuit 110 and a pixel matrix 130, wherein the gate driving circuit 110 is disposed in the pixel matrix 130. The pixel matrix 130 includes a plurality of pixel units, each coupled to a set of gate lines and data lines. The gate driving circuit 110 is used for generating corresponding gate driving signals on a plurality of gate lines to drive the pixel units. The data driving circuit 120 is configured to generate corresponding data driving signals on a plurality of data lines to provide image data to the pixel units. The control chip 140 is used for generating a plurality of timing signals, including a clock signal, a reset signal, a start pulse, and the like.

In addition, the display device 100 may further include an input unit 102. The input unit 102 is used for receiving an image signal and outputting the image signal to the control chip 140. According to an embodiment of the present invention, the display device 100 can be applied to an electronic device, wherein the electronic device has various embodiments, including: a mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desktop computer, a television, an automotive display, a portable compact disc player, or any device that includes an image display function.

It is noted that in some embodiments of the present invention, the data driving circuit of the display device may be integrated into the control chip 140. In these embodiments, image data may be provided to the pixel matrix 130 through the control chip 140. Therefore, the architecture shown in FIG. 1 is only one of many embodiments of the present invention, and is not intended to limit the scope of the present invention.

Generally, a display panel includes a visible Area (AA) and a Frame Area (Frame Area). According to an embodiment of the invention, the gate driving circuit 110 is disposed in the visible region of the display panel 101. Various gate driving circuits proposed by the present invention will be described in more detail below.

According to the first aspect of the present invention, all elements of the gate driving circuit 110 are disposed within the visible region of the display panel 101.

Fig. 2 is a diagram illustrating a gate driving circuit structure disposed in a visible area of a display panel according to an embodiment of the first aspect of the present invention. As shown, the gate driving circuit may include a plurality of driving units GOP disposed within a display panel visual area (AA) 200. The gate driving circuit is coupled to at least one power line and at least two clock signal lines, wherein the power line is coupled to a voltage source VSS for providing a reference voltage VGL required by the system, and the clock signal lines are coupled to a clock source for providing at least two clock signals CKA and CKB. The gate driving circuit receives the start pulse STV and the RESET signal RESET through the signal line, generates a plurality of gate driving signals in response to the start pulse STV, and closes the last-stage driving unit GOP through the RESET signal RESET.

According to an embodiment of the present invention, the drive units GOP may form a matrix, wherein one drive unit may be disposed between a plurality of data lines. Therefore, the layout of one driving unit can span several pixel units. For example, in an embodiment of the present invention, as shown in fig. 5, one driving unit may be disposed between 6 data lines, so that the layout of one driving unit may span 5 pixel units. In other words, according to an embodiment of the present invention, for a row (row) of pixel units of the pixel matrix, the number of driving units configured is less than the number of data lines of the display panel. It is noted that in other embodiments of the present invention, one driving unit may be disposed between more than 6 or less than 6 data lines, and thus the present invention is not limited to any one embodiment.

Fig. 3 is a top view of an exemplary electronic device according to an embodiment of the invention, in which the

areas

310 and 320 outlined by dotted lines represent driving unit circuit areas of the gate driving circuit, which may correspond to the driving

unit circuit areas

210 and 220 shown in fig. 2, for illustrating relative positions of two columns (columns) of driving units in the gate driving circuit on a panel visible area of the electronic device.

According to an embodiment of the present invention, the gate driving circuit disposed in the viewing area of the display panel may include N stages of driving units, where N is a positive integer. Fig. 4 is a block diagram of an nth-stage driving unit according to an embodiment of the present invention, wherein N is a positive integer and 0< N ≦ N. The driving unit 500 may include a pull-up control circuit 501, a pull-up output circuit 502, a pull-down control circuit 503, and a pull-down output circuit 504, wherein the pull-up output circuit 502 and the pull-down output circuit 504 are coupled to the nth gate line gl (n) for controlling the output of the gate driving signal. As shown in fig. 4, all elements of the driving unit 500 are disposed in the viewing area of the display panel, and the signal lines are disposed in the bezel area of the display panel.

In the first embodiment of the present invention, since only signal traces are left in the two side frame regions, the design requirement of very narrow frames can be realized, and the design requirement of non-rectangular panels can be further realized.

Fig. 5 is a circuit diagram showing a digital driving unit according to a first embodiment of the first aspect of the present invention. For convenience of illustration, fig. 5 only shows a portion of a column (column) driving unit of the gate driving circuit, wherein the column driving unit, such as the transistors T1(n), T1(n +1), T2(n), T2(n +1), T3(n), T3(n +1), T4(n-1) and T4(n) and the capacitors Cb (n) and Cb (n +1), is disposed between the data lines DL (1) to DL (6), wherein the data lines DL (1) to DL (6) are for illustration only and are not intended to limit the scope of the present invention.

The transistor T1 corresponds to a pull-up output circuit of the driving unit shown in fig. 4, the transistor T2 corresponds to a pull-up control circuit of the driving unit shown in fig. 4, the transistor T3 corresponds to a pull-down control circuit of the driving unit shown in fig. 4, and the transistor T4 corresponds to a pull-down output circuit of the driving unit shown in fig. 4. It should be noted that the pull-up output circuit, the pull-up control circuit, the pull-down control circuit and the pull-down output circuit in the first embodiment of the first aspect are each illustrated as including one transistor, but in other embodiments, the circuits may each include more than one transistor.

According to an embodiment of the present invention, the nth stage driving unit may include transistors T1(n), T2(n), T3(n), T4(n), and a capacitor cb (n). The transistor T1(n) has a first pole coupled to the clock signal line CKA and a second pole coupled to the nth gate line gl (n). The transistor T2(n) has a control electrode and a first electrode coupled to the (n-1) th gate line GL (n-1), and a second electrode coupled to the control electrode of the transistor T1 (n). The transistor T3(n) has a control electrode coupled to the (n +1) th gate line GL (n +1), a first electrode coupled to the second electrode of the transistor T2(n), and a second electrode coupled to the power line VSS. The transistor T4(n) has a control electrode coupled to the clock signal line CKB, a first electrode coupled to the nth gate line gl (n), and a second electrode coupled to the power line VSS.

Fig. 6 is a diagram illustrating signal waveforms according to an embodiment of the invention. When the gate pulse on the gate line GL (n-1) arrives, the transistor T2(n) is turned on, thereby turning on the transistor T1 (n). When the clock pulse on the clock signal line CKA arrives, it is transmitted to the gate line gl (n) through the turned-on transistor T1(n) and output as a gate pulse. When the gate pulse on the gate line GL (n +1) arrives, the transistor T3(n) is turned on, and the voltage of the gate of the transistor T1(n) is pulled down to turn off the transistor T1 (n). Similarly, when the clock pulse on the clock signal line CKB arrives, the transistor T4(n) is turned on, and the voltage of the nth gate line gl (n) is pulled down.

As shown in fig. 5, each stage of the driving unit includes only 4 transistors, and compared with the conventional design in which at least 13 transistors are required in the driving unit, the gate driving circuit provided in the present invention can effectively reduce the loss of the pixel aperture ratio in the visible region.

In addition, in the embodiment of the invention, in order to further reduce the loss of the pixel aperture ratio in the visible region, the layout of the circuit signal lines in the visible region can be further designed.

According to the first embodiment of the present invention, the gate line of the display panel is formed by a first metal layer, the data line is formed by a second metal layer, and the power line coupled to the voltage source VSS is formed by a third metal layer, wherein the first metal layer is formed on a substrate, the second metal layer is formed on the first metal layer, and the third metal layer is formed on the second metal layer, wherein the substrate can be a rigid substrate or a flexible substrate. Since the data line and the power line are formed on different metal layers, the data line and the power line can be overlapped in space (i.e. a projection area of the data line and the power line can be overlapped), thereby reducing the loss of the pixel aperture ratio. Further, according to the first embodiment of the present invention, the clock signal line is formed of the first metal layer and is parallel to the gate line. The contacts between different metal layers may be connected through contact vias (contacts via).

Fig. 7 is a top view of a block layout of a pixel matrix according to an embodiment of the invention, in which a clock signal line CK may represent any one of the clock signal lines according to the invention, e.g., any one of the clock signal lines CKA and CKB, and a data line DL may represent any one of the data lines according to the invention, e.g., any one of the data lines D (1) -D (6). As shown, the clock signal line CK is parallel to the gate lines GL (n), GL (n +1), etc., and the data line DL overlaps a projection area of the power line VSS (therefore, the same line is used to represent the data line DL and the power line VSS in fig. 7).

As shown in fig. 7, since no signal line passes through the pixel electrode opening area, not only a high aperture ratio can be obtained, but also the aperture ratios between the pixel units can be maintained to be uniform, thereby avoiding poor picture quality such as vertical line (vertical line).

Fig. 8A is a layout perspective view showing a block of the pixel matrix according to an embodiment of the invention. PE is the pixel electrode and CE is the common electrode. As shown in fig. 8A, in the design of the present invention, the layout of the clock signal line CLK does not overlap the pixel electrode PE, so that the voltage of the pixel electrode does not have a coupling problem.

Fig. 8B is a cross-sectional layout view of the driving unit circuit region in the visible area of the display panel, which is a cross-sectional layout view along a tangent line from point a to point a' shown in fig. 8A. As shown in fig. 8B, metal layers are sequentially formed on the substrate, wherein GE is a Gate line formed on the first metal layer, GI is a Gate dielectric layer (Gate Insulator), SD is a source/drain of a transistor formed on the second metal layer, Active is a semiconductor Active layer, BP1, BP2 and BP3 are insulating layers, PFA is a planarization layer, PE is a pixel electrode, M3 is a third metal layer, CE is a common electrode, and the pixel electrode PE and the common electrode CE are made of transparent conductive oxides, such as Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), fluorine doped tin oxide (FTO), aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO). According to an embodiment of the present invention, since the power line coupled to the voltage source VSS is formed by the third metal layer, the third metal layer is used for transmitting the voltage signal of the voltage source VSS in the driving unit circuit region.

It should be noted that the layout stacking manner shown in fig. 8B is only one of various embodiments of the present invention, and is used for illustrating the concept of the present invention, but not for limiting the scope of the present invention.

In addition, the third metal layer can also be used in conjunction with the application of an in-cell (touch in cell) technology, and the third metal layer is connected with the common electrode CE to transmit touch sensing signals, so that the applicability and added value of the product are improved.

Fig. 9A is a top view of an exemplary electronic device according to an embodiment of the invention. Fig. 9B is a cross-sectional view illustrating a layout of a non-driving unit circuit region in a visible region of a display panel according to an embodiment of the invention. As shown in fig. 9A, the common electrode CE can be used as a touch sensing electrode in the visible area of the display panel for sensing capacitance variation. As shown in fig. 9B, with the provision of the third metal layer, the third metal layer M3 is connected to the common electrode CE through the contact hole in the non-driving cell circuit region.

As described above, in the first embodiment of the present invention, the clock signal line is formed of the first metal layer and is parallel to the gate line. In other embodiments of the present invention, the clock signal line may be formed of other metal layers.

According to the second embodiment of the present invention, the gate lines of the display panel are formed of the first metal layer M1, the data lines are formed of the second metal layer M2, the power lines coupled to the voltage source VSS are formed of the third metal layer M3, and the clock signal lines may instead be formed of the second metal layer M2 and parallel to the data lines.

Fig. 10A is a circuit diagram showing a digital driving unit according to a second embodiment of the first aspect of the present invention. For convenience of explanation, fig. 10A shows only a part of a column (column) driving unit of the gate driving circuit, and the data lines DL (1) to DL (6) are for explanation only and do not limit the scope of the present invention.

As shown, the clock signal lines CKA and CKB are parallel to and spaced apart from the data lines.

In addition, according to the third embodiment of the present invention, the gate lines of the display panel are formed of the first metal layer M1, the data lines are formed of the second metal layer M2, the power source lines coupled to the voltage source VSS are formed of the third metal layer M3, and the clock signal lines may instead be formed of the third metal layer M3 and overlap the data lines.

Fig. 10B is a circuit diagram showing a digital driving unit according to a third embodiment of the first aspect of the present invention. For convenience of explanation, fig. 10B shows only a part of a column (column) driving unit of the gate driving circuit, and the data lines DL (1) to DL (6) are for explanation only and do not limit the scope of the present invention.

As shown, the clock signal lines CKA and CKB are spaced apart from and parallel to the power lines coupled to the voltage source VSS and overlap the data lines. Note that, in order to show the connection points of the transistor and the clock signal line and the transistor and the power source line, the data line and the power source line which are overlapped with each other or the data line and the clock signal line which are overlapped with each other are drawn separately in fig. 5, 10A, and 10B. However, it must be understood that when the data line and the power line, or the data line and the clock signal line are formed in different metal layers, the wirings thereof may be spatially overlapped such that the projection areas thereof overlap as shown in fig. 7 and 8B. In addition, it should be noted that in other embodiments of the present invention, the data lines, the power lines and the clock signal lines of different metal layers may or may not be spatially overlapped, and therefore the layout of the present invention is not limited to the above-mentioned embodiments.

According to the fourth embodiment of the present invention, the number of clock signals can be increased to reduce the duty cycle of the transistors in the driving unit.

Fig. 11A is a schematic diagram illustrating a gate driving circuit according to a fourth embodiment of the first aspect of the present invention. As shown, each stage of driving units in the gate driving circuit may be coupled to the clock signal lines CKA, CKB, CKC, and CKD, respectively, and may continue to cycle in this order.

Fig. 11B is a diagram showing signal waveforms according to the fourth embodiment of the first aspect of the present invention. As shown, after the start pulse STV arrives, the clock signal lines CKA, CKB, CKC and CKD sequentially provide non-overlapping clock pulses, which are sequentially outputted from the gate lines GL (1), GL (2), GL (3) and GL (4), and the duty cycle of the transistors in the driving unit (e.g., the transistors T1 and T4) can be reduced from 50% to 25% compared to the embodiments shown in fig. 5 and 6. Therefore, the time for the transistor element in the driving unit to be biased can be reduced, and the reliability of the circuit is effectively improved.

As described above, in the first aspect of the present invention, all the elements of the gate driving circuit 110 are disposed within the visible region of the display panel 101. In the second aspect of the present invention, some components of the gate driving circuit 110 may be disposed in the frame region of the display panel 101.

Fig. 12 is a block diagram of an nth-stage driving unit according to an embodiment of the second aspect of the present invention, wherein N is a positive integer and 0< N ≦ N. The driving unit 1500 may include a pull-up control circuit 1501, a pull-up output circuit 1502, a pull-down control circuit 1503 and pull-down output circuits 1504-1 and 1504-2, wherein the pull-up output circuit 1502 and the pull-down output circuits 1504-1 and 1504-2 are coupled to the nth gate line gl (n) for controlling the output of the gate driving signal. As shown in FIG. 12, the pull-down output circuits 1504-1 and 1504-2 and the signal lines of the driving unit 1500 are disposed in the frame area of the display panel.

Fig. 13A is a circuit diagram showing a several-stage driving unit according to the first embodiment of the second aspect of the present invention, in which a transistor T1 corresponds to the pull-up output circuit of the driving unit shown in fig. 12, a transistor T2 corresponds to the pull-up control circuit of the driving unit shown in fig. 12, a transistor T3 corresponds to the pull-down control circuit of the driving unit shown in fig. 12, and transistors T4 and T4a correspond to the pull-down output circuit of the driving unit shown in fig. 12. It should be noted that the pull-up output circuit, the pull-up control circuit, the pull-down control circuit and the pull-down output circuit of the first embodiment of the second aspect are each illustrated as including one transistor, but in other embodiments, the aforementioned circuits may each include more than one transistor. For the sake of convenience, fig. 13A only shows a part of a column (column) driving unit of the gate driving circuit, wherein some components of the column driving unit, such as the transistors T1(n), T1(n +1), T2(n), T2(n +1), T3(n), T3(n +1) and the capacitors Cb (n) and Cb (n +1), are disposed between the data lines DL (1) to DL (5), and other components, such as the transistors T4(n), T4(n +1), T4a (n) and T4a (n +1), are disposed in the frame region. The data lines DL (1) to DL (5) are only for illustration and not for limiting the scope of the present invention.

According to an embodiment of the present invention, the nth stage driving unit may include transistors T1(n), T2(n), T3(n), T4(n), T4a (n), and a capacitor cb (n). The coupling of the transistors T1(n) -T3 (n) is the same as the embodiment shown in fig. 5, and will not be described again here. In this embodiment, the transistor T4(n) has a control electrode coupled to the clock signal line CK1, a first electrode coupled to the nth gate line gl (n), and a second electrode coupled to the power line VSS, and the transistor T4a (n) is coupled in the same manner as the transistor T4 (n).

Fig. 13B is a diagram showing signal waveforms according to the first embodiment of the second aspect of the present invention. When the gate pulse on the gate line GL (n-1) arrives, the transistor T2(n) is turned on, thereby turning on the transistor T1 (n). When the clock pulse on the clock signal line CKA arrives, it is transmitted to the gate line gl (n) through the turned-on transistor T1(n) and output as a gate pulse. When the gate pulse on the gate line GL (n +1) arrives, the transistor T3(n) is turned on, and the voltage of the gate of the transistor T1(n) is pulled down to turn off the transistor T1 (n). Similarly, when the clock pulse on the clock signal line CK1 arrives, the transistors T4(n) and T4a (n) are turned on, and the voltage of the nth gate line gl (n) is pulled down.

It should be noted that although two clock signal lines CK1 and CK2 are added in fig. 13A for providing clock signals to the transistors T4(n) and T4a (n) disposed in the frame region, the invention is not limited thereto. In other embodiments of the present invention, the transistors T4(n) and T4A (n) disposed in the frame region may also be coupled to the clock signal line CKB as shown in fig. 14A, 15A and 15B. In other words, in other embodiments of the present invention, the transistors disposed in the frame area and the transistors disposed in the visible area may be coupled to the same clock signal line.

In the first embodiment of the second aspect of the present invention, the clock signal line is formed of the first metal layer M1, and is parallel to the gate line in the visible region as shown in fig. 13A, as in the first embodiment of the first aspect of the present invention. In other embodiments of the present invention, the clock signal line may be formed of other metal layers.

Fig. 14A is a circuit diagram showing a several-stage driving unit according to a second embodiment of the second aspect of the present invention. The circuit shown in fig. 14A is the same as the circuit shown in fig. 13A, except that the transistors T4(n) and T4A (n) disposed in the frame region are coupled to the clock signal line CKB, and the transistors T4(n +1) and T4A (n +1) disposed in the frame region are coupled to the clock signal line CKA. Fig. 14B is a diagram showing signal waveforms according to the second embodiment of the second aspect of the present invention. It is noted that the signal waveforms shown in FIG. 14B can also be shared by the circuits of FIG. 15A and FIG. 15B.

In the third embodiment of the second aspect of the present invention, the gate lines of the display panel are formed of the first metal layer M1, the data lines are formed of the second metal layer M2, the power source lines coupled to the voltage source VSS are formed of the third metal layer M3, and the clock signal lines may instead be formed of the second metal layer M2 and parallel to the data lines.

Fig. 15A is a circuit diagram showing a several-stage driving unit according to a third embodiment of the second aspect of the present invention. For convenience of explanation, fig. 15A shows only a part of a column (column) driving unit of the gate driving circuit, and the data lines DL (1) to DL (5) are for explanation only and do not limit the scope of the present invention.

As shown, the clock signal lines CKA/CKB are parallel to and spaced apart from the data lines.

In addition, in the fourth embodiment of the second aspect of the present invention, the gate lines of the display panel are formed of the first metal layer M1, the data lines are formed of the second metal layer M2, the power source lines coupled to the voltage source VSS are formed of the third metal layer M3, and the clock signal lines may instead be formed of the third metal layer M3 and overlap the data lines.

Fig. 15B is a circuit diagram showing a several-stage driving unit according to a fourth embodiment of the second aspect of the present invention. For convenience of explanation, fig. 15B shows only a part of a column (column) driving unit of the gate driving circuit, and the data lines DL (1) to DL (5) are for explanation only and do not limit the scope of the present invention.

As shown, the clock signal lines CKA/CKB are spaced apart from and parallel to the power lines coupled to the voltage source VSS, and overlap the data lines. Note that, in order to show the connection points of the transistor and the clock signal line and the transistor and the power source line, the data line and the power source line which are provided to overlap with each other, or the data line and the clock signal line which are provided to overlap with each other are drawn separately in fig. 13A, 14A, 15A, and 15B. However, it must be understood that when the data line and the power line, or the data line and the clock signal line are formed in different metal layers, the wirings thereof may be spatially overlapped such that the projection areas thereof overlap as shown in fig. 7 and 8B. In addition, it should be noted that in other embodiments of the present invention, the data lines, the power lines and the clock signal lines of different metal layers may or may not be spatially overlapped, and therefore the layout of the present invention is not limited to the above-mentioned embodiments.

In addition, in the fifth embodiment of the second aspect of the present invention, the number of clock signals in the visible area can also be increased to two or more as shown in fig. 11A, so as to reduce the duty cycle of the transistors in the visible area.

In addition, in the sixth embodiment of the second aspect of the present invention, when the device of the driving unit disposed in the frame area and the device disposed in the visible area are coupled to different clock signal lines as shown in fig. 13A, the number of clock signals provided to the device disposed in the frame area may be increased to reduce the duty cycle of the transistor in the frame area.

Fig. 16A is a diagram showing signal waveforms according to a sixth embodiment of the second aspect of the present invention, which is an embodiment of adding one more clock signal line CK3 to the first embodiment of the second aspect shown in fig. 13A. As shown, the clock lines CK1, CK2, and CK3 sequentially provide non-overlapping clock pulses to the transistors T4 and T4a of different stages, so that the duty cycle of the transistors (e.g., the transistors T4 and T4a) disposed in the frame region can be reduced from 50% to 33% compared to the embodiment shown in fig. 13B.

FIG. 16B is a diagram showing another signal waveform according to the sixth embodiment of the second aspect of the present invention, which is an embodiment of the first embodiment of the second aspect of FIG. 13A with two more clock signal lines CK3 and CK 4. As shown, the clock lines CK1, CK2, CK3 and CK4 sequentially provide non-overlapping clock pulses to the transistors T4 and T4a of different stages, so that the duty cycle of the transistors (e.g., the transistors T4 and T4a) disposed in the frame region can be reduced from 50% to 25% compared to the embodiment shown in fig. 13B.

FIG. 16C is a diagram showing still another signal waveform according to the sixth embodiment of the second aspect of the present invention, which is an embodiment of the first embodiment of the second aspect shown in FIG. 13A with the addition of three clock signal lines CK3, CK4 and CK 5. As shown, the clock lines CK1, CK2, CK3, CK4 and CK5 sequentially provide non-overlapping clock pulses to the transistors T4 and T4a of different stages, so that the duty cycle of the transistors (e.g., the transistors T4 and T4a) disposed in the frame region can be reduced from 50% to 20% as compared to the embodiment shown in fig. 13B.

Therefore, according to the sixth embodiment of the second aspect of the present invention, the time for the transistor elements in the frame region to be biased can be reduced, thereby effectively increasing the circuit reliability.

The example shown above. For example, although the layout of the clock signal lines CKA and CKB in the visible area 200 is horizontal and the layout of the power line VSS in the visible area 200 is vertical in fig. 2, the invention is not limited thereto.

FIG. 17 is a schematic diagram illustrating a gate driving circuit structure disposed in a viewing area of a display panel according to another embodiment of the invention. As shown, in this embodiment, the clock signal lines CKA and CKB are arranged in the vertical direction in the viewing area 200, and the power line VSS is arranged in the horizontal direction in the viewing area 200.

However, whether the clock signal is connected to the driving unit GOP in a manner of extending horizontally or vertically into the visible region, it cannot be avoided that the driving capability of the clock signal is insufficient in the visible region due to the influence of parasitic capacitance, and the output signal of the gate line is seriously attenuated.

Fig. 18 is a layout top view showing a block of a pixel matrix according to another embodiment of the invention. As shown, the staggered clock signal lines CLKA/CLKB and the power line VSS form a parasitic capacitance Cxcv, the staggered clock signal lines CLKA/CLKB and the gate lines form a parasitic capacitance Cxcg, the clock signal lines CLKA/CLKB and the pixel electrodes through the opening regions form a parasitic capacitance Ccp, and the clock signal lines CLKA/CLKB and the common electrodes through the opening regions form a parasitic capacitance Cccom. When the panel resolution is higher, the parasitic capacitance formed is larger, resulting in the deterioration of the clock signal driving capability.

FIG. 19A is a waveform diagram illustrating exemplary clock and gate driving signals when parasitic capacitance is small. FIG. 19B is a waveform diagram illustrating an exemplary clock signal and gate driving signal when parasitic capacitance is large. As shown in the figure, when the parasitic capacitance is large, the driving capability of the clock signal is deteriorated, and the gate driving signal is severely distorted.

In order to solve the above problem, in a third aspect of the present invention, a novel clock signal trace layout structure and a novel clock signal timing configuration method are provided to disperse the influence of parasitic capacitance on a clock signal.

According to the third aspect of the present invention, the driving unit circuit within the visible area may be divided into a plurality of regions, such as the driving unit circuit region described above. The division of the circuit area is not limited to the vertical or horizontal division. The circuit of each driving unit circuit area is provided with a dedicated clock signal line to drive the corresponding driving unit. For example, in an embodiment of the present invention, the first driving unit circuit region and the second driving unit circuit region within the visible region are driven by different sets of clock signal lines.

Fig. 20 is a diagram showing the structure of a gate driving circuit according to the first embodiment of the third aspect of the present invention. In this embodiment, the driving unit circuit within the visible area 200' is divided into three areas, i.e., the driving unit circuit area 200-1 includes a front driving unit GOP _ F, the driving unit circuit area 200-2 includes a middle driving unit GOP _ M, and the driving unit circuit area 200-3 includes a rear driving unit GOP _ E. Each driving unit circuit region is driven by different clock signals. For example, the driving unit circuit region 200-1 is driven by the first set of clock signals CKA _ F and CKB _ F, the driving unit circuit region 200-2 is driven by the second set of clock signals CKA _ M and CKB _ M, and the driving unit circuit region 200-3 is driven by the third set of clock signals CKA _ E and CKB _ E for evenly distributing parasitic capacitances to the three sets of clock signal lines.

Fig. 21 is a diagram showing signal waveforms according to the first embodiment of the third aspect of the present invention. According to the concept of the third aspect of the present invention, different sets of clock signals are configured in different driving unit circuit regions, and the timing control chip is configured to provide the time-sharing clock signal, so that the parasitic capacitance sensed by the clock signal line can be effectively reduced by only one third of the original parasitic capacitance.

More specifically, different sets of clock signals are distributed to different time output clock pulses for driving the driving units in the corresponding driving unit circuit regions. Taking the structure shown in fig. 20 as an example, the three sets of clock signals output clock pulses at different times in a time-sharing manner as shown in fig. 21. In the interval where the driving unit circuit region 200-3 needs to operate, the clock signals CKA _ E and CKB _ E output clock pulses, and at this time, the states of the clock signals CKA _ M and CKB _ M and CKA _ F and CKB _ F are not output. For example, the voltage levels of the clock signals CKA _ M and CKB _ M and CKA _ F and CKB _ F are pulled down to the level of the reference voltage VGL. When the driving units in the driving unit circuit region 200-3 are operated sequentially, the driving units in the driving unit circuit region 200-2 are operated sequentially. At this time, the clock signals CKA _ M and CKB _ M output clock pulses, and the states of the clock signals CKA _ E and CKB _ E are converted to no output. For example, the voltage levels of the clock signals CKA _ E and CKB _ E and CKA _ F and CKB _ F are pulled down to the level of the reference voltage VGL. When the driving units in the driving unit circuit region 200-2 are operated sequentially, the driving units in the driving unit circuit region 200-1 are operated sequentially. At this time, the clock signals CKA _ F and CKB _ F output clock pulses, and the states of the clock signals CKA _ M and CKB _ M are converted to no output. For example, the voltage levels of the clock signals CKA _ E and CKB _ E and CKA _ M and CKB _ M are pulled down to the level of the reference voltage VGL. In this way, the parasitic capacitance sensed by the clock signal line is only one third of the original parasitic capacitance.

It is noted that, although the driving unit circuit is divided into three regions in the above embodiments for clearly illustrating the concept of the present invention, the present invention is not limited thereto. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, such as dividing the driving unit circuit into two regions, or more than three regions. The division method of the driving unit circuit is not limited to the above-described front, middle, rear, left, middle, and right division method.

In addition, although in the above embodiments, each driving unit circuit region is coupled to two clock signal lines for receiving corresponding clock signals, the invention is not limited thereto. In other embodiments of the present invention, each driving unit circuit region may also be coupled to more than two clock signal lines respectively as shown in fig. 11A, for example, the driving unit GOP shown in fig. 11A may be regarded as a driving unit in the same driving unit circuit region, and the driving units in the driving unit circuit region are coupled to the clock signal lines CKA, CKB, CKC and CKD respectively, and may continuously cycle in this order to reduce the duty cycle of the transistors in the visible region.

Furthermore, it should be noted that the concept described in the third aspect of the present invention can be applied not only to the architecture in which all the elements of the gate driving circuit are disposed in the visible region of the display panel described in the first aspect of the present invention, but also to the architecture in which some of the elements of the gate driving circuit are disposed in the frame region of the display panel described in the second aspect of the present invention, including the embodiment of coupling the transistors disposed in the bezel area and the transistors disposed in the view area to different clock lines as shown in fig. 13A, the embodiment of coupling the transistors disposed in the bezel area and the transistors disposed in the view area to the same clock line as shown in fig. 14A, 15A and 15B, and the embodiment of increasing the number of clock signals supplied to the devices disposed in the bezel area as shown in fig. 16A, 16B and 16C.

In other words, in the clock signal timing configuration method provided in the third aspect of the present invention, in combination with the partition configuration of each group of clock signals and the technique of distributing each group of clock signals to output clock pulses at different times, each group of clock signals is output only when the driving unit circuit region in charge of itself needs to operate, and the rest of the time maintains the voltage at the level of the reference voltage VGL without outputting. Therefore, the parasitic capacitance sensed by the clock signal line can be effectively reduced, the power consumption can be saved, the time for the transistor element in the driving unit to be biased can be reduced, and the circuit reliability can be effectively improved. In addition, the time when the clock signal is not output can also avoid unnecessary ripples generated by the gate driving signal. For example, it is avoided that the gate driving signal GOUT shown in fig. 22 generates a ripple 2201 due to the clock pulse output of the clock signal line CLK when no pulse is required.

The use of ordinal terms such as "first," "second," "third," etc., in the claims to modify an element does not by itself connote any priority, precedence, order of various elements, or order of steps performed by the method, but are used merely as labels to distinguish one element from another element having a same name (but for use of a different ordinal term).

Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A display panel, comprising:

a substrate;

a plurality of data lines;

a plurality of gate lines;

the power line is coupled with a voltage source;

a gate driving circuit disposed in a visible area of the display panel, coupled to the gate lines and the power line, and generating gate driving signals according to a start pulse; and

a plurality of clock signal lines coupled to the gate driving circuit for providing a plurality of clock signals,

wherein the plurality of gate lines are formed of a first metal layer on the substrate, the plurality of data lines are formed of a second metal layer over the first metal layer, the power supply line is formed of a third metal layer over the second metal layer, and a projection area of at least one of the plurality of data lines on the substrate overlaps with a projection area of the power supply line on the substrate, and wherein the plurality of clock signal lines are formed of the first metal layer and are parallel to the plurality of gate lines, and the gate driving circuit is disposed between one of the plurality of gate lines and one of the plurality of clock signal lines.

2. The display panel of claim 1, wherein the plurality of clock signal lines are formed of the third metal layer, the plurality of clock signal lines are parallel to the power supply line, and a projected area of at least one of the plurality of data lines on the substrate overlaps with a projected area of at least one of the plurality of clock signal lines on the substrate.

3. The display panel of claim 1, wherein the gate driving circuit comprises N-stage driving units, and wherein the nth-stage driving unit comprises:

a first transistor having a first electrode coupled to the first clock signal line and a second electrode coupled to the nth gate line;

a second transistor having a control electrode and a first electrode coupled to the (n-1) th gate line, and a second electrode coupled to the control electrode of the first transistor; and

a third transistor having a control electrode coupled to the (n +1) th gate line, a first electrode coupled to the second electrode of the second transistor, and a second electrode coupled to the power line,

where N and N are positive integers and 0< N ≦ N.

4. The display panel of claim 3, wherein the nth stage driving unit further comprises:

a fourth transistor having a control electrode coupled to the second clock signal line, a first electrode coupled to the nth gate line, and a second electrode coupled to the power line.

5. The display panel of claim 3, further comprising:

a fourth transistor having a control electrode coupled to the second clock signal line, a first electrode coupled to the nth gate line, and a second electrode coupled to the power line,

wherein the fourth transistor is disposed in a frame region of the display panel.

6. A display panel, comprising:

a plurality of gate lines;

a plurality of clock signal lines for providing a plurality of clock signals; and

a gate driving circuit disposed in a visible area of the display panel, coupled to the gate lines and the clock signal lines, and generating gate driving signals according to a start pulse,

wherein the gate line and the plurality of clock signal lines are formed of a first metal layer on a substrate, and the plurality of gate lines are parallel to the plurality of clock signal lines, and the gate driving circuit is disposed between one of the plurality of gate lines and one of the plurality of clock signal lines.

7. The display panel of claim 6, further comprising:

a substrate;

the power line is coupled with a voltage source; and

a plurality of data lines for transmitting data signals,

wherein the plurality of data lines are formed of a second metal layer located above the first metal layer, the power line is formed of a third metal layer located above the second metal layer, and a projection area of at least one of the plurality of data lines on the substrate overlaps with a projection area of the power line on the substrate.

8. The display panel of claim 7, wherein the gate driving circuit comprises N-stage driving units, and wherein the nth-stage driving unit comprises:

where N and N are positive integers and 0< N ≦ N.

9. The display panel of claim 8, wherein the nth stage driving unit further comprises:

10. The display panel of claim 7, further comprising:

11. A display panel, comprising:

a plurality of data lines;

a plurality of gate lines;

a plurality of clock signal lines for providing a plurality of clock signals;

the power line is coupled with a voltage source; and

a gate driving circuit disposed in a visible area of the display panel, coupled to the gate lines, the clock signal lines and the power line, and generating gate driving signals according to a start pulse,

wherein the plurality of gate lines and the plurality of clock signal lines are formed of a first metal layer, and the plurality of gate lines are parallel to the plurality of clock signal lines, the plurality of data lines are formed of a second metal layer, the power supply line is formed of a third metal layer, and the gate driving circuit is disposed between one of the plurality of gate lines and one of the plurality of clock signal lines.

12. The display panel of claim 11, wherein the first metal layer is formed on a substrate, the second metal layer is formed over the first metal layer, and the third metal layer is formed over the second metal layer, and a projection area of at least one of the plurality of data lines on the substrate overlaps a projection area of the power line on the substrate.

13. The display panel of claim 11, wherein the gate driving circuit comprises N-stage driving units, and wherein the nth-stage driving unit comprises:

where N and N are positive integers and 0< N ≦ N.

14. The display panel of claim 13, wherein the nth stage driving unit further comprises:

15. The display panel of claim 13, further comprising: