CN104503177A - Array substrate and manufacturing method thereof, and display panel - Google Patents
Array substrate and manufacturing method thereof, and display panel Download PDFInfo
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- CN104503177A CN104503177A CN201410836655.2A CN201410836655A CN104503177A CN 104503177 A CN104503177 A CN 104503177A CN 201410836655 A CN201410836655 A CN 201410836655A CN 104503177 A CN104503177 A CN 104503177A
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- array base
- base palte
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- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000010409 thin film Substances 0.000 claims abstract description 36
- 239000011229 interlayer Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 78
- 238000009413 insulation Methods 0.000 claims description 50
- 239000002184 metal Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000002161 passivation Methods 0.000 claims description 10
- -1 cushion Substances 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
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- 238000012986 modification Methods 0.000 description 3
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- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 241000931705 Cicada Species 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013499 data model Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
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- 229920003023 plastic Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array substrate and a manufacturing method thereof, and a display panel. The array substrate comprises a plurality of grid lines, a plurality of data lines and a plurality of drive leads, wherein the grid lines are in one-to-one correspondence to the drive leads; the data lines and the drive leads are arranged in an interlayer manner; every two adjacent data lines and every two adjacent corresponding grid lines define a pixel area; each pixel area comprises a thin film transistor and a pixel electrode; each pixel electrode is communicated with one of the drain electrode or source electrode of the corresponding thin film transistor; the grid lines are communicated with the grid electrodes of the thin film transistors; the grid lines are communicated with the drive leads, and the drive leads are used for transmitting a driving signal generated by a grid electrode driving circuit to the grid lines; the data lines are communicated with the other one of the source electrode or drain electrode of the corresponding thin film transistor. According to the array substrate and the manufacturing method thereof, and the display panel disclosed by the invention, the aperture rate of a display is increased.
Description
Technical field
The present invention relates to electronic device field, be specifically related to a kind of array base palte and preparation method thereof, display panel.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) owing to there is Micro Energy Lose, low-work voltage, without advantages such as X-radiation, high definition, small sizes, being widely used at present in the portable type electronic product such as mobile phone, palm PC.Under the promotion of market competition, the tft liquid crystal display lighter, display effect is more superior, price is lower receives more and more to be pursued.Thin Film Transistor-LCD can be made to reduce by a driving chip amorphous silicon gate driver and the integrated gate driver technology of active matrix, can effectively make display screen become lighter, reduce costs, and the reliability of display can be increased.
Therefore, gate driver technology progressively becomes the focus of development research in recent years.But, gate driver circuit in current most of display all designs in frame portion, take the position that routine frame is very large, narrow to make the frame of display, gate driver circuit can be designed into the below (i.e. stepped area) of viewing area, to reduce the size of frame, even accomplish Rimless.This method makes to need extra driving lead-in wire to be connected in gate line by the sweep signal of raster data model, drives lead-in wire, how to guarantee that the aperture opening ratio of display is a needs issues that need special attention owing to introducing.Therefore, need badly and a kind ofly can improve the array base palte of display aperture ratio.
Summary of the invention
The embodiment of the present invention provides a kind of array base palte and preparation method thereof, display panel, in order to solve narrow frame or the low problem of Rimless display aperture ratio.
To achieve these goals, embodiments provide a kind of array base palte, comprising:
Many gate lines, a plurality of data lines and many drive lead-in wire, described gate line and describedly drive the one_to_one corresponding that goes between; Described data line and the described interlayer that goes between that drives are arranged; Article two, the gate line that adjacent data line is adjacent with two surrounds a pixel region;
Described pixel region comprises thin film transistor (TFT) and pixel electrode;
Be connected one of in the drain electrode of described pixel electrode and described thin film transistor (TFT) or source electrode;
Described gate line is connected with the grid of described thin film transistor (TFT); Described gate line is connected with described driving lead-in wire, and the described drive singal driving lead-in wire to be used for gate driver circuit produces passes to described gate line;
Described data line is with the source electrode of described thin film transistor (TFT) or in draining, another is connected.
Preferably, the center line of the projection of described data line on array base palte is completely overlapping with the described center line of the projection gone between on array base palte that drives.
Preferably, the projection of described data line on array base palte is overlapping with the described projection section gone between on array base palte that drives.
Preferably, the projection of described data line on array base palte and describedly drive the projection zero lap gone between on array base palte.
Preferably, described gate line with described drive to go between to be connected by the first connecting hole.
Preferably, described data line and described thin film transistor (TFT) source electrode and to drain same layer.
Preferably, described array base palte also comprises a light shield layer, described light shield layer and describedly drive the same layer that goes between.
Preferably, cushion, the first insulation course and the second insulation course is provided with successively between described driving lead-in wire and described data line.
Preferably, described array base palte comprises: be successively set on the light shield layer on substrate, cushion, semiconductor layer, the first insulation course, grid, the second insulation course and the source electrode be connected with described semiconductor layer by the second connecting hole, the 3rd connecting hole and drain electrode.
The embodiment of the present invention additionally provides a kind of method for making of array base palte, and described method comprises:
One substrate is provided;
Substrate arranges the first metal layer and figure dissolve light shield layer and drive lead-in wire;
Set gradually cushion, semiconductor layer and the first insulation course on the substrate, drive described the first connecting hole lead-in wire making and runs through described first insulation course and described cushion;
Arrange the second metal level on the substrate and figure dissolves gate line, described gate line is connected to described driving lead-in wire by described first connecting hole;
Set gradually the second insulation course, the 3rd metal level on the substrate, and figure dissolves source electrode, drain electrode, data line, described data line and described source electrode or be connected one of in draining;
Set gradually passivation layer and transparency conducting layer on the substrate, and graphical described transparency conducting layer forms pixel electrode, another is connected described pixel electrode with described drain electrode or source electrode.
Preferably, described method also comprises, and described first insulation course and the second insulation course make the second connecting hole and the 3rd connecting hole, and described source electrode is connected with described semiconductor layer with described 3rd connecting hole respectively by described second connecting hole with drain electrode.
Preferably, the center line of the projection of described data line on substrate is completely overlapping with the described center line of the projection gone between on substrate that drives.
Preferably, the projection of described data line on substrate is overlapping with the described projection section gone between on substrate that drives.
Preferably, the projection of described data line on substrate and describedly drive the projection zero lap gone between on substrate.
The embodiment of the present invention additionally provides a kind of display panel, comprises above-mentioned array base palte.
In above-described embodiment, described array base palte comprises many gate lines, a plurality of data lines and many drive lead-in wire, described gate line and describedly drive the one_to_one corresponding that goes between; Described data line and the described interlayer that goes between that drives are arranged; Article two, the gate line that adjacent data line is adjacent with two surrounds a pixel region; Described pixel region comprises thin film transistor (TFT) and pixel electrode; Be connected one of in the drain electrode of described pixel electrode and described thin film transistor (TFT) or source electrode; Described gate line is connected with the grid of described thin film transistor (TFT); Described gate line is connected with described driving lead-in wire, and the described drive singal driving lead-in wire to be used for gate driver circuit produces passes to described gate line; Described data line is with the source electrode of described thin film transistor (TFT) or in draining, another is connected.To lead placement be driven in the below of data line in the embodiment of the present invention, drive the projection of lead-in wire on array base palte can partly overlap with the projection of data line on array base palte, the part of overlap is more, and the aperture opening ratio of display is larger, the pixel of display is higher, and it is more obvious that aperture opening ratio promotes.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the structural representation of a kind of array base palte in the embodiment of the present invention;
Fig. 2 a to 2d is the structural representation of a kind of array base palte part and xsect in the embodiment of the present invention;
Fig. 3 a to 3c is the structural representation of another kind of array base palte part and xsect in the embodiment of the present invention;
Fig. 4 a to 4c is the structural representation of another kind of array base palte part and xsect in the embodiment of the present invention;
Fig. 5 is the schematic flow sheet of the method for making of a kind of array base palte in the embodiment of the present invention;
Fig. 6 a to Fig. 6 f is the schematic flow sheet of the method for making of another kind of array base palte in the embodiment of the present invention;
Fig. 7 is a kind of display panel in the embodiment of the present invention.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments provide a kind of array base palte, Fig. 1 shows the structural representation of described array base palte, Fig. 2 a to Fig. 2 d shows described array base palte part and cross sectional representation, owing to driving lead-in wire 103 overlapping with data line 101 in the embodiment of the present invention, for the ease of display, Fig. 1 eliminates data line 101.Fig. 2 d shows a kind of array base palte partial top structure, in order to clearly the embodiment of the present invention can be represented, light shield layer 106, cushion 107, first insulation course 109, second insulation course 110 and passivation layer 113 is eliminated in Fig. 2 d, the concrete structure position of each rete can see Fig. 2 a to Fig. 2 c, in order to each interstructural annexation of the clearer display of energy, data line 101 and gate line intersection make transparent processing, can know display first connecting hole 201, second connecting hole 202, the 3rd connecting hole 203 and the 4th connecting hole 204 from figure.Fig. 2 a to 2c is the trizonal xsect that have chosen partial array substrate shown in Fig. 2 d, is respectively A-A ＇ 301, B-B ＇ 302 and the trizonal xsect of C-C ＇ 303.The ＇ 301 of A-A described in embodiment of the present invention region is the xsect of the thin film transistor (TFT) on array base palte.
Composition graphs 1 and Fig. 2 a to Fig. 2 d, described array base palte comprises: many gate lines 102, a plurality of data lines 101 and many driving lead-in wires 103, described gate line 102 and described driving lead-in wire 103 one_to_one corresponding; Described data line 101 is arranged with described driving lead-in wire 103 interlayer; Article two, the gate line 102 that adjacent data line 101 is adjacent with two surrounds a pixel region 104; Described pixel region 104 comprises thin film transistor (TFT) and pixel electrode 105; Be connected one of in the drain electrode 112 of described pixel electrode 105 and described thin film transistor (TFT) or source electrode 111; Described gate line 102 is connected with the grid 115 of described thin film transistor (TFT); Described gate line 102 is connected with described driving lead-in wire 103, and described driving lead-in wire 103 passes to described gate line 102 for the drive singal produced by gate driver circuit; The source electrode 111 of described data line 101 and described thin film transistor (TFT) or drain in 112 that another is connected.As shown in Figure 1, each drives the corresponding gate line 102 of lead-in wire 103, for being communicated with gate line 102 and gate driver circuit.The projection of data line 101 described in the embodiment of the present invention on array base palte and the projection of described driving lead-in wire 103 on array base palte can partly overlap, can be completely overlapping, also can not be overlapping, overlapping part is more, the aperture opening ratio of display is larger, the pixel of display is higher, and it is more obvious that aperture opening ratio promotes; Although thus make to have increased driving lead-in wire 103 newly but aperture opening ratio can not be affected or affect smaller.Shown in Fig. 1 and Fig. 2 a to Fig. 2 d is the projection of described data line 101 on array base palte and the complete overlapping situation of the projection of described driving lead-in wire 103 on array base palte.
Preferably, the center line of the projection of described data line 101 on array base palte is completely overlapping with the projected centre lines of described driving lead-in wire 103 on array base palte.As shown in Fig. 2 a to Fig. 2 d, in the present embodiment, described data line 101 is completely overlapping with described driving lead-in wire 103, data line 101 and driving lead-in wire 103 different layers, the aperture opening ratio of raising display that can be large as far as possible, the pixel of display is higher, and it is more obvious that aperture opening ratio promotes.
Preferably, described gate line 102 is connected by the first connecting hole 201 with described driving lead-in wire 103.Institute's gate line 102 is connected by the first connecting hole 201 via hole with described driving lead-in wire 103, as shown in Figure 2 b.
Preferably, the source electrode 111 of described data line 101 and described thin film transistor (TFT) and the 112 same layers that drain.In the present embodiment, described data line 101 is connected with the source electrode 111 of described thin film transistor (TFT), and in the process made, source electrode 111 and drain electrode 112 are made by commaterial simultaneously.
Preferably, described array base palte also comprises a light shield layer 106, described light shield layer 106 and the same layer of described driving lead-in wire 103.As shown in A-A ＇ 301 and B-B ＇ 302, C-C ＇ 303 3 regions in Fig. 2 a to Fig. 2 c, in A-A ＇ 301 region, the one deck be positioned on substrate 114 is light shield layer 106, in B-B ＇ 302 and C-C ＇ 303 region, the one deck be positioned on substrate 114 is driving lead-in wire 103, in the process made, light shield layer 106 makes with driving lead-in wire 103 simultaneously, can save a mask plate.Meanwhile, due to data line 101 and driving lead-in wire 103 different layers, data line 101 can be overlapped with driving lead-in wire 103, minimizing is blocked, and increases the aperture opening ratio of display.
Preferably, cushion 107, first insulation course 109 and the second insulation course 110 is provided with between described driving lead-in wire 103 and described data line 101 successively.Described cushion 107, described first insulation course 109 and described second insulation course 110 are in order to isolate described driving lead-in wire 103 and described data line 101.
Preferably, described array base palte comprises: be successively set on the light shield layer 106 on substrate 114, cushion 107, semiconductor layer 108, first insulation course 109, grid 115, second insulation course 110 and the source electrode 111 be connected with described semiconductor layer 108 by the second connecting hole 202, the 3rd connecting hole 203 and drain 112.Wherein, described grid 115 is connected with described gate line 102, and described source electrode 111 is connected with described data line 101, and described drain electrode 112 is connected with described pixel electrode 105, and described source electrode 111 is connected with described drain electrode 112 by described semiconductor layer 108.Described cushion 107 is for isolating described light shield layer 106 and described semiconductor layer 108, described first insulation course 109 is for isolating described semiconductor layer 108 and described grid 115, and described second insulation course 110 is for isolating described grid 115 and described source electrode 111 and and isolating described grid 115 and described drain electrode 112.
Preferably, Fig. 3 a to Fig. 3 c shows the another kind of array base palte of the embodiment of the present invention, and the A-A ＇ 301 wherein shown in Fig. 3 c can see shown in Fig. 2 a.Described array base palte comprises: many gate lines 102, a plurality of data lines 101 and many driving lead-in wires 103, described gate line 102 and described driving lead-in wire 103 one_to_one corresponding; Described data line 101 is arranged with described driving lead-in wire 103 interlayer; The projection of described data line 101 on array base palte is not overlapping with the projection of described driving lead-in wire 103 on array base palte, and the projection of described data line 101 on array base palte is adjacent with the projection of described driving lead-in wire 103 on array base palte; Article two, the gate line 102 that adjacent data line 101 is adjacent with two surrounds a pixel region 104; Described pixel region 104 comprises thin film transistor (TFT) and pixel electrode 105; Described pixel electrode 105 is connected with the drain electrode 112 of described thin film transistor (TFT); Described gate line 102 is connected with the grid 115 of described thin film transistor (TFT); Described gate line 102 is connected with described driving lead-in wire 103, and described driving lead-in wire 103 passes to described gate line 102 for the drive singal produced by gate driver circuit; Described data line 101 is connected with the source electrode 111 of described thin film transistor (TFT).Shown in composition graphs 1 and Fig. 3 a to Fig. 3 c, the projection of data line 101 on array base palte is not overlapping with the projection of driving lead-in wire 103 on array base palte, shown in the data line 101 in B-B ＇ 302 and C-C ＇ 303 region and driving lead-in wire 103, described data line 101 is not overlapping with described driving lead-in wire 103, and data line 101 and driving lead-in wire 103 different layers, the stray capacitance between described data line 101 and described driving lead-in wire 103 can be reduced, simultaneously because the projection of described data line 101 on array base palte is adjacent with the projection of described driving lead-in wire 103 on array base palte, the shielded area of black matrix can be reduced, therefore compared with prior art, the aperture opening ratio of display can also be improved, the pixel of display is higher, it is more obvious that aperture opening ratio promotes.
Preferably, Fig. 4 a to Fig. 4 c shows the another kind of array base palte of the embodiment of the present invention, and the A-A ＇ 301 wherein shown in Fig. 4 c can see shown in Fig. 2 a.Described array base palte comprises: many gate lines 102, a plurality of data lines 101 and many driving lead-in wires 103, described gate line 102 and described driving lead-in wire 103 one_to_one corresponding; Described data line 101 is arranged with described driving lead-in wire 103 interlayer; The projection of described data line 101 on array base palte is overlapping with the projection section of described driving lead-in wire 103 on array base palte; Article two, the gate line 102 that adjacent data line 101 is adjacent with two surrounds a pixel region 104; Described pixel region 104 comprises thin film transistor (TFT) and pixel electrode 105; Described pixel electrode 105 is connected with the drain electrode 112 of described thin film transistor (TFT); Described gate line 102 is connected with the grid 115 of described thin film transistor (TFT); Described gate line 102 is connected with described driving lead-in wire 103, and described driving lead-in wire 103 passes to described gate line 102 for the drive singal produced by gate driver circuit; Described data line 101 is connected with the source electrode 111 of described thin film transistor (TFT).Shown in composition graphs 1 and Fig. 4 a to Fig. 4 c, the projection of data line 101 on array base palte is overlapping with the projection section of driving lead-in wire 103 on array base palte, overlapping part is more, the aperture opening ratio of display is larger, the pixel of display is higher, it is more obvious that aperture opening ratio promotes, and can also reduce the stray capacitance produced between described data line 101 and described driving lead-in wire 103 simultaneously.
Fig. 5 shows the flow process of the method for making of array base palte, and this flow process may be used for making above-mentioned array base palte, but is not limited to the array base palte that the present embodiment provides.The concrete steps of described flow process comprise:
Step S501, provides a substrate 114.
Step S502, substrate 114 arranges the first metal layer and figure dissolves light shield layer 106 and drives lead-in wire 103.
Step S503, described substrate 114 sets gradually cushion 107, semiconductor layer 108 and the first insulation course 109, drives described the first connecting hole 201 lead-in wire making and runs through described first insulation course 109 and described cushion.
Step S504, described substrate 114 arranges the second metal level and figure dissolves gate line 102 and grid 115, and described gate line 102 is connected with described grid 115, and described gate line 102 is connected to described driving lead-in wire 103 by described first connecting hole 201.
Step S505, described substrate 114 sets gradually the second insulation course 110, the 3rd metal level, and figure dissolves source electrode 111, drain electrode 112, data line 101, and described data line 101 and described source electrode 111 or one of to drain in 112 is connected.Wherein, the projection of described data line 101 on substrate 114 and the projection of described driving lead-in wire 103 on substrate 114 can partly overlap, also can not be overlapping, the center line of the projection of described data line 101 on substrate 114 is completely overlapping with the center line of the projection of described driving lead-in wire 103 on substrate 114.The aperture opening ratio of display can be improved, overlapping part is more, the aperture opening ratio of display is larger, the pixel of display is higher, it is more obvious that aperture opening ratio promotes, can the aperture opening ratio of maximized raising display when complete overlap, when the projection of described data line 101 on substrate 114 is not overlapping with the projection of described driving lead-in wire 103 on substrate 114, the stray capacitance reduced between described data line 101 and described driving lead-in wire 103 is the most obvious.
In step S505, also comprise: on described first insulation course 109 and the second insulation course 110, make the second connecting hole 202 and the 3rd connecting hole 203, described source electrode 111 is connected with described semiconductor layer 108 with described 3rd connecting hole 203 respectively by described second connecting hole 202 with drain electrode 112.
Step S506, described substrate 114 sets gradually passivation layer 113 and transparency conducting layer, and graphical described transparency conducting layer forms pixel electrode 105, and another is connected described pixel electrode 105 with described drain electrode 112 or source electrode 111.
In described step S506, when public electrode is at top, described passivation layer 113 makes the first connecting hole 201, by described 4th connecting hole 204, described pixel electrode 105 is connected with described drain electrode 112; When public electrode is in centre position, described passivation layer 113 and described second insulation course 110 make described 4th connecting hole 204, another is connected described pixel electrode 105 with described drain electrode 112 or source electrode 111.
In order to better explain the present invention, the embodiment of the present invention additionally provides a kind of method making array base palte, and the method may be used for making above-mentioned array base palte, but is not limited to the array base palte that the present embodiment provides.
Fig. 6 a to Fig. 6 f shows the flow process of the method for making of array base palte.
Described method for making comprises: as shown in Figure 6 a, provides a substrate 114, and described substrate 114 is generally transparent glass substrate, can be also other transparency carriers, as transparent plastic substrate.Substrate 114 forms the first metal layer, carries out photoetching to described the first metal layer, figure dissolves light shield layer 106 and drives lead-in wire 103.Described the first metal layer chooses the lower metal of resistance usually, as the alloy that one or more in Cr, W, Ti, Ta, Mo, Al, Cu are combined to form.
As shown in Figure 6 b, for the ease of display, the not shown light shield layer 106 of the vertical view in Fig. 6 b, cushion 107, first insulation course 109.Described substrate 114 and described the first metal layer are formed cushion 107, semiconductor layer 108 and the first insulation course 109 successively, and described semiconductor layer 108 carries out photoetching, graphical described semiconductor layer 108, semiconductor layer 108 after graphical is positioned at region corresponding to light shield layer, shown in A-A ＇ 301 region namely in Fig. 6 b; Driving the first connecting hole 201 lead-in wire 103 making and runs through the first insulation course 109 and cushion 107, expose portion drives lead-in wire 103, as shown in B-B ＇ 302 region in Fig. 6 b.Described first connecting hole 201 is used as connecting gate line 102, and gate line 102 is connected with driving lead-in wire 103 by described first connecting hole 201, and described first insulation course 109 selects silicon nitride usually, can certainly be the material of other insulation.Described semiconductor layer 108 is generally amorphous silicon or polysilicon.
As fig. 6 c, for the ease of display, the not shown light shield layer 106 of the vertical view in Fig. 6 c, cushion 107, first insulation course 109.Described substrate 114 forms the second metal level, photoetching is carried out to described second metal level, graphically described second metal level, form gate line 102 and grid 115, described gate line 102 is connected with described grid 115, and described gate line 102 is connected with described driving lead-in wire 103 by described first connecting hole 201.Described second metal level chooses the lower metal of resistance usually, as the alloy that one or more in Cr, W, Ti, Ta, Mo, Al, Cu are combined to form.
As shown in fig 6d, for the ease of display, the not shown light shield layer 106 of the vertical view in Fig. 6 d, cushion 107, first insulation course 109, second insulation course 110.Described substrate 114 is formed the second insulation course 110, described second insulation course 110 makes the second connecting hole 202 and the 3rd connecting hole 203, described second connecting hole 202 and described 3rd connecting hole 203 expose part of semiconductor layer 108, as shown in A-A ＇ 301 region in Fig. 6 d, described second connecting hole 202 is used as connecting source electrode 111, and described 3rd connecting hole 203 is used as drain electrode 112.Described second insulation course 110 selects silicon nitride usually, can certainly be the material of other insulation.
As shown in fig 6e, for the ease of display, the not shown light shield layer 106 of the vertical view in Fig. 6 e, cushion 107, first insulation course 109, second insulation course 110.Described substrate 114 forms the 3rd metal level, photoetching is carried out to described 3rd metal level, graphically described 3rd metal level, form data line 101, source electrode 111, drain electrode 112, described source electrode 111 is connected with described data line 101, described source electrode 111 is connected with described semiconductor layer 108 by described second connecting hole 202, and described drain electrode 112 is connected with described semiconductor layer 108 by described 3rd connecting hole 203.The projection of described data line 101 on substrate 114 is completely overlapping with the projection of described driving lead-in wire 103 on described substrate 114, can improve the aperture opening ratio of display.Described 3rd metal level chooses the lower metal of resistance usually, as the alloy that one or more in Cr, W, Ti, Ta, Mo, Al, Cu are combined to form.
As shown in Figure 6 f, for the ease of display, the not shown light shield layer 106 of the vertical view in Fig. 6 f, cushion 107, first insulation course 109, second insulation course 110, passivation layer 113.Described substrate 114 forms passivation layer 113, described passivation layer 113 makes the 4th connecting hole 204, expose part drain electrode 112, described 4th connecting hole 204 is used as connecting pixel electrode 105.Described passivation layer 113 can be transparent dielectric film, is preferably silicon nitride or organic film.
Described substrate 114 forms the 4th metal level, and carry out photoetching to described 4th metal level, graphically described 4th metal level, described 4th metal level is connected with described drain electrode 112 by described 4th connecting hole 204.Concrete structure visible Fig. 2 a to Fig. 2 d, described 4th metal level selects transparent conductive material usually.
By above-mentioned manufacturing process, the array base palte be made into, can improve the aperture opening ratio of display, and the pixel of display is higher, and it is more obvious that aperture opening ratio improves.
Preferably, as shown in Figure 7, the embodiment of the present invention additionally provides a kind of display panel, comprises above-mentioned array base palte.Described display panel can provide the aperture opening ratio of display.
Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (15)
1. an array base palte, is characterized in that, comprising:
Many gate lines, a plurality of data lines and many drive lead-in wire, described gate line and describedly drive the one_to_one corresponding that goes between; Described data line and the described interlayer that goes between that drives are arranged; Article two, the gate line that adjacent data line is adjacent with two surrounds a pixel region;
Described pixel region comprises thin film transistor (TFT) and pixel electrode;
Be connected one of in the drain electrode of described pixel electrode and described thin film transistor (TFT) or source electrode;
Described gate line is connected with the grid of described thin film transistor (TFT); Described gate line is connected with described driving lead-in wire, and the described drive singal driving lead-in wire to be used for gate driver circuit produces passes to described gate line;
Described data line is with the source electrode of described thin film transistor (TFT) or in draining, another is connected.
2. array base palte as claimed in claim 1, it is characterized in that, the center line of the projection of described data line on array base palte is completely overlapping with the described center line of the projection gone between on array base palte that drives.
3. array base palte as claimed in claim 1, it is characterized in that, the projection of described data line on array base palte is overlapping with the described projection section gone between on array base palte that drives.
4. array base palte as claimed in claim 1, is characterized in that, the projection of described data line on array base palte and describedly drive the projection zero lap gone between on array base palte.
5. array base palte as claimed in claim 1, is characterized in that, described gate line with described drive to go between to be connected by the first connecting hole.
6. array base palte as claimed in claim 1, is characterized in that, the source electrode of described data line and described thin film transistor (TFT) and the same layer that drains.
7. array base palte as claimed in claim 6, it is characterized in that, described array base palte also comprises a light shield layer, described light shield layer and describedly drive the same layer that goes between.
8. array base palte as claimed in claim 7, is characterized in that, is provided with cushion, the first insulation course and the second insulation course successively between described driving lead-in wire and described data line.
9. array base palte as claimed in claim 1, it is characterized in that, described array base palte comprises: be successively set on the light shield layer on substrate, cushion, semiconductor layer, the first insulation course, grid, the second insulation course and the source electrode be connected with described semiconductor layer by the second connecting hole, the 3rd connecting hole and drain electrode.
10. a method for making for array base palte, is characterized in that, described method comprises:
One substrate is provided;
Substrate arranges the first metal layer and figure dissolve light shield layer and drive lead-in wire;
Set gradually cushion, semiconductor layer and the first insulation course on the substrate, drive described the first connecting hole lead-in wire making and runs through described first insulation course and described cushion;
Arrange the second metal level on the substrate and figure dissolves gate line, described gate line is connected to described driving lead-in wire by described first connecting hole;
Set gradually the second insulation course, the 3rd metal level on the substrate, and figure dissolves source electrode, drain electrode, data line, described data line and described source electrode or be connected one of in draining;
Set gradually passivation layer and transparency conducting layer on the substrate, and graphical described transparency conducting layer forms pixel electrode, another is connected described pixel electrode with described drain electrode or source electrode.
11. methods as claimed in claim 10, it is characterized in that, described method also comprises, described first insulation course and the second insulation course make the second connecting hole and the 3rd connecting hole, and described source electrode is connected with described semiconductor layer with described 3rd connecting hole respectively by described second connecting hole with drain electrode.
12. methods as claimed in claim 10, is characterized in that, the center line of the projection of described data line on substrate is completely overlapping with the described center line of the projection gone between on substrate that drives.
13. methods as claimed in claim 10, is characterized in that, the projection of described data line on substrate is overlapping with the described projection section gone between on substrate that drives.
14. methods as claimed in claim 10, is characterized in that, the projection of described data line on substrate and describedly drive the projection zero lap gone between on substrate.
15. 1 kinds of display panels, is characterized in that, comprise as arbitrary in claim 1 to 9 as described in array base palte.
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