KR20040024915A - Liquid crystal display - Google Patents

Abstract

PURPOSE: A liquid crystal display is provided to improve display characteristics as reducing power consumption. CONSTITUTION: A liquid crystal panel displays an image by comprising a gate line, a data line and a number of pixels comprising a switching device connected to the gate line and the data line. A gate driver circuit comprises a plurality of stages(SRC1-SRC2i), and the plurality of stages are divided into N groups and output a gate driving signal provided to the gate line from each stage in sequence in response to a clock signal and a clock bar signal having an inverted phase from the clock signal. A data driver circuit outputs a data signal provided from the data line. And N pairs of interconnection lines are connected to a corresponding group of the gate driver circuit, and comprise a clock interconnection line outputting the clock signal and a clock bar interconnection line outputting the clock bar signal to the stages of the corresponding group.

Description

Liquid Crystal Display {LIQUID CRYSTAL DISPLAY}

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device capable of improving display characteristics while reducing power consumption.

Recently, the information processing apparatus has been rapidly developed to have various forms, various functions, and faster information processing speed. Information processed in such an information processing apparatus has an electrical signal form. In order for the user to visually check the information processed by the information processing apparatus, a display apparatus that serves as an interface is required.

Among such display devices, the liquid crystal display device applies a voltage to a specific molecular array of liquid crystals and converts the same into another molecular array, and the optical properties such as birefringence, photoreactivity, dichroism, and light scattering characteristics of the liquid crystal cell emitted by the molecular array It is a display device that converts a change into a visual change and uses modulation of light by a liquid crystal cell.

The liquid crystal display device includes a thin film transistor (hereinafter, referred to as TFT) substrate, a color filter substrate provided to face the TFT substrate, and a liquid crystal formed between the TFT substrate and the color filter substrate.

The TFT substrate includes a gate line extending in a first direction, a data line extending in a second direction orthogonal to the first direction, a liquid crystal connected to a TFT and a TFT connected to the gate and the data line in a region defined by the gate line and the data line. A large number of pixels made of a capacitor are formed in a matrix form.

A plurality of pixels are formed in the display area of the TFT substrate, and driving circuits for driving gate lines and data lines are integrated around the display area. In detail, a gate driving circuit generating a gate driving signal applied to the gate line and a data driving circuit generating a data signal applied to the data line are formed in the peripheral region.

The gate driving circuit is composed of one shift register and a plurality of wirings for providing various signals to the shift register. Each stage of the shift register has an input terminal, an output terminal, a control terminal, a clock input terminal, a first power supply voltage terminal, and a second power supply voltage terminal. Each stage is connected to the control terminal of the previous stage at the same time as the output terminal is connected to the input terminal of the next stage and cascaded. In addition, the output signal of each stage is connected to each corresponding gate line.

On the other hand, the wirings include a start signal wiring, a first power supply voltage wiring, a second power supply voltage wiring, a clock wiring and a clock bar wiring. Specifically, the start signal wiring applies a start signal to the input terminal of the first stage, and the first and second power supply voltage wirings respectively apply the first and second power supply voltages to the first and second power supply voltage terminals of each stage. Is authorized. In addition, the clock wiring provides a clock signal to an odd stage of the shift register, and the clock bar wiring provides a clock bar signal having a phase inverted with the clock signal to an even stage.

When various signals are applied to the shift register, the gate lines are sequentially selected by output signals of each stage sequentially having an active period (high state).

However, as a liquid crystal display device is gradually developed in a direction of increasing size and high resolution, the following problems occur in driving a screen by a conventional gate driving circuit integrated on a TFT substrate.

As the screen becomes larger or the resolution becomes higher, the number of gate lines formed on the TFT substrate of the liquid crystal display device increases accordingly. As a result, the delay time of the clock and clock bar signals increases toward the last stage, thereby distorting the output signal of the shift register, thereby degrading display characteristics of the liquid crystal display.

In addition, the frequency of the clock and clock bar signals is increased because the increased gate line must be driven for a predetermined period, that is, one frame period. As such, when the frequency of the clock and clock bar signals is increased, the power consumption of the liquid crystal display device is correspondingly increased.

Accordingly, it is an object of the present invention to provide a liquid crystal display device for improving display characteristics while reducing power consumption.

1 is a view showing in detail a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating the gate driving circuit shown in FIG. 1 in detail.

3 is a waveform diagram illustrating an output waveform according to an input waveform of the gate driving circuit illustrated in FIG. 2.

4 is a view showing in detail a liquid crystal display according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100, 300: TFT substrate 110, 310: TFT

120, 320: liquid crystal capacitor 130: gate driving circuit

140: data driving circuit 200, 400: liquid crystal display device

330: first gate driving circuit 340: second gate driving circuit

CK1: first clock wire CKB1: first clock bar wire

CK2: Second Clock Wiring CKB2: Second Clock Bar Wiring

According to an aspect of the present invention, a liquid crystal display device includes a gate line, a data line, and a plurality of pixels including a gate element and a switching element connected to the data line to display an image. A liquid crystal panel; And a plurality of stages that are connected in a dependent manner, wherein the plurality of stages are divided into N groups and respectively, from each stage to the gate line in response to a corresponding clock signal and a clock bar signal having a phase inverted from the clock signal. A gate driving circuit sequentially outputting the provided gate driving signal; A data driving circuit which outputs a data signal provided to the data line; And a pair of N wires connected to a corresponding group of the gate driving circuit and comprising a clock wire for outputting the clock signal and a clock bar wire for outputting the clock bar signal to stages forming the group.

According to another aspect of the present invention, a liquid crystal display device includes a gate line, a data line, and a plurality of pixels including a gate element and a switching element connected to the data line to display an image. A liquid crystal panel; Comprising a plurality of stages connected in cascade, the plurality of stages are divided into N groups and sequentially outputs the first gate driving signal provided from the respective stages to odd-numbered gate lines in response to a corresponding clock signal. A first gate driving circuit; Comprising a plurality of stages connected in a cascade, the plurality of stages are divided into N groups to sequentially receive a second gate driving signal provided from the respective stages to even-numbered gate lines in response to a corresponding clock bar signal. A second gate driving circuit outputting the second gate driving circuit; A data driving circuit which outputs a data signal provided to the data line; N clock wires connected to a corresponding group of the first gate driving circuit and outputting the clock signal to stages belonging to the group; And N clock bar wires connected to a corresponding group of the second gate driving circuit to output the clock bar signal to stages belonging to the group.

According to the liquid crystal display, the shift register constituting the gate driving circuit is divided into N groups, and a clock wire for outputting a clock signal and a clock bar signal having an inverted phase with the clock signal are output to stages belonging to each group. Clock bar wiring is connected. Therefore, the power consumption of the liquid crystal display can be reduced by reducing the delay time of the clock and clock bar signals and reducing the frequency.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a block diagram illustrating the gate driving circuit illustrated in FIG. 1 in detail.

Referring to FIG. 1, a liquid crystal display device 200 according to an exemplary embodiment of the present invention may include a TFT substrate 100 and a color filter substrate having a plurality of pixels facing the TFT substrate 1000. And a liquid crystal (not shown) formed between the TFT substrate 100 and the color filter substrate.

Pixels formed in the TFT substrate 100 are connected to gates and data lines in a region defined by gate lines extending in a first direction, data lines extending in a second direction perpendicular to the first direction, and gate lines and data lines. TFT 110 and a liquid crystal capacitor 120 connected to the TFT 110. Specifically, the gate electrode 111 of the TFT 110 is connected to the gate line, the source electrode 112 is connected to the data line, and the drain electrode 113 is connected to the liquid crystal capacitor 120.

Here, a plurality of pixels are formed in the display area D of the TFT substrate 100 to display an image, and gate lines G1 to Gn and data lines are formed in the peripheral area S formed around the display area D. FIG. A driving circuit for driving (D1 to Dm) is formed to control the operation of the TFT.

Specifically, in the peripheral area S, the gate driving circuit 130 generating the gate driving signals applied to the gate lines G1 to Gn and the data driving circuit generating the data signals applied to the data lines D1 to Dm. 140 is formed. The gate driving circuit 130 is connected to one end of the plurality of gate lines G1 to Gn and sequentially applies gate driving signals to the plurality of gate lines G1 to Gn. In addition, the data driving circuit 140 is connected to one end of the plurality of data lines D1 to Dm to apply a data driving signal to the plurality of data lines D1 to Dm.

Referring to FIG. 2, the gate driving circuit 130 may provide various signals to one shift register 131 and a plurality of stages SRC1 to SRC2i of the shift register 131 to which a plurality of stages SRC1 to SRC2i are cascaded. It is made of wirings ST, VDD, VSS, CK1, CKB1, CK2, and CKB2 for providing.

Since the shift register 131 is connected to the n gate lines G1 to Gn, respectively, the shift register 131 includes n stages SRC1 to SRC2i for outputting a gate driving signal to the n gate lines G1 to Gn. Therefore, 2i is equal to n, and i and n are natural numbers. The shift register 131 is divided into first and second groups 131a and 131b, and the first group 131a includes first to i-th stages SRC1 to SRCi, and the second group 131b Includes the i + 1 to 2i th stages SRCi + 1 to SRC2i.

On the other hand, the wirings include the start signal wiring ST, the first power supply voltage wiring VSS, the second power supply voltage wiring VDD, the first clock wiring CK1, the first clock bar wiring CKB1, and the second clock wiring. CK2 and second clock bar wiring CKB2.

Specifically, the start signal wiring ST applies the start signal ST to the input terminal IN of the first stage SRC1 among the stages SRC1 to SRC2i, and the first and second power voltage wirings The VSS and VDD apply the first and second power supply voltages VSS and VDD to the stages SRC1 to SRC2i, respectively. In addition, the first clock wire CK1 provides the first clock signal CK1 to the odd-numbered stage of the first group 131a of the shift register 131, and the first clock bar wire CKB1 is the first group. The first clock bar signal CKB1 is provided to an even-numbered stage of 131a. The second clock wire CK2 provides the second clock signal CK2 to the odd-numbered stage of the second group 131b of the shift register 131, and the second clock bar wire CKB2 provides the second group 131b. The second clock bar signal CKB2 is provided to even-numbered stages.

Here, the first clock wire CK1, the first clock bar wire CKB1, the second clock wire CK2, and the second clock bar wire CKB2 are formed side by side at a predetermined interval and side by side. The first clock wire CK1 and the first clock bar wire CKB1 receive the first clock signal CK1 and the first clock bar signal CKB1 from the outside. The second clock wire CK2 and the second clock bar wire CKB2 also receive the second clock signal CK2 and the second clock bar signal CKB2 from the outside. The first clock and the first clock bar signals CK1 and CKB1, the second clock and the second clock bar signals CK2 and CKB2 may generate timing signals for generating various signals applied to the liquid crystal display 200. These are the signals generated from.

As shown in FIG. 2, input terminals of the first clock and the first clock bar wires CK1 and CKB1 are disposed at one end of the TFT substrate 100, and the second clock and the second clock bar wires CK2, The input terminal of CKB2 is also disposed at one end of the TFT substrate 100. As such, the input terminals of the first clock, the first clock bar, the second clock, and the second clock bar signals CK1, CKB1, CK2, and CKB2 are disposed at one end of the TFT substrate 100, thereby providing the first clock and the first clock. A connecting member (not shown) for applying a signal provided from the timing controller to the first clock bar wirings CK1 and CKB1 and the second clock and the second clock bar wirings CK2 and CKB2 is provided at one end of the TFT substrate 100. Can only be attached.

Each stage SRC1 to SRC2i of the shift register 131 includes an input terminal IN, an output terminal OUT, a control terminal CT, a clock input terminal CK, a first power supply voltage terminal VSS, and a second It has a power supply voltage terminal VDD. Each stage SRC1 to SRC2i is cascaded by being connected to the control terminal of the previous stage while the output terminal OUT is connected to the input terminal IN of the next stage. Although not shown in the drawing, the shift register 131 may further include one dummy stage connected to the next stage of the 2i th stage SRC2i in addition to the 2i stages SRC1 to SRC2i corresponding to the n gate lines G1 to Gn. It may include.

The start signal ST is input to the input terminal IN of the first stage SRC1 of the shift register 131. The output terminals OUT1 to OUTn of each stage SRC1 to SRC2i are connected to corresponding gate lines G1 to Gn.

The output signal OUT2 of the next stage (for example, SRC2) is input to the control terminal CT of each stage (for example, SRC1) as a control signal. Here, the control signal input to the control terminal CT is used to lower the output signal of each stage SRC1 to SRC2i to a low level. Accordingly, the output signals of the stages SRC1 to SRC2i sequentially have an active period (high state), so that the corresponding gate lines G1 to Gn are sequentially selected in the active period of each output signal.

3 is a waveform diagram illustrating an output waveform according to an input waveform of the gate driving circuit illustrated in FIG. 2.

Referring to FIG. 3, since one screen of the liquid crystal display 200 is driven for one frame period, the gate is sequentially driven to have n high gate lines G1 to Gn in order to operate a pixel. Signal is generated. The shift register 131 including 2i stages SRC1 to SRC2i driving n gate lines G1 to Gn is separated into first and second groups 131a and 131b.

That is, the first and second clock bar signals CK1 and CKB1 generated in the first group 131a including the 1 st th to i th stages SRC1 to SRCi alternately have a high state for 1/2 frame period. Are applied respectively. In addition, in the second group 131b including the i + 1 to 2i th stages SRCi + 1 to SRC2i, the second clock bar signal and the second clock bar signal generated alternately in a high state for the remaining 1/2 frame period. (CK2, CKB2) are applied respectively.

When the first clock and the first clock bar signals CK1 and CKB1 and the start signal ST are supplied to the shift register 131, the first clock SRC1 responds to the leading end of the start signal ST in the first stage SRC1. The high level section of the signal CK1 is generated as the first output signal OUT1. [0047] After that, in the second stage SRC2, the first clock in response to the first output signal OUT1 of the first stage SRC1 is generated. The high level section of the bar signal CKB1 is generated as the second output signal OUT2. In this manner, the first clock and the first clock bar signals CK1 and CKB1 are sequentially generated as the gate driving signal during the 1/2 frame period from the 1 st to i th stages SRC1 to SRCi.

Next, the i + 1 th stage SRCi + 1 has a high level section of the second clock signal CK2 in response to the i th output signal OUTi of the i th stage SRCi. Generated by the i + 1th output signal OUTi + 1 of 1). Thereafter, in the i + 2 th stage SRCi + 2, the high level section of the second clock bar signal CKB2 in response to the i + 1 th output signal OUTi + 1 of the i + 1 th stage SRCi + 1. This i + 2 output signal OUTi + 2 is generated. In this way, the second clock and the second clock bar signals CK2 and CKB2 are sequentially generated as the gate driving signals until the i + 1 to 2i th stages SRCi + 1 to SRC2i for the remaining 1/2 frame period.

In FIG. 2 and FIG. 3, the shift register 131 is divided into two groups 131a and 131b, and is connected to each of the separate groups to provide separate clocks for providing clock and clock bar signals to stages belonging to each group. The case where a clock bar wiring is provided is shown. However, the gate driving circuit 130 according to the present invention further includes clock and clock bar wires as separated from the shift register 131 divided into three or more, so that the clock and clock bar signals are included in the stages belonging to each group. Can be provided.

In other words, the gate driving circuit 130 is divided into N groups, and N varies depending on the resolution of the liquid crystal display device 200. As the resolution of the liquid crystal display device 200 increases, the value of N also increases. Where N is a natural number.

As such, by reducing the number of stages of the shift register 131 connected to one clock and clock bar wire, the delay time of the clock and clock bar signals is reduced, and the frequency of the clock and clock bar signals is reduced, thereby decreasing the frequency of the clock and clock bar signals. ) Can reduce power consumption.

4 is a view showing in detail a liquid crystal display according to another embodiment of the present invention.

Referring to FIG. 4, the liquid crystal display device 400 according to another exemplary embodiment of the present invention includes a TFT substrate 300 having a plurality of pixels formed in a matrix form, a color filter substrate (not shown) provided to face the TFT substrate, and It is made of a liquid crystal (not shown) formed between the TFT substrate 300 and the color filter substrate.

Pixels formed in the TFT substrate 300 are connected to gates and data lines in a region defined by gate lines extending in a first direction, data lines extending in a second direction orthogonal to the first direction, and gate lines and data lines. TFT 310 and a liquid crystal capacitor 320 connected to the TFT 310.

Here, the plurality of pixels are formed in the display area D of the TFT substrate 300 to display an image, and the gate lines G1 to G2n and the peripheral areas S1 and S2 formed around the display area D are displayed. A driving circuit for driving the data lines D1 to Dm is formed to control the operation of the pixel.

The peripheral areas S1 and S2 are formed of the first peripheral area S1 formed around the left side of the display area D and the second peripheral area S2 formed around the right side of the display area D. FIG. Clock wirings CK1 and CK2 connected to the first gate driving circuit 330 and the first gate driving circuit 330 are disposed in the first peripheral region S1, and the second gate driving circuit is disposed in the second peripheral region S2. Clock bar wires CKB1 and CKB2 connected to the furnace 340 and the second gate driving circuit 340 are disposed.

The first gate driving circuit 330 is composed of a plurality of stages SRC1 to SRC4i + 1 that are cascaded to sequentially output first gate driving signals provided to odd-numbered gate lines G1 to G2n-1. . In addition, the second gate driving circuit 340 is composed of a plurality of stages SRC2 to SRC4i connected in cascade, and is provided to even-numbered gate lines G2 to G2n to sequentially output the second gate driving signal.

Here, 2n stages SRC1 to SRC4i are formed to output gate driving signals to the 2n gate lines G1 to G2n through the first and second gate driving circuits 330 and 340. Therefore, 4i is equal to 2n, and i and n are natural numbers.

Meanwhile, the plurality of stages SRC1 to SRC4i + 1 of the first gate driving circuit 330 may include the first group 331 consisting of the 1st to 2i-1st stages SRC1 to SRC2i-1 and 2i + 1 to 4i. It is separated into a second group 332 consisting of the +1 th stage (SRC2i + 1 to SRC4i + 1). In addition, the plurality of stages SRC2 to SRC4i of the second gate driving circuit 340 may include a third group 341 made up of the second to second stages SRC2 to SRC2i and the 2i + 2 to 4i stages SRC2i + 2 to Is divided into a fourth group 342 consisting of SRC4i).

Here, each stage of the first gate driving circuit 330 and the second gate driving circuit 340 is cascaded. Therefore, the output signal of the stage of the first gate driving circuit 330 controls the stage of the second gate driving circuit 340, and the stage of the second gate driving circuit 340 of the first gate driving circuit 330. Control the output of the next stage.

On the other hand, the clock wire CK connected to the first gate driving circuit 330 transmits the first clock signal CK1 generated during the 1/2 frame period to the first group 331 of the first gate driving circuit 330. And a second clock wire CK2 for providing the second clock signal CK2 generated during the remaining half frame period to the second group 332.

In addition, the clock bar wire CKB connected to the second gate driving circuit 340 is generated for a half frame period in the third group 341 of the second gate driving circuit 340 and the first clock signal CK1. The first clock bar wire CKB1 for providing the first clock bar signal CKB having an inverted phase with the second clock signal, and the second clock signal CK2 is generated during the remaining 1/2 frame period in the fourth group 342. ) And a second clock bar wire CKB2 for providing a second clock bar signal CKB2 having an inverted phase.

According to such a liquid crystal display, the shift registers constituting the gate driving circuit are divided into N groups, and each group includes a clock wire for outputting a clock signal and a clock for outputting a clock bar signal having a phase inverted from the clock signal. Separate wire pairs including bar wires are connected.

Accordingly, the number of stages of the shift register connected to one clock and clock bar wiring is reduced by providing a pair of wirings for applying clock and clock bar signals to each group of the shift registers. Thus, the delay time of the clock and clock bar signals can be reduced, and the power consumption of the liquid crystal display can be reduced by reducing the frequency of the clock and clock bar signals.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (7)

A liquid crystal panel configured to display an image having a plurality of pixels including a gate line, a data line, and a switching element connected to the gate line and the data line; And a plurality of stages that are connected in a dependent manner, wherein the plurality of stages are divided into N groups and respectively, from each stage to the gate line in response to a corresponding clock signal and a clock bar signal having a phase inverted from the clock signal. A gate driving circuit sequentially outputting the provided gate driving signal; A data driving circuit which outputs a data signal provided to the data line; And A pair of N wires connected to a corresponding group of the gate driving circuit and comprising a clock wire for outputting the clock signal and a clock bar wire for outputting the clock bar signal to stages constituting the group; A liquid crystal display device. The liquid crystal display device according to claim 1, wherein N is a natural number of two or more. The liquid crystal display of claim 1, wherein each of the N pairs of wires outputs the clock signal and the clock bar signal during different 1 / N frame periods. The display panel of claim 1, wherein the liquid crystal panel comprises a display area for displaying an image and a peripheral area formed around the display area. And the gate driving circuit and the N pair of wirings are arranged in the peripheral region. The liquid crystal display of claim 1, wherein the clock line is connected to an odd stage and the clock bar line is connected to an even stage. A liquid crystal panel configured to display an image having a plurality of pixels including a gate line, a data line, and a switching element connected to the gate line and the data line; Comprising a plurality of stages connected in cascade, the plurality of stages are divided into N groups and sequentially outputs the first gate driving signal provided from the respective stages to odd-numbered gate lines in response to a corresponding clock signal. A first gate driving circuit; Comprising a plurality of stages connected in a cascade, the plurality of stages are divided into N groups to sequentially receive a second gate driving signal provided from the respective stages to even-numbered gate lines in response to a corresponding clock bar signal. A second gate driving circuit outputting the second gate driving circuit; A data driving circuit which outputs a data signal provided to the data line; N clock wires connected to a corresponding group of the first gate driving circuit and outputting the clock signal to stages belonging to the group; And And N clock bar wires connected to a corresponding group of the second gate driving circuit to output the clock bar signal to stages belonging to the group. The liquid crystal panel of claim 6, wherein the liquid crystal panel comprises a display area for displaying an image, a first peripheral area formed around the right side of the display area, and a second peripheral area formed around the left side of the display area. And the first gate driving circuit and the clock wirings are disposed in the first peripheral region, and the second gate driving circuit and the clock bar wirings are disposed in the second peripheral region.