JP2000137459A - Integrated circuit device and liquid crystal display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the production cost and decrease the frame size of a liquid crystal display module by reducing the dimension of a semiconductor chip in the short length direction and a chip area. SOLUTION: This integrated circuit device eliminates the need for wiring across a switch 43 and a latch 44 by taking a same display data in a j-th step (j=1, 2,..., 12) and a (j+12)th step of a data register 42, and configuring the circuit to alternately supply display data from each j-th step (j=1, 3,..., 11) and (i+1)th step-data from the 1st to 12th step to the 1st-6th steps of NROM decoders 46N and data from the 13th step to 24th step to PROM decodes 46P-via double input-single output switches as 1st change-over switches 43 and latches 44 so that the data at NROM decoder 46N and the data at PROM decoder 46P are reversed to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit device and an active matrix type liquid crystal display device of the dot inversion drive type using the same.

[0002]

2. Description of the Related Art A liquid crystal display module of an active matrix type liquid crystal display device of a dot inversion drive system is shown in FIG.
As shown in FIG. 1, the liquid crystal panel 100 and a driving device 200 arranged on the outer periphery of the liquid crystal panel 100 are provided. The liquid crystal panel 100 is composed of two glass substrates arranged to face each other with a liquid crystal interposed therebetween. A TFT (thin film transistor) and a pixel electrode are formed on a rear substrate, and a common electrode and a color filter are formed on a front substrate. Have been. TFTs and pixel electrodes are formed in a matrix on the rear substrate, and these TFTs and pixel electrodes extend in the horizontal direction, and gate lines arranged in the vertical direction. Data lines arranged side by side are connected. The driving device 200 includes a vertical driver 210 connected to the gate line.
And a horizontal driver 220 connected to the data line. When a scanning signal is supplied to a certain gate line from the vertical driver 210, the TFT connected to this gate line is turned on, and the display data signal supplied to the data line from the horizontal driver 220 is turned on.
Is supplied to the pixel electrode via the pixel electrode, and an electric field is applied to the liquid crystal by the pixel electrode and the common electrode, thereby causing an optical change to perform display.

[0003] When the drivers 210 and 220 are mounted on a module, for example, in the case of XGA (1024 x 768 pixels) display, the horizontal driver 220 has data lines of R (red) and G
(Green) and B (blue) are required, so 1024 × 3 = 30
It is necessary to drive 72 data lines, for example, 38
Eight horizontal drivers 220 having four driving capacities are arranged on the upper outer periphery of the liquid crystal panel 100 in a cascade connection on one side. The vertical driver 210 needs to drive 768 gate lines. For example, four vertical drivers 210 having a driving capability of 192 are arranged on the left outer periphery of the liquid crystal panel 100 on one side in a cascade connection. The drivers 210 and 220 are each composed of an integrated circuit device composed of a long rectangular semiconductor chip. To mount this integrated circuit device on a module, each integrated circuit device is mounted on a TCP (tape carrier package) and a liquid crystal device is mounted. Panel 10
0 are arranged in parallel on the long side of the semiconductor chip on the corresponding side of 0.

[0004] The invention of this application is based on the drivers 210 and 22 described above.
0 is for the horizontal driver 220. Hereinafter, a schematic configuration of the horizontal driver 220 will be described with reference to FIG. In recent years, there has been a demand for a horizontal driver to increase the number of bits in order to improve the image quality of the liquid crystal panel. The negative and positive gradation voltages of the tone are alternately output for each horizontal period so that the odd lines and the even lines have different polarities on the data lines as negative and positive drive voltages. 221, data register 222, latch 2
23, a level shifter 224, a D / A converter 225, and a voltage follower output circuit 226.
The shift register 221 is, for example, 64-bit bidirectional, and selects right shift start pulse input / output or left shift start pulse input / output by shift direction switching input, and reads the H level of the start pulse at the edge of the clock input. Generate control signals for data capture sequentially,
Output to the data register 222. Data register 22
Reference numeral 2 denotes 8-bit display data sequentially read every six stages based on a control signal from each stage of the shift register 221, and a latch 223 reads the display data read into the data register 222 at a latch input edge via a level shifter 224. Batch output to the D / A converter 225 every horizontal period. The D / A converter 225 internally outputs one of the 256 gray scale negative and positive gray scale voltages generated by the internal gray scale voltage generation circuit by the gamma correction power supply input based on the display data corresponding to each output. , And alternately output each data line as a negative and positive drive voltage via a voltage follower output circuit 226 such that the odd and even lines have different polarities every one horizontal period. .

Next, a conventional integrated circuit device mounted on a TCP as the horizontal driver 220 will be described with reference to FIG. 3 assuming that it has a driving capability for 384 data lines.
In the figure, reference numeral 1 denotes a slim bar-shaped semiconductor chip, and the circuit of the above-described horizontal driver 220 is arranged as an internal circuit 2 in the semiconductor chip 1 at the center along the long side. Although not shown, output pads corresponding to 384 data lines are arranged on the outer peripheral portion arranged on the liquid crystal panel side of the two outer peripheral portions along the long side so as to be connected to the internal circuit 2 and are arranged on the opposite outer peripheral portion. In the section, input pads for start pulse input / output, shift direction switching input, clock input, data input, latch input, etc., and power pads for positive power supply, negative power supply, and γ correction power supply are connected to the internal circuit 2 and arranged. I have. A part of the output pad may be arranged on the short side or the long side on the input side in addition to the long side on the liquid crystal panel side. Internal circuit 2
The inside is divided into four drive circuit blocks 3 of substantially the same configuration corresponding to a quarter of the 384 data lines, that is, 96 data lines.

Next, the drive circuit block 3 will be described with reference to FIG. For the sake of simplicity, the drive circuit block 3 having 96 outputs will be described with reference to a drive circuit block having 12 outputs, and a common circuit such as a gradation voltage generation circuit and external power supply inputs and signals will be described. Illustration of the input is omitted. The drive circuit block 3 has two stages (16 stages in the case of 96 outputs) of shift registers 11 corresponding to six outputs, and 12 stages (96 stages in the case of 96 outputs) of data corresponding to 12 outputs. A register 12, a first switch 13 having six stages (48 stages in the case of 96 outputs) having two inputs and two outputs, and one corresponding to 12 outputs
Latches 14 and 12 of two stages (96 stages for 96 outputs)
Twelve levels (96 levels for 96 outputs) level shifter 15 corresponding to the output, and six levels (48 levels for 96 outputs)
NROM decoder 16N and 6 stages (4 for 96 outputs)
A D / A converter 16 in which a PROM decoder 16P (8 stages) is arranged adjacent to the semiconductor chip 1 in the longitudinal direction;
A second change-over switch 17 having six (two-input, two-output) switches for two-input and two-output, and a voltage-follower output circuit 18 having twelve stages (96 for 96-output) corresponding to twelve outputs And the voltage follower output circuit 18 is sequentially arranged in the longitudinal direction on the liquid crystal panel side of the semiconductor chip 1 so as to form a wiring 21 between the shift register 11 and the data register 12, the data register 12, and the first switch. 13, a wiring 23 between the first changeover switch 13 and the latch 14, and a latch 1
4 and the level shifter 15, a wiring 24 and a level shifter 1
5 and the D / A converter 16, and a wiring 26 between the D / A converter 16 and the second switch 17.
And the second changeover switch 17 and the voltage follower output circuit 18 are connected with the wiring 27.

The wiring 21 is provided between the first stage of the shift register 11 and the first through sixth stages of the data register 12, and the second stage of the shift register 11 and the seventh through twelfth stages of the data register 12. Connected between steps. The wiring 22 is connected between the first stage of the data register 12 and one input side of the two inputs of the first stage of the first changeover switch 13,
2 of the second stage and 2 of the first stage of the first switch 13
Between the other input side of the input, between the third stage of the data register 12 and one input side of the second input of the second stage of the first changeover switch 13, between the fourth stage of the data register 12 and the second stage of the first changeover switch 13. Between the other input sides of the two inputs of the stage,..., Between the one input side of the two inputs of the eleventh stage of the data register 12 and the sixth stage of the first changeover switch 13, and the data register 1
The other input side of the second input of the second stage and the other input side of the second input of the sixth stage of the first changeover switch 13 are connected by eight lines. The wiring 23 is connected between one output of the first output of the first switch 13 and the first output of the latch 14, the other output of the first output of the first switch 13 and the seventh output of the latch 14. Between the second output of the second switch of the first switch 13 and the second output of the latch 14, the other output of the second output of the second switch 13 and the eighth output of the latch 14, ,..., One output of the second output of the sixth switch of the first switch 13 and the sixth output of the latch 14, and the other output of the second output of the sixth switch of the first switch 13 and the output of the latch 14. The twelfth stage is connected by eight lines. Wiring 24
Are between the first stage of the latch 14 and the first stage of the level shifter 15, between the second stage of the latch 14 and the second stage of the level shifter 15,..., And the second stage of the latch 14 and the first stage of the level shifter 15. Each of the twelfth stages is connected by eight wires.
The wiring 25 is provided between the first stage of the level shifter 15 and the first stage of the NROM decoder 16N, between the second stage of the level shifter 15 and the second stage of the NROM decoder 16N,..., The seventh stage of the level shifter 15 and the PROM. Between the first stage of the decoder 16P,..., And the twelfth stage of the level shifter 15 and PR
The sixth stage of the OM decoder 16P is connected by 16 lines each. The wiring 26 is connected to the first of the NROM decoder 16N.
Between the first stage and one input side of the two inputs of the first stage of the second changeover switch 17, the second stage and the second stage of the NROM decoder 16N.
.., Between the one input side of the two inputs of the second stage of the changeover switch 17,..., Between the sixth stage of the NROM decoder 16N and one input side of the two inputs of the sixth stage of the second changeover switch 17;
Between the other input side of the first stage of the ROM decoder 16P and the second input of the first stage of the second changeover switch 17, and the second input of the second stage of the PROM decoder 16P and the second stage of the second changeover switch 17 , And the other input side of the second input of the sixth stage of the second changeover switch 17 and the sixth stage of the PROM decoder 16P are connected by one line. The wiring 27 is connected between one output of the two outputs of the first stage of the second changeover switch 17 and the first stage of the voltage follower output circuit 18, and connected to the second stage of the first stage of the second changeover switch 17.
The other output and the second output of the voltage follower output circuit 18
Between the stages,..., 2 in the sixth stage of the second changeover switch 17
One of the outputs and the first of the voltage follower output circuit 18
One output is connected between the first stage and the other output of the second output of the sixth switch 17 and the twelfth stage of the voltage follower output circuit 18, respectively.

The operation of the drive circuit block 3 is as follows. For example, when the right shift start pulse input / output is selected by the shift direction switching input in the shift register 11,
The H level of the start pulse is read in the first stage of the shift register 11 at the edge of the clock input every horizontal period, and is transferred to the second stage of the shift register 11 to be shifted to the first stage.
1, a right shift start pulse is output from the second stage, and a control signal for sequentially taking in data from the first stage and the second stage of the shift register 11 is sequentially transmitted from the first stage of the data register 12 to the first stage. 6th and 7th to 12th
It is output in each row. The data register 12 is controlled by the control signal from the first stage of the shift register 11 to each of the first to sixth stages and the seventh stage by the control signal from the second stage every one horizontal period. , The 8th bit of display data is fetched to each of the twelfth stages, and the first stage, the third stage,.
The display data captured in the first stage is output to one input side of each of the first to sixth stages of the first changeover switch 13 and the second stage of the data register 12 which is an even stage. , The fourth stage,..., And the display data captured in the twelfth stage are output to the other inputs of the first to sixth stages of the first changeover switch 13. The first changeover switch 13 converts the display data input to the first input to the sixth input and the display data input to the other input to the first input to the sixth input of the latch 14 every horizontal period. 7th stage to 1st
The output is alternately output to the second stage. The latch 14 applies the display data input from the first stage to the twelfth stage every one horizontal period through the level shifter 15 at the edge of the latch input.
The NROM decoder 16N and the PROM decoder 16P inside the / A converter 16 collectively output the first to sixth stages. The D / A converter 16 has an internal NRO
Based on the display data input from the first to sixth stages of the M decoder 16N, one of 256 negative gray scale voltages
Each time the second switch 17 from the first stage to the sixth stage
Output to the first input side of the stage, and internal PR
Based on the display data input from the first stage to the sixth stage of the OM decoder 16P, one of the 256 gray-scale positive gradation voltages is changed from the first stage to the sixth stage of the second changeover switch 17. To each other input side. The second changeover switch 17 sets a voltage between the negative gray scale voltage input to one input side and the positive gray scale voltage input to the other input side of each of the first to sixth stages for each horizontal period. The first, third,..., Eleventh, odd stages of the follower output circuit 18
The second stage, the fourth stage,..., And the twelfth stage, which are the even stages and the even stages, are output alternately. The voltage follower output circuit 18 converts the negative gray scale voltage and the positive gray scale voltage inputted to each of the first to twelfth stages so that the polarity is different between the odd and even stages so that one horizontal line is obtained. The data is alternately output to the odd data lines and the even data lines for each period.

[0009]

As shown in FIG. 4, the wiring 23 is provided between the first output of the second output of the first switch 13 and the first output of the latch 14 and the first switch 13. And the other output of the second output of the first stage and the latch 14
Of the second stage of the first changeover switch 13 between the seventh stage
Between one output and the second stage of the latch 14, between the other output of the second switch of the first switch 13 and the eighth stage of the latch 14,..., The sixth stage of the first switch 13 Between one of the two outputs and the sixth stage of the latch 14, and
The other output of the second output of the sixth stage of the changeover switch 13 is connected to the twelfth stage of the latch 14 by eight lines, respectively.
In addition to the parallel wiring between the first changeover switch 13 and the latch 14, a wiring that intersects with the parallel wiring is required, and at least the wiring pitch × 6 outputs × 8 in the direction between the first changeover switch 13 and the latch 14 for the layout. The size for book / output is required. When the drive circuit block 3 corresponds to 96 outputs, at least the wiring pitch × 48 outputs × 8 lines /
Output dimensions are required, and the wiring pitch is, for example, 1.5 μm
Then, this dimension is 1.5 μm × 48 outputs × 8 lines / output = 576 μm, and the proportion of the chip in the short dimension is as large as about 20% when the short dimension of the chip is 2.5 mm, for example. However, there is a problem that the cost is large. Further, in the liquid crystal display module, a driver is arranged in a peripheral portion (frame) other than the display area. In order to reduce the size of the liquid crystal display device, it is necessary to make the peripheral portion as small as possible. In order to reduce the dimension in the short direction, it was necessary to reduce this ratio. . SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and eliminates the intersection of wiring between a first changeover switch and a latch. It is an object of the present invention to provide an integrated circuit device in which the width of a semiconductor chip is reduced and the chip area is reduced by reducing the ratio of the integrated circuit device to the size, and a liquid crystal display device using the same.

[0010]

According to a semiconductor integrated circuit device of the present invention, n drive circuit blocks having m outputs are arranged in a longitudinal direction of a long rectangular semiconductor chip, and a positive polarity signal is output from the outputs. An integrated circuit device for alternately outputting a drive voltage and a negative drive voltage in each horizontal period such that the odd-numbered output and the even-numbered output have different polarities, wherein the drive circuit block includes a plurality of drive circuits in each stage. Import bit display data 2
The data register of the m-th stage and the display data taken in the i-th (i = 1, 3,..., 2m−1) and (i + 1) -th stages of the data register are alternately arranged every horizontal period. M, a two-input, one-output, first-stage changeover switch connected to the first changeover switch, and a latch input, which collectively outputs display data from each stage of the first changeover switch every horizontal period. Stage, a (m / 2) -stage one-conductivity ROM decoder connected to the first stage to the (m / 2) -th stage of the latch and outputting a unipolar drive voltage, and the ((( A D / D stage in which a (m / 2) -stage other conductive type ROM decoder connected to the (m / 2) +1) -th stage to the (2m) -th stage and outputting a driving voltage of the other polarity is arranged adjacent to the semiconductor chip in the longitudinal direction. Before being connected to A / D converter and this D / A converter A two-input / two-output second switching circuit for alternately outputting one-polarity drive voltage and another-polarity drive voltage every one horizontal period, and the display data to be taken into the data register is stored in a j-th stage (j = 1, 2,..., M) and the (j + m) -th stage, and the first switch is the display data taken in the i-th and (i + 1) -th stages of the data register. From the first stage to the (m / 2)
The output is made different between the stage and the ((m / 2) +1) th stage to the 2mth stage. According to this means, the number of stages of the data register is twice the number of outputs of the drive circuit block, and half of the total number of stages is used for the one-conductivity ROM decoder, and the other half is used for the other-conductivity ROM decoder. j = 1,2
, M) and the (j + m) -th stage, the same display data is fetched, and the number of stages of the two-input / one-output first changeover switch is set to be the same as the number of outputs of the drive circuit block.
Display data from adjacent odd-numbered and even-numbered stages of the data register for the OM decoder are transferred to the one-conductivity-type ROM decoder via the first changeover switch and the latch. Display data from adjacent odd-numbered and even-numbered stages of each stage is displayed on the other-conductivity-type ROM decoder via the first changeover switch and the latch, and is displayed on the odd-numbered stage by the one-conduction-type ROM decoder. By alternately supplying the data and the display data of the even-numbered stages so as to be different every one horizontal period, the wiring between the first changeover switch and the latch is connected to the first-stage, second-stage, and second-stage, respectively. .., The m-th stage can be connected to each other, so that there is no intersection between the stages, and wiring that runs horizontally between the first changeover switch and the latch becomes unnecessary.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an integrated circuit device for a horizontal driver according to a first embodiment of the present invention will be described with reference to FIG. 1 as having a driving capability for 384 data lines. In the figure, reference numeral 31 denotes a slim bar-shaped semiconductor chip. On the semiconductor chip 31, a circuit similar to the horizontal driver 220 described with reference to FIG. Although not shown, the data line 384 is connected to the outer peripheral portion, which is located on the liquid crystal panel side, of both outer peripheral portions along the long side.
Output pads corresponding to the main circuit are arranged so as to be connected to the internal circuit 32.
Shift direction switching input, clock input, data input,
Input pads such as a latch input and power pads for a positive power supply, a negative power supply, and a γ correction power supply are arranged so as to be connected to the internal circuit 32. A part of the output pad may be arranged on the short side or the long side on the input side in addition to the long side on the liquid crystal panel side. The internal circuit 32 is divided into four drive circuit blocks 33 of substantially the same configuration corresponding to, for example, a quarter of 384 data lines, that is, 96 data lines.

Next, the driving circuit block 33 is shown in FIG.
This will be described with reference to FIG. For the sake of simplicity, the drive circuit block 33 having 96 outputs will be described as follows.
A circuit having two outputs will be illustrated and described, and illustration of a common circuit such as a gradation voltage generation circuit and an external power supply input or signal input will be omitted. The drive circuit block 33 has two stages (16 stages in the case of 96 outputs) in which one stage for generating a control signal for data acquisition by reading the H level of a start pulse at an edge of a clock input corresponds to six outputs. A shift register 41, a 24-stage data register 42 (two sets of 96 stages in the case of 96 outputs) corresponding to 12 outputs for taking in 8-bit display data by a control signal from the shift register 41, and a data register 42. Display data fetched in the adjacent odd-numbered stage i (i = 1, 3,..., 23) and the even-numbered stage (i + 1) are alternately arranged in the first to twelfth stages. The two-input / one-output switch that outputs the odd-numbered display data and the even-numbered display data differently from each other in the display data captured in the 13th to 24th stages has 12 stages ( 96 out In the case of 96
A first-stage changeover switch 43, and a 12-stage (96-stage in the case of 96 outputs) latch 44 corresponding to 12 outputs for collectively outputting display data from the first changeover switch 43 at the edge of the latch input; Twelve stages corresponding to the twelve outputs for converting the voltage level of the display data from the latch 44 to a level capable of driving the next stage circuit (96 in the case of 96 outputs)
Stage shifter 45, and a negative gray scale voltage having one polarity of 256 gray scales is input, and based on display data from the level shifter 45, each of the six stages outputs one of the gray scale voltages from each of the stages. NROM decoder 46N, which is a corresponding six-stage one-conductivity-type ROM decoder (4 for 96 outputs)
(8 stages) and 256 gradations, and a positive gradation voltage having the other polarity is input. Based on the display data from the level shifter 45, each stage outputs 6 gradation voltages corresponding to 6 outputs. A D / A converter 46 in which a PROM decoder 46P (48 stages in the case of 96 outputs), which is another conductive type ROM decoder, is arranged adjacent to the semiconductor chip 31 in the longitudinal direction. 2-input 2 for alternately outputting negative and positive gradation voltages to one output side and the other output side
There are six output switches (48 for 96 outputs).
) Corresponding to the 12 outputs for outputting the gradation voltages from one output side and the other output side of the second changeover switch 47 to the odd and even stages, respectively.
The voltage follower output circuits 48 (in the case of 96 outputs, 96 steps) are sequentially arranged in the long side direction of the semiconductor chip 31 on the liquid crystal panel side, and a wiring 51 is provided between the shift register 41 and the data register 42. And data register 4
2, a wire 52 between the first switch 43 and the latch 44, a wire 54 between the latch 44 and the level shifter 45, and a wire 55 between the level shifter 45 and the D / A converter 46. And D / A
Wiring 5 between converter 46 and second switch 47
6, a second switch 47 and a voltage follower output circuit 48 are connected by a wiring 57.

The wiring 51 is connected between the first stage of the shift register 41 and the first to sixth stages and the thirteenth to eighteenth stages of the data register 42 and the second stage of the shift register 41 and the data. The seventh to twelfth stages and the nineteenth to twenty-fourth stages of the register 42 are connected. The wiring 52 is provided between the first stage of the data register 42 and one input side of the two inputs of the first stage of the first switch 43, and the second stage of the data register 42 and the second stage of the first stage 43 of the first switch 43. Between the other input side of the input, between the third stage of the data register 42 and one input side of the second input of the second stage of the first changeover switch 43, and between the fourth stage of the data register 42 and the second stage of the first changeover switch 13. Between the other input sides of the second input of the stage,..., The 23rd stage of the data register 42 and the first changeover switch 4
3 between one input side of the two inputs of the 12th stage, and the 24th stage of the data register 42 and the 1 of the first changeover switch 43.
The other two input terminals of the second stage are connected by eight lines. The wiring 53 is provided between the first stage output of the first changeover switch 43 and the first stage of the latch 44, between the second stage output of the first changeover switch 43 and the second stage of the latch 44,. Eight connections are made between the twelfth output of the changeover switch 43 and the twelfth output of the latch 44.
The wiring 54 is provided between the first stage of the latch 44 and the first stage of the level shifter 45, and the second stage of the latch 44 and the level shifter 45.
, And the twelfth stage of the latch 44 and the twelfth stage of the level shifter 45 are connected by eight lines. The wiring 55 is connected to the first stage of the level shifter 45 and NR
, Between the first stage of the OM decoder 46N, between the second stage of the level shifter 45 and the second stage of the NROM decoder 46N,.
The seventh stage of the level shifter 45 and the PROM decoder 46P
, And between the twelfth stage of the level shifter 45 and the sixth stage of the PROM decoder 46P, respectively.
They are connected with six wires. The wiring 56 is an NROM decoder 46
N between the input of the first stage and one input of the second input of the first switch of the second selector switch 47, and one input of the second input of the second stage of the NROM decoder 46N and the second input of the second selector switch 47 Between the input sides,..., Between the sixth stage of the NROM decoder 46N and one input side of the second input of the sixth stage of the second changeover switch 47, and between the first stage of the PROM decoder 46P and the second stage of the second changeover switch 47. Between the other input side of the 2nd input of the first stage, PRO
Second stage of M decoder 46P and second changeover switch 4
7, the second input of the second stage, between the other input side,.
The sixth stage of the M decoder 46P and the second changeover switch 4
The other input side of the second input of the seventh stage is connected with one each. The wiring 57 is connected between one output of the two outputs of the first stage of the second changeover switch 47 and the first stage of the voltage follower output circuit 48, and the other output of the two outputs of the first stage of the second changeover switch 47 and the voltage. Follower output circuit 48
, One output of the two outputs of the sixth stage of the second changeover switch 47 and the voltage follower output circuit 48
And the other output of the second output of the sixth stage of the second changeover switch 47 and the twelfth stage of the voltage follower output circuit 48 are respectively connected by one line.

The operation of the drive circuit block 33 is such that, for example, when the right shift start pulse input / output is selected by the shift direction switching input in the shift register 41, the clock is shifted to the first stage of the shift register 41 every horizontal period. At the input edge, the H level of the start pulse is read, transferred to the second stage of the shift register 41, a right shift start pulse is output from the second stage of the shift register 41, and the first stage of the shift register 41 is output. Eye and second
The control signals for taking in data sequentially from the first stage are the first to sixth stages and the thirteenth to eighteenth stages and the seventh to twelfth and nineteenth stages of the data register circuit 42. To the 24th stage. The data register 42 is controlled by the control signal from the first stage of the shift register 41 every first horizontal period to each of the first to sixth stages and the thirteenth to eighteenth stages, and to the second stage. 7 to 12 and 19
Display data of 8 bits are respectively stored in each of the stages from the stage 24 to the j-th stage (j = 1, 2,..., 12) and (j + 1).
2) The display data is fetched so as to have the same display data at the first stage, the first stage, the third stage,
.., The display data taken in the 23rd stage is output to one input side of each of the first to twelfth stages of the first changeover switch 43, and the even number stage of the data register 42 The display data taken in the second stage, the fourth stage,..., The twenty-fourth stage is output to the other input sides of the first to twelfth stages of the first changeover switch 43. The first changeover switch 43 alternates display data input to one input side and the other input side of each of the first to twelfth stages in each horizontal period, and alternates the display data from the first to sixth stages. Seventh
The odd-numbered display data and the even-numbered display data are output differently from the first stage to the twelfth stage of the latch 44 from the first stage to the twelfth stage. Latch 44 is 1
The display data input from the first stage to the twelfth stage is input to the NROM decoder 46 inside the D / A converter 46 via the level shifter 45 at the edge of the latch input every horizontal period.
N-th and PROM decoders 46P from the first stage to the sixth stage
Batch output to the second row. The D / A converter 46 has an internal N
Based on the display data input to the first to sixth stages of the ROM decoder 46N, one of the 256 gray scale negative gray scale voltages is changed from the first to sixth stages of the second switch 47. And outputs one of the 256 gray-scale positive gray-scale voltages based on the display data input from the first to sixth stages of the internal PROM decoder 46P. The signals are output to the other input sides of the first to sixth stages of the changeover switch 47, respectively. The second changeover switch 47 sets a voltage between the negative gray scale voltage input to one input side and the positive gray scale voltage input to the other input side of each of the first to sixth stages for each horizontal period. The first stage, the third stage,..., The eleventh stage, which is an odd stage of the follower output circuit 48, and the second stage, the fourth stage,.
The output is alternately output to the second stage. The voltage follower output circuit 48 converts the negative gray scale voltage and the positive gray scale voltage input to each of the first to twelfth stages so that the polarity is different between the odd-numbered stages and the even-numbered stages so that one horizontal line is obtained. The data is alternately output to the odd data lines and the even data lines for each period.

As described above, the number of stages of the data register 42 is twice the number of outputs of the drive circuit block 33, and the first to twelfth stages are used for the NROM decoder 46N.
The same display data is taken in the j-th (j = 1, 2,..., 12) and (j + 12) -th stages for the 3rd to 24th stages for the PROM decoder 46P. The number of stages of the first switch 43 is determined by the drive circuit block 3
3, the i-th stage (i = 1, 3, 3) of the data register 42 adjacent to the first to twelfth stages of the data register 42.
.., 11) display data from the odd-numbered stage and the (i + 1) -th even-numbered stage from the first changeover switch 43 and the latch 4
4 through the first to sixth stages of the NROM decoder 46
In the first to sixth stages of N, the display data from the (i + 12) th and (i + 13) th stages adjacent to the thirteenth to twenty-fourth stages are transferred to the first changeover switch 43 and Through the seventh to twelfth stages of the latch 44, the first to sixth stages of the PROM decoder 46P, the first to sixth stages, and the seventh to twelfth stages By making the polarity different and supplying alternately every horizontal period,
The wiring 53 between the first switch 43 and the latch 44 can be connected to each of the first stage, the second stage,..., The twelfth stage, and there is no intersection between the stages. Wiring that runs laterally between the
Accordingly, the dimension of the semiconductor chip 31 in the short direction can be reduced. If the short dimension of the conventional semiconductor chip 1 is, for example, 2.5 mm, the short dimension of the semiconductor chip 31 in this embodiment can be reduced by about 0.5 mm, and the short dimension of the semiconductor chip 31 can be reduced. In addition, the chip area can be reduced by about 20%.

[0016]

According to the present invention, the wiring between the first changeover switch and the latch constituting each drive circuit block of the internal circuit disposed on the semiconductor chip as a semiconductor integrated circuit device is prevented from intersecting between the wirings. This eliminates the need for a wiring running laterally between the first changeover switch and the latch, thereby reducing the size of the semiconductor chip in the short direction, and reducing the frame size of the liquid crystal display module when used in a liquid crystal display device. Since the effective screen ratio (display area / outermost area of the module) can be increased and the area of the semiconductor chip itself can be reduced, the production cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a semiconductor chip as an integrated circuit device according to one embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a circuit block arranged on the semiconductor chip of FIG. 1;

FIG. 3 is a schematic plan view of a semiconductor chip as a conventional integrated circuit device.

FIG. 4 is a schematic configuration diagram of a circuit block arranged on the semiconductor chip of FIG. 3;

FIG. 5 is a schematic structural view of a liquid crystal display module.

FIG. 6 is a block diagram showing a configuration of a horizontal driver of the liquid crystal display module of FIG. 5;

[Explanation of symbols]

 31 semiconductor chip 32 internal circuit 33 drive circuit block 41 shift register 42 data register 43 first switch 44 latch 45 level shifter 46 D / A converter 46N NROM decoder 46P PROM decoder 47 second switch 48 voltage follower output circuit

Claims (2)

[Claims] An n drive circuit block having m outputs is arranged in a longitudinal direction of a long rectangular semiconductor chip, and a positive drive voltage and a negative drive voltage are obtained from the outputs by an odd output and an even output. An output circuit for alternately outputting every one horizontal period so that the polarity of the output signal is different from that of a second output signal, wherein the drive circuit block has a 2m-stage data register that takes in a plurality of bits of display data in each stage; , (I = 1, 3,..., 2m-1) and (i
+1) A two-input, one-output m-stage first changeover switch for alternately outputting the display data taken in the first stage every one horizontal period, and the first changeover switch is connected and the first changeover switch is connected to the first changeover switch. An m-stage latch for collectively outputting display data from each stage of the changeover switch for each horizontal period, and the first stage to the (m / 2) th stage of this latch are connected to output a unipolar drive voltage. (M / 2) -stage one-conductivity ROM
A (m / 2) -stage (m / 2) -stage other-conductivity-type ROM decoder connected to the (m / 2) + 1-th to (2m) -th stages of the decoder and the latch and outputting a driving voltage of another polarity; And a two-input / two-output second switching circuit connected to the D / A converter and alternately outputting the one-polarity drive voltage and the other-polarity drive voltage every one horizontal period. And the display data taken into the data register is the j-th stage (j = 1, 2, 2,
, M) and the (j + m) -th stage, and the first
The changeover switch converts the display data taken in the i-th stage and the (i + 1) -th stage of the data register from the first stage to the (m / 2) -th stage and the ((m / 2) +1) -th stage. Second from eyes
An integrated circuit device that outputs differently at the m-th stage. 2. A liquid crystal display device wherein the integrated circuit device according to claim 1 is mounted on a tape carrier package for driving data lines of a liquid crystal panel.