KR100942838B1 - Apparatus of Driving Liquid Crystal Display Device - Google Patents

Abstract

The present invention relates to a driving device of a liquid crystal display device which enables left / right division driving in a liquid crystal display device including an odd number of data integrated circuits.

The driving apparatus of the liquid crystal display device of the present invention includes a liquid crystal panel driven by being divided into a left part and a right part, at least one first data integrated circuit for supplying first data to data lines formed in the left part, and a right part formed in the right part. The first data and the second data by at least one second data integrated circuit for supplying second data to the data lines; And a third data integrated circuit for supplying the first and second data alternately, and supplying a first source shift clock to the first data integrated circuit and the third data integrated circuit. Supplying a second source integrated clock to the second data integrated circuit and the third data integrated circuit having a phase different from that of the source shift clock. A timing control unit is provided.

Description

Apparatus of Driving Liquid Crystal Display Device             

1 is a view showing a conventional liquid crystal display device.

2 is a view showing a liquid crystal display device according to another conventional embodiment.

3 is a diagram illustrating a data integrated circuit included in the data driver illustrated in FIG. 2.

FIG. 4 is a block diagram showing a detailed configuration of the data integrated circuit shown in FIG.

FIG. 5 is a waveform diagram showing signals supplied to data integrated circuits in the left and right portions shown in FIG. 2; FIG.

6 is a view showing a liquid crystal display device according to an embodiment of the present invention.

FIG. 7 is a block diagram showing a detailed configuration of a data integrated circuit located at the boundary between the left side and the right side shown in FIG.

<Description of Symbols for Main Parts of Drawings>

2,12,52 LCD panel 4: Data driver

6: gate driver 8,22,68: timing controller                 

10: common voltage generator 14,54: left side

16,56: right part 18,20,58,60: data driver

24,64,66: integrated circuit 30,120: signal controller

32,118: gamma voltage section 34,104,105: shift register section

36,106: latch portion 38,108: digital-analog conversion portion

40, 42, 110, 112: decoding unit 44, 114: multiplexer

46,116: output buffer part

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a liquid crystal display device, and more particularly, to a driving device of a liquid crystal display device which enables left / right division driving in an LCD including an odd data integrated circuit.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display device includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel. The driving circuit drives the pixel matrix so that the image information is displayed on the display panel.

1 is a view showing a conventional liquid crystal display device.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 2, a data driver 4 for driving data lines DL1 to DLm of the liquid crystal panel 2, and a liquid crystal panel 2. A gate driver 6 for driving the gate lines GL0 to GLn of the gate line, a timing controller 8 for controlling the driving timing of the data and gate drivers 4 and 6, and a common voltage Vcom for the liquid crystal cell. ) Is provided with a common voltage generator 10.

The timing controller 8 receives a dot clock DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE, data, and the like from an external system. The timing controller 8 that receives the data rearranges the data and supplies the data to the data driver 4. The timing controller 8 receiving the dot clock, the horizontal synchronization signal, the vertical synchronization signal, and the data enable signal receives control signals such as timing signals and polarity inversion signals for controlling the timing of the data and gate drivers 4 and 6. Will occur.

The liquid crystal panel 2 is connected to the thin film transistor TFT formed at the intersection of the n gate lines GL1 to GLn and the m data lines DL1 to DLm, and is formed in a matrix form. The liquid crystal cells are arranged as.

The thin film transistor TFT supplies data from the data lines DL1 to DLm to the liquid crystal cell in response to gate signals from the gate lines GL1 to GLn. The liquid crystal cell is composed of a common electrode facing each other with a liquid crystal interposed therebetween, and a pixel electrode connected to the thin film transistor TFT, so that the liquid crystal cell may be equivalently represented as a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst connected to the previous gate line in order to maintain the data voltage charged in the liquid crystal capacitor Clc until the next data voltage is charged.

The gate driver 6 sequentially supplies gate signals to the gate lines GL1 to GLn according to a control signal from the timing controller 8. The data driver 4 converts the data R, G, and B supplied from the timing controller 8 into a video signal, which is an analog signal, and converts the data signal 4 into one video signal every 1 horizontal period in which the gate signals are supplied to the gate lines GL1 to GLn. The video signal for the horizontal line is supplied to the data lines DL1 to DLm.

The data driver 4 selects a gamma voltage having a predetermined DC level according to the luminance values of the data R, G, and B, and supplies the selected gamma voltage to the data lines DL1 to DLm.

The common voltage generator 10 generates a common voltage Vcom and supplies the generated common voltage Vcom to a common electrode which is one side of the liquid crystal capacitor Clc.

In the conventional liquid crystal display device, the dot clock has to have a high frequency because m pieces of data must be supplied to the data driver within one horizontal period. As such, when the dot clock has a high frequency, high electromagnetic interference (EMI) is generated in the liquid crystal display. In addition, the conventional liquid crystal display device has a problem in that a high transfer rate is required and a large power consumption is consumed because m data must be supplied to the data driver within one horizontal period.

In order to solve this problem, a liquid crystal display device according to another exemplary embodiment as shown in FIG. 2 has been proposed.

2 is a diagram illustrating a liquid crystal display according to another exemplary embodiment of the prior art. In the configuration of FIG. 2, detailed structures of the gate driver and the liquid crystal cell are omitted.

Referring to FIG. 2, a liquid crystal display according to another exemplary embodiment includes a liquid crystal panel 12 divided into a left portion 14 and a right portion 16, and data lines DL1 to DLm / of the left portion 14. 2) a first data driver 18 for driving the second data driver; a second data driver 20 for driving the data lines DLm / 2 + 1 to DLm of the right side 16; A timing controller 22 is provided for controlling the drive timing of the two data drivers 18 and 20.

The liquid crystal panel 12 is driven by being divided into a left portion 14 and a right portion 16. Here, the left part 14 and the right part 16 are driven simultaneously.

The timing controller 22 receives a data clock DCLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE, and data from an external system. The timing controller 22 receiving the data alternately supplies the data of the left side 14 and the right side 16 to the first data driver 18 and the second data driver 20. The timing controller 22 supplies the first source start pulse SSP1 and the first source shift clock SSCL to the first data driver 18, and also supplies the second source start pulse to the second data driver 20. SSP2 and the second source shift clock SSCR are supplied. In practice, the timing controller 22 further supplies control signals such as the polarity control signal POL and the source output enable SOE to the first and second data drivers 18 and 20, but is omitted for convenience of description. Shall be.

The first data driver 18 latches data of the left part 14 among data supplied from the timing controller 22 while being controlled by the first source start pulse SSP1 and the first source shift clock SSCL. 14 to the data lines DL1 to DLm / 2. The second data driver 20 controls the second source start pulse SSP2 and the second source shift clock SSCR to latch data of the right part 16 among the data supplied from the timing controller 22. Supply to lines DLm / 2 + 1 to DLm.

Each of the first data driver 18 and the second data driver 20 includes the same number of integrated circuits 24 as shown in FIG. 3. Each of the data ICs 24 converts an analog video signal and supplies the data supplied thereto to the data lines DL.

To this end, each of the data ICs 24 includes a shift register 34 for sequentially supplying a sampling signal as shown in FIG. 4, and sequentially latching and simultaneously outputting data in response to the sampling signal. A latch unit 36, a digital-to-analog converter (hereinafter referred to as a "DAC unit") 38 for converting data (Data) from the latch unit 36 into an analog video signal, and a DAC unit 38. And an output buffer section 46 for buffering and outputting video signals from the video signal.

In addition, each of the data ICs 24 includes a signal control unit 30 relaying control signals and data Data supplied from the timing control unit 22, and a positive and negative polarity required by the DAC unit 38. A gamma voltage unit 32 for supplying gamma voltages is provided. The data ICs 24 having this configuration drive i (eg, 384 and 480) channels and i data lines DL.                         

The signal controller 30 controls various control signals (SSP, SSC, SOE, REV, POL, etc.) and data from the timing controller 22 to be output to the corresponding components.

The gamma voltage unit 12 subdivides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The shift register unit 34 includes a plurality of shift registers to sequentially shift the source start pulses SSP1 or SSP2 from the signal controller 30 in response to the source sampling clock SSCL or SSCR to output the sampling signals. .

The latch unit 36 sequentially samples and latches the data Data from the signal control unit 30 in predetermined units in response to the sampling signal from the shift register unit 34. To this end, the latch unit is composed of i latches to latch i data, each of which has a size corresponding to the number of bits (eg, 3 bits or 6 bits) of the data. The latch unit 36 simultaneously outputs the n pieces of latched data in response to a source output enable (SOE) signal from the signal controller 30.

The DAC unit 38 simultaneously converts the data Data from the latch unit 36 into positive and negative video signals and outputs the same. To this end, the DAC unit 38 includes a positive (P) decoding unit 40 and a N (Netative) decoding unit 42, and a P decoding unit 40 and an N decoding unit 42 commonly connected to the latch unit 36. Is provided with a multiplexer (MUX) 44 for selecting the output signal.

The i P decoders included in the P decoding unit 40 convert the data input from the latch unit 36 into a positive video signal. The i N decoders included in the N decoding unit 42 convert the data input from the latch unit 36 into a negative video signal.                         

The multiplexer (MUX) 44 selectively outputs video signals from the P decoding unit 40 and the N decoding unit 42 in response to the polarity control signal POL from the signal control unit 30. The output buffer unit 46 buffers the video signals from the multiplexer 44 and supplies them to the data lines DL.

Meanwhile, the first source shift clock SSCL and the second source shift clock SSCR supplied from the timing controller 22 are alternately supplied as shown in FIG. 5. In other words, the second source shift clock SSCR has a low signal when the high signal of the first source shift clock SSCL has a low signal, and the second source shift clock SSCR when the low signal of the first source shift clock SSCL has a low signal. Has a high signal.

Here, the data of the left portion 14 supplied from the timing controller 22 when the high signal of the first source shift clock SSCL is latched by the data IC 24 provided in the left portion 14 and the second source shift clock ( At the high signal of the SSCR, the data of the right side 16 supplied from the timing controller 22 is latched by the data IC 24 provided in the right side 16. That is, in the related art, data of the left part 14 and the right part 16 alternately output from the timing controller 22 by alternately supplying the first source shift clock SSCL and the second source shift clock SSCR. Can be supplied exactly.

Also, since the liquid crystal display shown in FIG. 2 supplies m / 2 pieces of data to each of the first and second data drivers 18 and 20 during one horizontal period, the frequency is lower than that of the liquid crystal display shown in FIG. Has a data clock of EMI, thereby reducing EMI. In addition, since m / 2 pieces of data are supplied to the first and second data drivers 18 and 20, respectively, transmission speed and power consumption can be lowered as compared to the liquid crystal display shown in FIG. It can be easily applied to a large screen liquid crystal display.

However, in order to divide the liquid crystal panel 12 into the left portion 14 and the right portion 16 as shown in FIG. 2, the liquid crystal panel 12 is included in the first data driver 18 and the second data driver 20. The number of integrated circuits (hereinafter referred to as "ICs") must be the same (i.e., the total number of data ICs must be set to an even number).

In other words, the first data driver 18 and the second data driver 20 alternately receive data from the timing controller 22. Therefore, simultaneous driving is possible only if the number of data ICs (D-ICs) 24 included in each of the data drivers 18 and 20 is the same. If the number of data ICs 24 included in the first and second data drivers 18 and 20 is different, the amount of data to be supplied to the first data driver 18 or the second data driver 20 is different. As a result, the liquid crystal panel 12 cannot be divided into the left portion 14 and the right portion 16.

On the other hand, currently used data ICs 24 are released with a fixed number of channels. For example, the data IC 24 has a fixed number of channels, such as 384 channels and 480 channels. As described above, since the number of channels of the data IC 24 is fixed and released, the liquid crystal panel 12 may not be divided into the left portion 14 and the right portion 16. For example, in the case of the SVGA (800 × 600) class liquid crystal panel 12, 800 × 3 (R, G, B subpixels) = 2400 (number of data lines) channels are required.

Here, the liquid crystal panel 12 is conventionally driven by using seven data ICs 24 having 384 channels (2688 channels). That is, in the conventional SVGA class liquid crystal panel 12, seven data ICs 24 are used, and thus, the liquid crystal panel 12 cannot be divided into the left portion 14 and the right portion 16.

Accordingly, an object of the present invention is to provide a driving device of a liquid crystal display device which enables left / right division driving in a liquid crystal display device including an odd number of data integrated circuits.

In order to achieve the above object, the driving apparatus of the liquid crystal display device of the present invention includes a liquid crystal panel driven by being divided into a left part and a right part, and at least one first data integrated circuit for supplying first data to data lines formed at the left part. And at least one second data integrated circuit for supplying second data to the data lines formed on the right side, the data lines formed on the left side and the data lines formed on the left side and positioned at the boundary of the left and right sides. A third data integrated circuit for supplying the first data and the second data, the first data and the second data are alternately output, and the first source shift clock is supplied to the first data integrated circuit and the third data integrated circuit. And a second source shift clock having a phase different from that of the first source shift clock. And a timing controller for supplying the data to the three data integrated circuits.

The timing controller supplies a first source start pulse to any one of the first data integrated circuits formed on the left side and a second source start pulse to the third data integrated circuit.

The first source shift clock and the second shift clock have a phase difference of 180 degrees.

The third data integrated circuit includes a first shift register for supplying i / 2 first sampling signals (i is a natural number) to the first to i / 2th latches when the first source shift clock and the carry signal are input. And a second for supplying i / 2 (i is a natural number) second sampling signal to the i / 2 + 1 th latch to the i th latch when the second source shift clock and the second source start pulse are input. A shift register section and a latch section for latching the first and second data in response to the first and second sampling signals supplied from the first shift register section and the second shift register section.

The latch unit latches the first data when the first sampling signal is input and latches the second data when the second sampling signal is input.

The carry signal is supplied from a first data integrated circuit provided at the left side.

The third data integrated circuit may include a digital-to-analog converter for receiving the first and second data stored in the latch unit and converting the first and second data into a positive video signal and a negative video signal; And an output buffer section for supplying the first and second data to i data lines connected thereto.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 7.

6 is a view showing a liquid crystal display device according to an embodiment of the present invention.

Referring to FIG. 6, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel 52 divided into a left portion 54 and a right portion 56, and data lines DL1 to DLm / of the left portion 54. 2) a first data driver 58 for driving the second data driver; a second data driver 60 for driving the data lines DLm / 2 + 1 to DLm of the right part 56; The timing control part 68 is provided for controlling the drive timing of the two data drive parts 58 and 60.

The liquid crystal panel 52 is divided into a left portion 54 and a right portion 56 to be driven. Here, the left portion 54 and the right portion 56 are driven at the same time.

The timing controller 68 receives a data clock DLCK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, a data enable DE, and data from an external system. The timing controller 68 that receives the data alternately outputs data of the left portion 54 and data of the right portion 56.

In addition, the timing controller 68 receiving the data clock, the horizontal synchronization signal, the vertical synchronization signal, and the data enable signal includes timing signals and a polarity inversion signal for controlling the first and second data drivers 58 and 60. Generate the same control signals. Here, the timing controller 58 supplies the first source start pulse SSP1 and the first source shift clock SSCL to the first data driver 58 and the second source start to the second data driver 20. The pulse SSP2 and the second source shift clock SSCR are supplied.

Meanwhile, the first source shift clock SSCL is supplied to alternate with the second source shift clock SSCR as shown in FIG. 5. In other words, the second source shift clock SSCR has a low signal when the high signal of the first source shift clock SSCL has a low signal, and the second source shift clock SSCR when the low signal of the first source shift clock SSCL has a low signal. Has a high signal (has a phase difference of 180 degrees). The first source start pulse SSP1 is supplied to the first data driver 64 located at the left portion 54, and the second source start pulse SSP2 is supplied. It is supplied to the data driver 66 located at the left side 54 and the right side 56.

The first data driver 58 is controlled by the control signals (eg, polarity signals, source output signals, etc.), the first source shift clock SSCL and the first source start pulse SSP1 supplied thereto. Of the data supplied from the timing controller 68, only data of the left portion 54 is extracted and supplied to the data lines DL1 through DLm / 2. The second data driver 60 is controlled by the control signals (eg, polarity signal, source output signal, etc.), the second source shift clock SSCR, and the second source start pulse SSP2 supplied thereto. Of the data supplied from the timing controller 68, only the data of the right part 56 is extracted and supplied to the data lines DLm / 2 + 1 to DLm.

Here, the total number of data ICs 64, 66 included in the first and second data drivers 58, 60 is set to an odd number. Accordingly, the first and second data drivers 58 and 60 share the data IC 66 provided at the boundary between the left portion 54 and the right portion 56. In other words, the data IC 66 provided at the boundary between the left portion 54 and the right portion 56 supplies the video signal to the data lines DL of the left portion 54 and the right portion 56.

Referring to the operation process of the liquid crystal display according to the present invention, first, the timing controller 68 alternates the data of the left portion 54 and the right portion 56 with the first and second data drivers 58 and 60. To supply. In other words, the timing controller 68 supplies data in the order of DL1, DLm / 2 + 1, DL2, DLm / 2 + 2,...

The first data IC 64 of the left portion 54 latches data (supplied to DL1 to DLi) to be supplied to the left portion 54 in synchronization with the rising edge of the first source shift clock SSCL. When all the data are stored in the first data IC 64, the carry signal Carry is supplied to the second data IC 64, and thus the data to be supplied to the left portion 54 (DLi + 1 to DL2i). This second data IC 64 is latched. Similarly, when all the data are stored in the second data IC 64, a carry signal Carry is supplied to the data IC 66 of the boundary portion, and thus the data DL2i + 1 to DLm / 2 to be supplied to the left portion 54. Supply to a line) is latched to the data IC 66 located at the boundary portion.

On the other hand, the data IC 66 located at the boundary portion latches data (supply to DLm / 2 + 1 to DL3i) to be supplied to the right portion 56 in synchronization with the rising edge of the second source shift clock SSCR. do. When all data are stored in the data IC 66 positioned at the boundary, a carry signal Carry is installed at the right side 56 and then supplied to the data IC 64 to sequentially supply data to the right side 56. To latch. Here, the configuration and operation of the remaining data ICs 64 except for the data IC 66 positioned at the boundary between the left portion 54 and the right portion 56 are the same as those of the conventional data IC 24 shown in FIG. 4. Therefore, detailed description will be omitted.

Fig. 6 is a diagram showing the detailed configuration of the data IC 66 located at the boundary between the left side and the right side.

Referring to FIG. 6, the data IC 66 positioned at the boundary part includes first and second shift registers 104 and 105 for sequentially supplying sampling signals, and latches data in response to the sampling signals. A latch unit 106, a DAC unit 108 for converting data from the latch unit 106 into an analog video signal, and an output buffer unit for buffering and outputting the video signal from the DAC unit 108 ( 116.

In addition, the data IC 66 includes a signal controller 120 for relaying control signals and data supplied from the timing controller 68, and a positive and negative gamma voltage required by the DAC unit 108. And a gamma voltage unit 118 for supplying them. The data IC 66 having such a configuration drives i (i is a natural number, for example, i is 348, 480) channels, i.e., i data lines DL2i + 1 to 3i.

The signal controller 120 outputs control signals (SOE, POL, etc.) and data supplied from the timing controller 68 to the corresponding components. In addition, the signal controller 120 supplies a carry signal Carry supplied from the first source shift clock SSCR and the previous stage data IC 64 to the first shift register 104, and the second source shift. The clock SSCL and the second source start pulse SSP2 are supplied to the second shift register 105.

The gamma voltage unit 118 divides and outputs a plurality of gamma reference voltages inputted from a gamma reference voltage generator (not shown) for each gray.

The first shift register 104 includes a plurality of shift registers to sequentially shift the carry signal Carry supplied from the signal controller 120 in correspondence to the first source shift clock SSCR to output a sampling signal. . Here, the sampling signal output from the first shift register section 104 is supplied to the first latches to i / 2 latches included in the latch section 106. The second shift register unit 105 includes a plurality of shift registers to sequentially shift the second source start pulse SSP2 supplied from the signal controller 120 to correspond to the second source shift clock SSCL to sample the signal. Outputs Here, the sampling signal output from the second shift register section 105 is supplied to the i / 2 + 1 th latch to the i th latch included in the latch section 106.

The latch unit 106 latches data supplied from the signal controller 120 in response to a sampling signal supplied from the first shift register 104 or the second shift register 105. For this purpose, the latch unit 106 is composed of i latches for latching i data, each of which has a size corresponding to the number of bits (for example, 3 bits or 6 bits) of the data. Have The latch unit 106 simultaneously outputs the latched i data in response to the source output enable (SOE) signal from the signal controller 120.

The DAC unit 108 converts the data from the latch unit 106 into positive and negative video signals at the same time and outputs the same. To this end, the DAC unit 108 selects the P decoding unit 110 and the N decoding unit 112 and the output signals of the P decoding unit 110 and the N decoding unit 112 commonly connected to the latch unit 106. A multiplexer (MUX) 114 is provided.

The i P decoders included in the P decoding unit 110 convert the data input from the latch unit 106 into a positive video signal. The i N decoders included in the N decoding unit 112 convert the data input from the latch unit 106 into a negative video signal.

The multiplexer 114 selectively outputs video signals from the P decoding unit 110 and the N decoding unit 112 in response to the polarity control signal POL from the signal controller 120. The output buffer unit 116 buffers the video signals from the multiplexer 114 and supplies them to the data lines DL2i + 1 to DL3i.

Referring to the operation process of the data IC 66 as described above, first, the timing controller 68, the second source start pulse (SSP2), the first source shift clock (SSCR), the second source shift clock (SSCL) and the control signal To the signal controller 120. The signal controller 120 supplies the second source shift clock SSCL and the second source start pulse SSP2 supplied thereto to the second shift register 105, and supplies the first source shift clock SSCR to the first source shift clock SSCR. One shift register 104 is supplied. The control signals and data are output to the corresponding components.

The second shift register part 105 supplied with the second source shift clock SSCL and the second source start pulse SSP2 is synchronized with the rising edge of the second source shift clock SSCL so that the second source start pulse SSP2 is synchronized. Is generated while the sampling signal is shifted, and is supplied to the latch unit 106. Then, desired data (supply to DLm / 2 + 1 to DL3i) is stored in the i / 2 + 1 th latch to the i th latch of the latch unit 106. The second shift register unit 105 generates and supplies a carry signal Carry2 to the next data IC 64.

After a predetermined time, a carry signal Carry is supplied to the signal controller 120 from the data IC 64 of the previous stage. The signal controller 120 supplies a carry signal Carry supplied thereto to the first shift register 104. Then, the first shift register unit 104 supplied with the first source shift clock SSCR and the carry signal Carry shifts the carry signal Carry to be synchronized with the rising edge of the first source shift clock SSCR. The sampling signal is generated and supplied to the latch unit 106. At this time, desired data (supplied to DL2i + 1 to DLm / 2) is stored in the first latch to i / 2 latch of the latch unit 106.

Data stored in the latch unit 106 is supplied to the DAC 108 in response to a source output enable (SOE) signal. The DAC 108 converts the data supplied thereto to the positive and negative video signals and supplies them to the multiplexer 114. The multiplexer 114 selectively outputs the positive and negative video signals in response to the polarity control signal POL, and the video signals are temporarily stored in the output buffer unit 116 and then the data lines DL2i + 1 to DL3i. ).

In the present invention as described above, since one data IC 66 can be shared in the left portion 54 and the right portion 56, left / right division driving is possible in an LCD including an odd data integrated circuit. Become. In other words, even in the SVGA-class liquid crystal panel using seven 384 channel-class data ICs, left / right split driving can be performed, thereby reducing power consumption, EMI, and transmission speed.

As described above, according to the driving apparatus of the liquid crystal display device according to the present invention, since one data IC is shared by the left and right parts of the liquid crystal panel, the left and right sides of the liquid crystal display device including an odd data integrated circuit are also driven. It is possible to drive. That is, in the present invention, regardless of the number of data integrated circuits, all of the liquid crystal panels may be driven by being divided into left and right parts, thereby achieving effects such as power consumption reduction, EMI reduction, and transmission speed improvement.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

A liquid crystal panel driven by being divided into a left part and a right part, At least one first data integrated circuit for supplying first data to data lines formed in the left part; At least one second data integrated circuit for supplying second data to the data lines formed on the right side; A third data integrated circuit positioned at a boundary between the left and right parts and supplying first data and second data to data lines formed at the left part and data lines formed at the right part, respectively; A second source that alternately outputs the first data and the second data and supplies a first source shift clock to the first data integrated circuit and the third data integrated circuit and has a phase different from that of the first source shift clock; And a timing controller for supplying a shift clock to the second data integrated circuit and the third data integrated circuit. The method of claim 1, The timing controller is configured to supply a first source start pulse to any one of the first data integrated circuits formed in the left part and to supply a second source start pulse to the third data integrated circuit. Driving device for the liquid crystal table market value. 3. The method of claim 2, And the first source shift clock and the second shift clock have a phase difference of 180 degrees. The method of claim 3, The third data integrated circuit A first shift register section for supplying i / 2 first sampling signals (i is a natural number) to first to i / 2th latches when the first source shift clock and the carry signal are input; A second shift register for supplying i / 2 (i is a natural number) second sampling signal to the i / 2 + 1 th latch to the i th latch when the second source shift clock and the second source start pulse are input; Wealth, And a latch unit for latching the first and second data in response to first and second sampling signals supplied from the first shift register unit and the second shift register unit. The method of claim 4, wherein And the latch unit latches the first data when the first sampling signal is input and latches the second data when the second sampling signal is input. The method of claim 4, wherein And said carry signal is supplied from a first data integrated circuit provided in said left portion. The method of claim 4, wherein The third data integrated circuit A digital-analog converter for receiving first and second data stored in the latch unit and converting the first and second data into a positive video signal and a negative video signal; And an output buffer unit for supplying the first and second data converted by the digital-analog converter to i data lines connected thereto.

Images