KR20060000896A - Memory device and method for fabricating the same - Google Patents

Abstract

Disclosed are a semiconductor memory device and a method of fabricating the same, which improves a problem in that the dopants of a plug are out-diffused at the storage node contact without degrading the bit line contact resistance, thereby reducing the refresh characteristics of the device. The semiconductor memory device of the present invention for this purpose, a plurality of gate patterns formed on the semiconductor substrate; A storage node contact junction region formed under the surface of the semiconductor substrate on one side of the gate pattern; A bit line contact junction region formed under the surface of the semiconductor substrate on the other side of the gate pattern; A trench formed by etching a portion of the semiconductor substrate in the storage node contact junction region; A dopant diffusion barrier layer formed on a sidewall of the semiconductor substrate in the trench to prevent the dopant in the storage node contact plug from being out-diffused; A storage node contact plug formed on one side of the gate pattern including an inside of the trench; And a bit line contact plug formed on the other side of the gate pattern.

Memory device, bit line contact plug, stray node contact plug, trench, dopant diffusion prevention

Description

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME             

1 is a cross-sectional view of a cell region of a memory device in which a contact plug is formed according to the prior art.

2 is a cross-sectional view showing a characteristic structure of a semiconductor memory device according to the present invention.

3 is a cross-sectional view of a cell region of a memory device in which a contact plug is formed according to an embodiment of the present invention.

4A through 4F are cross-sectional views illustrating a process of fabricating a memory device in accordance with a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

201: silicon substrate 202: device isolation film

203: gate insulating film 204: gate conductive layer

205: mask insulating film 206a: storage node contact junction region

206b: bit line contact junction region 207a: dopant diffusion barrier

208a: Storage Node Contact Plug 208b: Bitline Contact Plug

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a process of simultaneously manufacturing each contact plug of a bit line and a storage node in a DRAM device.

As is well known, a memory device such as a DRAM consists of a unit cell as one transistor and one capacitor, a bit line is contacted to one junction region of the cell transistor, and a storage node of the capacitor is connected to the other junction region of the cell transistor. To be contacted.

In order to solve the problem of contact failing in a miniaturized and highly integrated memory device, a contact forming technology for simultaneously forming contact plugs of a bit line and a storage node is used.

1 is a cross-sectional view of a memory device cell region in which bit line contact plugs and storage node contact plugs are formed in accordance with the prior art, with reference to this description.

First, the device isolation film 102 is formed on the silicon substrate 101, the gate oxide film 103, the gate conductive layer 104, and the mask nitride film 105 are sequentially stacked, and then stacked using a gate mask. The gate pattern G is formed by etching the films. The gate conductive layer 104 has a structure in which polysilicon 104a and tungsten silicide 104b are stacked.

Subsequently, source / drain junction regions 106a and 106b are formed by an impurity ion implantation process. The storage node will be in contact with the source (or drain) junction region 106a and the bit line will be in contact with the drain (or source) junction region 106b.

Subsequently, after the nitride film for the gate sidewall spacer is deposited, the nitride film spacer 107 is formed on the gate pattern sidewall by anisotropic etching.

Subsequently, deposition and polishing (or etch back) of a conductive layer such as doped polysilicon or doped epitaxial silicon are performed between the gate patterns G on which the spacers 107 are formed to form the bit line contact plug 108b and the storage. The node contact plug 108a is formed.

By the way, in the conventional memory device manufactured by the above-described method, the dopant in the storage node contact plug 108a is easily out-diffused into the junction region 106a. As a result, the junction region 106a and the channel region of the transistor doped with the impurity for controlling the threshold voltage are close to each other, and a problem arises in that the junction leakage current is generated by concentrating the electric field on the pn junction. Increasing the junction leakage current in the storage node contact junction region shortens the data retention time and degrades the refresh characteristics of memory devices such as DRAM.

An object of the present invention is to provide a semiconductor memory device and a method of manufacturing the same for suppressing out-diffusion of dopants of a storage node contact plug without deteriorating a bit line contact resistance.

One aspect of the present invention provides a memory device including: a plurality of gate patterns formed on a semiconductor substrate; A storage node contact junction region formed under the surface of the semiconductor substrate on one side of the gate pattern; A bit line contact junction region formed under the surface of the semiconductor substrate on the other side of the gate pattern; A trench formed by etching a portion of the semiconductor substrate in the storage node contact junction region; A dopant diffusion barrier layer formed on a sidewall of the semiconductor substrate in the trench to prevent the dopant in the storage node contact plug from being out-diffused; A storage node contact plug formed on one side of the gate pattern including an inside of the trench; And a bit line contact plug formed on the other side of the gate pattern.

In addition, another characteristic memory device of the present invention, the gate pattern formed on the semiconductor substrate; A storage node contact junction region formed under the surface of the semiconductor substrate on one side of the gate pattern; A bit line contact junction region formed under the surface of the semiconductor substrate on the other side of the gate pattern; First insulating film spacers formed on one side and the other sidewall of the gate pattern, respectively; A trench formed by etching a portion of the semiconductor substrate of the storage node contact junction region exposed by the insulating layer spacer; A second insulating film spacer formed on sidewalls of the first insulating film spacer and sidewalls of the semiconductor substrate inside the trench to prevent diffusion of the dopant of the storage node contact plug; A storage node contact plug formed at one side of the gate pattern including the trench and having the second insulating layer spacer formed thereon; And a bit line contact plug formed on the other side of the gate pattern on which the second insulating layer spacer is formed.

In another aspect, a method of manufacturing a memory device includes: forming a plurality of gate patterns having a predetermined interval on an upper surface of a semiconductor substrate; Forming a storage node contact junction region under the surface of the semiconductor substrate on one side of the gate pattern and forming a bit line contact junction region under the surface of the semiconductor substrate on the other side of the gate pattern; Etching a portion of the semiconductor substrate to form a trench; Forming a dopant diffusion barrier layer on a sidewall of the semiconductor substrate in the trench to prevent the dopant in the storage node contact plug from being out-diffused; And forming a storage node contact plug on one side of the gate pattern including the inside of the trench, and forming a bit line contact plug on the other side of the gate pattern.

In addition, another characteristic memory device manufacturing method includes forming a gate pattern on a semiconductor substrate; Forming a storage node contact junction region under the semiconductor substrate surface on one side of the gate pattern, and forming a bit line contact junction region under the semiconductor substrate surface on the other side of the gate pattern; Forming a trench by forming a first insulating layer spacer on sidewalls of one side and the other side of the gate pattern, and etching a portion of the semiconductor substrate of the storage node contact junction region exposed by the first insulating layer spacer; Forming a second insulating film spacer on sidewalls of one side and the other side of the gate pattern on which the first insulating layer spacer is formed and sidewalls of the semiconductor substrate inside the trench; And forming a storage node contact plug on one side of the gate pattern including the inside of the trench, and forming a bit line contact plug on the other side of the gate pattern.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a cross-sectional view showing a characteristic structure of a semiconductor memory device according to the present invention.

Referring to FIG. 2, an isolation layer 202 is formed on a silicon substrate 201 to define an active region and a field region, and a gate insulating layer 203, a gate conductive layer 204, and a mask are formed on the silicon substrate 201. The insulating layer 205 is stacked to form a plurality of gate patterns G. The gate patterns G are repeatedly formed at regular intervals. Instead of the silicon substrate 201, another semiconductor substrate such as a substrate having a silicon epitaxial layer may be used. The gate insulating layer 202 may be a single layer or a multilayer of a silicon oxide film, a silicon oxynitride film, or the like by thermal growth or / and deposition. Can be used as The gate conductive layer 204 has a structure in which polysilicon 204a and tungsten silicide 204b are stacked, or a gate electrode of other structure such as a metal / polysilicon structure electrode in which a metal such as tungsten is formed on polysilicon. Can be applied. Further, a nitride film or another insulating film may be used as the gate mask insulating film 205, and may be formed of a multilayer instead of a single layer.

Source / drain junction regions 206a and 206b are formed under the surface of the silicon substrate 201 on the side of the gate pattern G. The storage node will be in contact with the source (or drain) junction region 206a and the bit line will be in contact with the drain (or source) junction region 206b.

Importantly, the silicon substrate 201 of the storage node contact junction region 206a is partially etched to form a shallow trench T, and a dopant in the storage node contact plug 208a is bonded to the junction region 206a. A dopant diffusion barrier 207a is formed on the sidewalls of the substrate inside the trench T1 to prevent out-diffusion. The depth of the trench T is formed to be shallower than the depth of the junction region 206a.

As the dopant diffusion barrier 207a, a thin film such as a conductive film or an insulating film having a function of preventing dopant diffusion may be applied, but the dopant diffusion barrier 207a is also formed on the sidewall of the gate pattern G in a simplified sidewall of the process ( The reference numeral “207” is preferably formed of an insulating film for insulation between the gate pattern G and the contact plug 208a. In particular, since the interlayer insulating film for insulating between the gate and the bit line is mainly used as an oxide film, it is preferable that the interlayer insulating film is formed of a nitride film having an etching selectivity.

The storage node contact plug 208a is formed on the storage node contact junction region 206a including the inside of the trench T.

As described above, the semiconductor memory device according to the present invention is characterized in that the trench T is formed on the silicon substrate of the storage node contact junction region 206a and the dopant diffusion barrier layer 207a is formed on the sidewall of the trench T. As such, the dopant diffusion barrier prevents the dopant in the contact plug (i.e., the doped polysilicon) from diffusing in the direction of the junction region 206a adjacent to the channel region under the gate. That is, concentration of the electric field generated by bringing the junction region 206a and the channel region of the transistor closer to each other is prevented. Therefore, the junction leakage current is suppressed to prevent deterioration of the refresh characteristics of the memory device.

On the other hand, when the portion where the bit line is contacted is examined, the bit line contact plug 208b is formed on the bit line contact junction region 206b without the trench and the dopant diffusion barrier 207a. The reason why the trench T and the dopant diffusion barrier 207a are not formed differently from the storage node contact structure despite the process of simultaneously forming the transistor, the bit line, and the contact plug of the storage node in the cell region of the memory device. Is to prevent the bit line contact resistance from being lowered by the dopant diffusion prevention film 207a. In other words, since the bit line contact junction region 206b is not related to the refresh characteristics of the device, it is not necessary to form a trench and a dopant diffusion barrier layer up to the bit line contact junction region.

3 is a cross-sectional view of a cell transistor region of a memory device in which a storage node contact plug is formed according to an embodiment of the present invention.

Referring to FIG. 3, the gate oxide layer 303, the gate conductive layers 304a and 304b, and the mask nitride layer 304 are stacked on the silicon substrate 301 on which the device isolation layer 302 is formed, so that the gate pattern G is formed. Is formed. The storage node contact junction region 306a and the bit line contact junction region 306b are formed under the surface of the silicon substrate 301 near the gate pattern G.

An oxide film 307 is formed on the sidewall of the gate pattern G by re-oxidation after the gate pattern is etched and the deposition of the buffer oxide film, and a first nitride film spacer 308 is formed on the sidewall.

The silicon substrate 301 of the storage node contact junction region 306a exposed by the first nitride film spacer 308 is partially etched to form a thin trench. The depth of the trench is formed to be shallower than the depth of the junction region 305. In order to prevent the dopant in the storage node contact plug 310a from being out-diffused to the junction region 306a, the dopant diffusion barrier layer is extended from the sidewall of the gate pattern G to the sidewall of the substrate in the trench. A nitride film spacer 309 is formed.

A trench is not formed in the bit line contact junction region 306b, and a second nitride film spacer 309 is formed only on the sidewall of the gate pattern G.

Storage node contact plugs 310a and bit line contact plugs 310b are formed in the space between the gate pattern G including the trench and the second nitride film spacer.

4A through 4F are cross-sectional views illustrating a process of fabricating a memory device in accordance with a preferred embodiment of the present invention.

Referring to FIG. 4A, the gate oxide film 303, the gate conductive layer 304, and the mask nitride film 305 are sequentially stacked on the silicon substrate 301 having the device isolation film 302 formed thereon, and then using a gate mask. The gate pattern G is formed by etching the stacked films. A detailed process for forming the gate pattern G will be described. After the photoresist is applied and an exposure process using a gate mask (reticle) is formed, a photoresist pattern is formed by development, and then the photoresist pattern is used as an etching barrier to mask. The nitride layer 305 is etched, the photoresist is removed, and the gate conductive layer 303 is etched using the patterned mask nitride layer 305 as an etch barrier. The gate conductive layer 304 has a structure in which polysilicon 304a and tungsten silicide 304b are stacked.

Referring to FIG. 4B, gate light oxidation is performed for the purpose of etching damage during the formation of the gate pattern G and improvement of the characteristics of the gate oxide film 303, and the source / drain ion implantation process may be performed. After the junction regions 306a and 306b are formed, a buffer oxide film 307 is formed over the substrate. A storage node contact junction region 306a is formed under the silicon substrate surface on one side of the gate pattern G by a source / drain ion implantation process, and a bit line under the silicon substrate surface on the other side of the gate pattern G. Contact junction region 306b is formed.

Referring to FIG. 4C, the mask pattern 320 may be deposited on the entire surface of the resultant layer, the first nitride layer 308a for the gate sidewall spacer, the storage node contact junction region 306a may be opened, and the bit line contact junction region 306b may be masked. ). The mask pattern 320 may be a photoresist pattern.

Referring to FIG. 4D, the first nitride film 308a in the open region is anisotropically etched to form a first nitride film spacer, followed by the silicon of the storage node contact junction region 306a exposed by overetching. The substrate 301 is etched to form the trench T.

Referring to FIG. 4E, a second nitride film for preventing dopant diffusion is formed on the entire surface of the resultant with the mask pattern 320 removed, and the nitride film is anisotropically etched to form sidewalls and trenches of the gate pattern G. While forming the second nitride film spacer 309 on the sidewall of T), the storage node contact junction region 306a and the bit line contact junction region 306b are exposed.

Subsequently, as shown in FIG. 4F, contact plugs 310a and 310b are formed by depositing and polishing (or etching back) a conductive layer such as doped polysilicon or doped epitaxial silicon on the front surface of the resultant.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention provides a refresh characteristic due to a junction leakage current by forming a trench in a silicon substrate of a storage node contact junction region and providing a means for preventing diffusion of a dopant from the contact plug into the junction region on the trench sidewall. Deterioration can be prevented.

In addition, the present invention prevents the formation of the trench and the trench sidewall dopant diffusion barrier film by masking in the bitline contact junction region where the bitline contact plug is formed. As a result, the bit line contact resistance in the bit line contact portion where the junction leakage current is not a major issue can be prevented.

Claims (20)

A plurality of gate patterns formed on the semiconductor substrate; A storage node contact junction region formed under the surface of the semiconductor substrate on one side of the gate pattern; A bit line contact junction region formed under the surface of the semiconductor substrate on the other side of the gate pattern; A trench formed by etching a portion of the semiconductor substrate in the storage node contact junction region; A dopant diffusion barrier layer formed on a sidewall of the semiconductor substrate in the trench to prevent the dopant in the storage node contact plug from being out-diffused; A storage node contact plug formed on one side of the gate pattern including an inside of the trench; And Bit line contact plugs formed on the other side of the gate pattern A semiconductor memory device having a. The method of claim 1, And the dopant diffusion barrier layer is a spacer formed extending from one sidewall of the gate pattern to a sidewall of the semiconductor substrate in the trench. The method according to claim 1 or 2, And the spacer comprises nitride. The method according to claim 1 or 2, And the trench is formed to have a depth smaller than that of the storage node contact junction region. A gate pattern formed on the semiconductor substrate; A storage node contact junction region formed under the surface of the semiconductor substrate on one side of the gate pattern; A bit line contact junction region formed under the surface of the semiconductor substrate on the other side of the gate pattern; First insulating film spacers formed on one side and the other sidewall of the gate pattern, respectively; A trench formed by etching a portion of the semiconductor substrate of the storage node contact junction region exposed by the insulating layer spacer; A second insulating film spacer formed on sidewalls of the first insulating film spacer and sidewalls of the semiconductor substrate inside the trench to prevent diffusion of a dopant of a storage node contact plug; A storage node contact plug formed at one side of the gate pattern including the trench and having the second insulating layer spacer formed thereon; And Bit line contact plugs formed on the other side of the gate pattern on which the second insulating layer spacer is formed. Semiconductor memory device comprising a. The method of claim 5, And the insulating film spacer is a first nitride. The method of claim 6, And the second insulating film spacer is a second nitride. The method according to claim 6 or 7, And an oxide formed between the first nitride and the gate pattern. The method of claim 8, And the gate pattern is formed by stacking a gate insulating film, a gate conductive film, and a mask insulating film on a semiconductor substrate. The method of claim 5, And the trench is formed to have a depth smaller than that of the storage node contact junction region. Forming a plurality of gate patterns having a predetermined interval on the semiconductor substrate; Forming a storage node contact junction region under the surface of the semiconductor substrate on one side of the gate pattern and forming a bit line contact junction region under the surface of the semiconductor substrate on the other side of the gate pattern; Etching a portion of the semiconductor substrate in the storage node contact junction region to form a trench; Forming a dopant diffusion barrier layer on a sidewall of the semiconductor substrate in the trench to prevent the dopant in the storage node contact plug from being out-diffused; And Forming a storage node contact plug on one side of the gate pattern including the inside of the trench, and forming a bit line contact plug on the other side of the gate pattern Semiconductor memory device manufacturing method comprising a. The method of claim 11, And the dopant diffusion barrier layer is formed as a spacer extending from a sidewall of one side of the gate pattern to a sidewall of a semiconductor substrate in the trench. The method according to claim 11 or 12, wherein And the spacers comprise nitrides. Forming a gate pattern on the semiconductor substrate; Forming a storage node contact junction region under the semiconductor substrate surface on one side of the gate pattern, and forming a bit line contact junction region under the semiconductor substrate surface on the other side of the gate pattern; Forming a trench by forming a first insulating layer spacer on sidewalls of one side and the other side of the gate pattern, and etching a portion of the semiconductor substrate of the storage node contact junction region exposed by the first insulating layer spacer; Forming a second insulating film spacer on sidewalls of one side and the other side of the gate pattern on which the first insulating layer spacer is formed and sidewalls of the semiconductor substrate inside the trench; And Forming a storage node contact plug on one side of the gate pattern including the inside of the trench, and forming a bit line contact plug on the other side of the gate pattern Semiconductor memory device manufacturing method comprising a. The method of claim 14, Forming the first insulating film spacer and the trench, Depositing an insulating film on a substrate on which the gate pattern is formed; And And anisotropically etching the insulating layer by opening the storage node contact junction region and masking the bit line contact junction region. The method of claim 15, The trench is a semiconductor memory device manufacturing method, characterized in that formed by the transient etching during the anisotropic etching. The method of claim 14, And the first insulating film spacer is a first nitride. The method of claim 17, And the second insulating film spacer is a second nitride. The method of claim 17 or 18, The method of claim 1, further comprising an oxide formed between the first nitride and the gate pattern. The method of claim 14, The gate pattern is a semiconductor memory device manufacturing method, characterized in that the gate insulating film, the gate conductive film and the mask insulating film is formed on the semiconductor substrate stacked.

Images