KR20050121867A - Driving method of plasma display panel - Google Patents

Abstract

The present invention provides a method of driving a plasma display panel by a driving waveform consisting of a reset period, an address period, and a sustain discharge period, wherein a voltage having a scan high level is applied to a plurality of the first electrodes in the address period. And scanning pulses having a scan low level lower than the scan high level are sequentially applied to each of the first electrodes, and display data signals for the first electrodes to which the scanning pulses are applied to the address electrodes are applied. An address bias voltage is applied to the second electrodes, and in the sustain discharge period, a sustain pulse having the same pulse size as the scan pulse is alternately applied to the plurality of first electrodes and the plurality of second electrodes. It is characterized by being applied.

Description

Driving method of plasma display panel {Driving method of plasma display panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel, and more particularly, a scan pulse applied to an Y period and a sustain pulse applied to an organic discharge period in one subfield including a reset period, an address period, and a sustain discharge period. The present invention relates to a plasma display panel driving method which can reduce the manufacturing cost of the driving apparatus by making the same pulse size.

In a typical plasma display panel, the Y sustain electrodes and the X sustain electrodes are formed to be parallel to each other between the front substrate and the rear substrate which are spaced apart from each other, and the address electrodes are formed to cross the Y and X sustain electrodes. For the Y and X sustain electrodes and the address electrodes, the unit frame is divided into a plurality of subfields for time division gray scale display, and resetting, addressing, and display-holding steps are performed in each of the subfields. The drive signal waveform is applied so as to.

FIG. 1 shows driving signals applied to electrodes of a plasma display panel in each unit subfield according to a waveform diagram showing a plasma display panel driving signal. The conventional resetting method included in the driving method of Fig. 1 is taught in Japanese Laid-Open Patent Publications 214,823 and 242,224.

Referring to FIG. 1, in the rising period of the resetting time PR of the unit subfield SF, the potential increases from the Y electrodes X ₁ ,..., X _n to the second potential V _T. The voltage is continuously raised to the first potential V _T + V _{SET which} is higher by the fifth potential V _SET than the next second potential V _T. Here, the ground potential V _G is applied to the X electrodes X ₁ ,..., X _n and the address electrodes A ₁ ..., A _m . Accordingly, a weak discharge occurs between the Y electrodes and the X electrodes, while a weaker discharge occurs between the Y electrodes and the address electrodes. As a result, many negative wall charges are formed around the Y electrodes, positive wall charges are formed around the X electrodes, and less positive wall charges are formed around the address electrodes.

In the falling period of the reset time PR, while the potential applied to the X electrodes is maintained at the bias potential Ve, the potential applied to the Y electrodes is changed from the second potential V _S to the third potential ( V _nf ) is continuously lowered. Here, the ground potential V _G is applied to the address electrodes. Thus, due to the weak discharge between the X electrodes and the Y electrodes, some of the negative wall charges around the Y electrodes move around the X electrodes. Accordingly, the wall electric-potential of the X electrodes X ₁ ,..., X _n is lower than the wall potential of the address electrodes and higher than the wall potential of the Y electrodes. Accordingly, the addressing voltage V _A -V _SC-L required for the counter discharge between the selected address electrodes and the Y electrode line in the subsequent addressing period PA may be lowered. Meanwhile, since the ground potential V _G is applied to all the address electrodes, the address electrodes discharge the X electrodes and the Y electrodes, and the positive wall charges around the address electrodes disappear due to the discharge. .

In the subsequent addressing period PA, in the state in which the bias voltage Ve is applied to the X electrodes, the display data signal is applied to the address electrodes, and the sixth potential V _{SC− which} is lower than the second potential V _{S. As} the scan pulses of the low level potential V _SC-L are sequentially applied to the Y electrodes biased with _H ), smooth addressing may be performed. As for the display data signal applied to each address electrode, the positive addressing potential V _A is applied when the display cell is selected, and the ground potential V _G is applied when the display cell is not selected. Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the low level potential V _SC-L is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges are not formed in the display cell.

In the subsequent sustain discharge period PS, sustain pulses of the second potential V _S are alternately applied to all the Y electrodes and the X electrodes, thereby displaying the display cells in which wall charges are formed at the corresponding addressing time PA. -Cause a discharge for maintenance.

On the other hand, in the signal waveform diagram according to the conventional driving method as described above, the address discharge is a scan of the scanning pulse applied to the Y electrode at the potential of the display data signal voltage V _A and the positive charge accumulated near the address electrode. It is caused by the energy (that is, the sum of the absolute values of all the potentials) minus the potential due to the negative charge accumulated near the low level voltage V _SC-L and the Y electrode.

1, scan pulses V _{SC -H} -V _SC-L are sequentially applied to a plurality of Y electrodes in an address period, and sustain pulses Vs are simultaneously applied in a sustain discharge period. do. As such, since all power supply circuits and switching circuits to which the scan pulses and the sustain pulses are to be applied must be connected to all the Y electrodes, there is a problem in that the manufacturing cost of the driving device is large.

In addition, since the power supply circuit and the switching circuit to which the sustain pulse is to be applied to all the X electrodes must be connected, there is a problem in that the manufacturing cost of the driving device is large.

Accordingly, there is a need for a method of reducing the manufacturing cost of a driving device that applies a driving signal to the electrodes of the plasma display panel.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method for driving a plasma display panel which can lower the manufacturing cost of a driving apparatus for applying a driving signal to the electrodes of the plasma display panel. To provide.

The present invention for achieving the above technical problem,

A method of driving a plasma display panel by a drive waveform consisting of a reset period, an address period, and a sustain discharge period,

In the address period, a voltage having a scan high level V _{SC -H} is applied to the plurality of first electrodes, and a scan low level V _{SC -L} lower than the scan high level is applied to each of the first electrodes. Scan pulses are sequentially applied, display data signals V _A1 are applied to the first electrodes to which the scan pulses are applied, and address bias voltage Ve1 is applied to the second electrodes. Licensed,

In the sustain discharge period, sustain pulses Vs having the same pulse size (V _SC-H -V _SC-L ) as the scan pulse are alternately applied to the plurality of first electrodes and the plurality of second electrodes. It is characterized in that applied to.

According to another feature of the invention, in the reset period, the first initialization discharge and the reference potential by the ramp-up pulse is started to be applied to the first electrodes from the voltage higher than the reference potential by the pulse size of the scanning pulse, The second initialization discharge may be caused by the start of the rampdown pulse from the voltage higher by the size of the scan pulse.

In addition, the present invention provides a method of driving a plasma display panel by a driving waveform consisting of a reset period, an address period, and a sustain discharge period.

In the address period, a voltage having a scan high level V _{SC -H} is applied to the plurality of first electrodes, and a scan low level V _{SC -L} lower than the scan high level is applied to each of the first electrodes. Scan pulses are sequentially applied, and a display data signal V _A1 for the first electrode to which the scan pulses are applied is applied to the address electrodes,

In the sustain discharge period, the positive sustain pulse (+ Vs) and the negative sustain pulse (-Vs) having the same pulse size (V _{SC -H} -V _{SC -L} ) as the scan pulses on the plurality of first electrodes. Are alternately authorized,

A fixed voltage is applied to the second electrodes.

According to another feature of the invention, in the reset period, the first initialization discharge and the reference potential by the ramp-up pulse is started to be applied to the first electrodes from the voltage higher than the reference potential by the pulse size of the scanning pulse, The second initialization discharge may be caused by the start of the rampdown pulse from the voltage higher by the size of the scan pulse.

On the other hand, the methods can be realized through a computer by means of a recording medium which records a program for execution on the computer.

Hereinafter, the configuration and operation of a method of driving a plasma display panel according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The basic concept of the method for driving a plasma display panel according to the present invention is the sustain applied to the scanning pulse and the organic discharge period applied to the address period to the Y electrode in one subfield including a reset period, an address period and a sustain discharge period. The present invention provides a method of driving a plasma display panel which can reduce the manufacturing cost of the driving apparatus by making the pulse size of the pulse the same.

2 is a perspective view showing the structure of a plasma display panel.

2, between the front and rear glass substrate of a plasma display panel (1) (100, 106), the address electrodes (A _1, A _2, ..., A _m), a dielectric layer (102, 110 ), Y electrodes (Y ₁ , ..., Y _n ), X electrodes (X ₁ , ..., X _n ), fluorescent layer 112, partition wall 114 and a protective layer such as magnesium monoxide ( MgO) layer 104 is provided.

The address electrodes A ₁ , A ₂ ,..., A _m are formed in a predetermined pattern on the front side of the rear glass substrate 106. The lower dielectric layer 110 is applied in front of the address electrodes A ₁ , A ₂ ,..., A _m . In front of the lower dielectric layer 110, barrier ribs 114 are formed in a direction parallel to the address electrodes A ₁ , A ₂ ,..., A _m . The partition walls 114 function to partition the discharge area of each display cell and to prevent optical interference between the display cells. The fluorescent layer 112 is formed between the partition walls 114.

The X electrodes X ₁ , ..., X _n and the Y electrodes Y ₁ , ..., Y _n are orthogonal to the address electrodes A ₁ , A ₂ , ..., A _m . The back of the front glass substrate 100 is formed in a predetermined pattern. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) are transparent electrode lines (X _na ) made of a transparent conductive material such as indium tin oxide (ITO). , Y _na ) and metal electrode lines X _nb and Y _nb for increasing conductivity may be formed. The front dielectric layer 102 is formed by applying the entire surface to the back of the X electrodes (X ₁ ,..., X _n ) and the Y electrodes (Y ₁ ,..., Y _n ). A protective layer 104 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying a front surface to the back of the front dielectric layer 102. The plasma forming gas is sealed in the discharge space 108.

A driving scheme generally applied to such a plasma display panel is a method in which initialization, address, and display holding steps are sequentially performed in a unit sub-field. In the initialization step, the charge states of the display cells to be driven are made uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the display holding step, display discharge is performed in the display cells to be selected. At this time, a plasma is formed from the plasma forming gas of the display cells performing display discharge, and the fluorescent layer 112 of the display cells is excited by ultraviolet radiation from the plasma to generate light.

3 illustrates a driving apparatus of the plasma display panel of FIG. 2.

Referring to the drawing, the driving apparatus of the plasma display panel 1 includes an image processor 200, a controller 202, an address driver 206, an X driver 208, and a Y driver 204. The image processing unit 200 converts an external analog image signal into a digital signal, and internal image signals, for example, 8-bit red (R), green (G) and blue (B) image data, clock signals, vertical and horizontal, respectively. Generate synchronization signals. The controller 202 generates the driving control signals SA, SY, and SX according to the internal image signal from the image processor 200. The address driver 206 processes the address signal SA among the drive control signals SA, SY, and SX from the controller 202 to generate a display data signal, and transmits the generated display data signal to the address electrodes. Is authorized. The X driver 208 processes the X driving control signal SX among the driving control signals SA, SY, and SX from the controller 202 and applies the X driving control signal SX to the X electrodes. The Y driver 204 processes the Y driving control signal SY among the driving control signals SA, SY, and SX from the controller 202 and applies the Y driving control signal SY to the Y electrodes.

As a driving method of the plasma display panel 1 having the above-described structure, an address-display separation driving method mainly used is disclosed in US Pat. No. 5,541,618.

FIG. 4 shows a conventional address-display separation driving method for Y electrodes of a plasma display panel.

Referring to the drawings, a unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ..., SF8 is divided into a reset period (not shown), an address period A1, ..., A8, and sustain discharge periods S1, ..., S8. do.

In each address period A1, ..., A8, a display data signal is applied to the address electrodes AR1, AG1, ..., AGm, ABm in FIG. Scanning pulses corresponding to Yn) are sequentially applied.

In each sustain discharge period S1, ..., S8, pulses for display discharge are alternately applied to the Y electrodes Y1, ..., Yn and the X electrodes X1, ..., Xn. In the address periods A1, ..., A8, display discharge is caused in discharge cells in which wall charges are formed.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gray levels, each subfield is sequentially held at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128 in order. The number of pulses can be assigned. In order to obtain luminance of 133 gray levels, cells may be addressed and sustained and discharged during the subfield 1 period, the subfield 3 period, and the subfield 8 period.

The number of sustain discharges allocated to each subfield may be variably determined according to the weights of the subfields according to the APC (Automatic Power Control) step. In addition, the number of sustain discharges allocated to each subfield is. Various modifications are possible in consideration of gamma characteristics or panel characteristics. For example, the gradation level assigned to subfield 4 may be lowered from 8 to 6, and the gradation level assigned to subfield 6 may be increased from 32 to 34. In addition, the number of subfields forming one frame can be variously modified according to design specifications.

FIG. 5 is a signal waveform diagram for applying to a panel according to a driving method of a plasma display panel according to a first embodiment of the present invention. In the ADS driving method of an AC PDP, address electrodes A1 to A1 through subfield SF are shown in FIG. Am), and drive signals applied to the X electrodes X1 to Xn and the Y electrodes Y1 to Yn. As shown in FIG. 5, one subfield SF includes a reset period PR, an address period PA, and a sustain discharge period PS.

In the reset period PR, reset pulses are applied to the scan lines of all groups to force write discharge, thereby initializing the wall charge states of all cells. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. The cells initialized by the reset period PR have similar wall charge conditions inside the cells.

The reset pulse applied to the Y electrodes Y1 to Yn includes a ramp-up pulse t2 to t3 and a rampdown pulse t3 to t4, and the first weak discharge is performed by the ramp-up pulse t2 to t3. After this, a lot of negative charges are accumulated near the Y electrode, and the second weak discharge is generated by the ramp-down pulses t3 to t4, and the negative charge is slightly emitted near the Y electrode.

In the reset period, the ramp-up pulses t2 to t3 that cause the first weak discharge are applied to the Y electrodes Y1 to Yn from a voltage higher than the reference potential by a predetermined voltage V _T1 . In this case, when the ramp-up pulses t2 to t3 start to be applied from a voltage higher than the reference potential by the pulse size Vs of the scan pulse, a circuit for applying the ramp-up pulse in addition to the power supply circuit and the switching circuit used for the scan pulse, The increase in manufacturing costs due to the installation can be reduced. The ramp-down pulses t3 to t4 causing the second weak discharge are applied to the Y electrodes Y1 to Yn from a voltage higher by a predetermined voltage V _T2 than the reference potential. In this case, when the ramp-down pulses t3 to t4 start to be applied from a voltage higher than the reference potential by the pulse size Vs of the scan pulse, the circuit for applying the ramp-down pulse in addition to the power supply circuit and the switching circuit used for the scan pulse are separately provided. The increase in manufacturing costs due to the installation can be reduced.

On the other hand, when the ramp down pulses t3 to t4 are applied, it is preferable that a reset bias voltage Ve1 is applied to the X electrodes X1 to Xn to release positive charges to assist the second weak discharge.

The address period PA is performed after the reset period PR is performed. At this time, in the address period PA, the address bias voltage Ve1 is applied to the X electrodes X1 to Xn, and the scan electrodes Y1 to Yn and the address electrodes A1 to Am are positioned at the cell positions to be displayed. By simultaneously turning on, the display cell is selected.

In the address period PA, while the scan high level V _SC-H is applied to the plurality of Y electrodes, the scan low level V _SC-L lower than the scan high level is applied to each Y electrode. When the pulses are sequentially applied, the address electrodes are turned on at the same time, so that a large amount of negative charge is emitted near the Y electrode and a large amount of positive charge is emitted near the address electrode in the selected display cell, thereby generating a large amount of positive charge near the Y electrode. Piles up and becomes ready for maintenance discharge.

The address bias voltage Ve1 applied to the X electrode firstly increases the potential of the X electrode at the time of address discharge so that discharge with the address electrode does not occur, thereby enhancing counter discharge between the Y electrode and the address electrode. Secondly, when positive charges accumulate near the Y electrode due to address discharge, negative charges accumulate near the X electrode by the address bias voltage Ve1, thereby preparing for a sustain discharge.

After the address period PA is performed, the sustain discharge period PS is performed by alternately applying the sustain pulse Vs to the X electrodes X1 to Xn and the Y electrodes Y1 to Yn. During the sustain discharge period PS, a low level voltage V _G is applied to the address electrodes A1 to Am. In PDP, the brightness is adjusted by the number of sustain discharge pulses. If the number of sustain discharge pulses in one subfield or one TV field is large, the luminance increases. At the time when the first sustain pulse is applied in the sustain discharge period PS of FIG. 5, positive charges accumulated in the address period are accumulated on the Y electrode lines and negative charges are accumulated on the X electrode lines. When the sustain voltage Vs is applied to the Y electrode lines, positive charges are discharged in the Y electrode lines and negative charges are discharged into space charges in the X electrode lines, thereby performing primary sustain discharge. This primary sustain discharge is characterized by the difference between the sum of the positive charge and the Vs voltage accumulated near the Y electrode lines and the negative charge (ie the sum of the absolute values of all potential values) accumulated near the X electrode lines. It is done while exceeding. When the primary sustain discharge occurs, negative charges accumulate near the Y electrode lines and positive charges accumulate near the X electrode lines.

After the first sustain discharge, when the sustain voltage Vs is applied to the X electrode lines, positive charges begin to be discharged into the space charges in the X electrode lines, and negative charges are discharged into the space charges in the Y electrode lines, and the secondary charges are discharged. Sustain discharge is performed. This secondary sustain discharge is obtained by subtracting the potential of the negative charge accumulated near the Y electrode lines from the potential due to the Vs voltage applied to the X electrode and the positive charge accumulated near the X electrodes (that is, the absolute value of all potential values). Is made while exceeding the discharge start voltage. When the primary sustain discharge occurs, positive charges accumulate near the Y electrode lines, just as before the primary sustain discharge, and negative charges accumulate near the X electrode lines. After that, the third sustain discharge occurs by the same action as the first sustain discharge, and then the fourth sustain discharge occurs by the same action as the second sustain discharge. Alternate sustain pulses are maintained for a predetermined time for each subfield, and such sustain discharge is continued.

In order to perform the above-described address period and sustain discharge period, a driving device for applying a scanning pulse having a pulse size (V _SC-H -V _SC-L ) of a voltage difference for performing address discharge to each of the Y electrodes. In addition, a driving device for applying a sustaining pulse having a pulse size Vs of the voltage difference for performing the sustaining discharge is required, and these driving devices have become a major factor in raising the cost of the plasma display device.

Therefore, in the present invention, the pulse size (V _SC-H -V _SC-L ) of the scanning pulse applied to each of the Y electrodes and the pulse size (Vs) of the sustaining pulse are the same, which is required for the power supply circuit and the switching circuit. To reduce the increase in manufacturing costs.

On the other hand, the address discharge is near the scan low-level voltage V _SC-L and the Y electrode of the scanning pulse applied to the Y electrode at the voltage V _A1 of the display data signal and the potential due to the positive charge accumulated near the address electrode. It is caused by the energy minus the potential due to accumulated negative charges (that is, the sum of the absolute values of all potentials). Therefore, when a scanning pulse is applied to the Y electrode in the address period PA, the more negative charge is accumulated near the Y electrode (the dielectric layer covering the Y electrode), the more advantageous for the address discharge. Therefore, as shown in FIG. 5, when the pulse size (V _SC-H -V _SC-L ) of the scan pulse applied to the Y electrode is made larger by the pulse size (Vs) of the sustain pulse, the potential between the Y electrode and the address electrode is further increased. Grows Therefore, the voltage of the display data signal required for causing the address discharge between the Y electrode and the address electrode can be relatively lowered. Therefore, the voltage V _A1 of the display data signal of FIG. 5 can be lower than the voltage V _A of the display data signal of FIG. 1.

At this time, the address discharge should be generated only between the Y electrode and the address electrode, and not between the Y electrode and the X electrode. Therefore, it is preferable to decrease the bias voltage Ve1 for positive polarity (+) applied to the X electrode as the pulse size of the negative (−) scan pulse applied to the Y electrode is increased. In other words, if the address bias voltage Ve1 applied to the X electrode is lowered, the attraction force between the Y electrode and the X electrode does not increase during address discharge, and thus the possibility of false discharge between the Y electrode and the X electrode can be reduced.

6 is a waveform diagram illustrating a driving signal applied to an electrode of a panel according to a method of driving a plasma display panel according to a second embodiment of the present invention.

Referring to FIG. 6, one subfield SF includes a reset period PR, an address period PA, and a sustain discharge period PS. The characteristic of the driving signal shown in FIG. 6 is that a predetermined reference voltage, for example, a ground voltage V _G is applied to the X electrodes X1 to Xn, and is applied to the Y electrode lines in the sustain discharge period PS. The sustain pulses are alternately applied not only with the positive sustain voltage Vs + but also with the pulse size of the negative sustain voltage Vs- (hereinafter, these pulses are referred to as alternating sustain pulses).

The reference voltage or bias voltage applied to the X electrodes is preferably a ground voltage (V _G ) which is an intermediate voltage between the highest voltage value (Vs) and the lowest voltage value (-Vs) of the alternate sustain pulse, but the scope of the present invention. Is not limited thereto. That is, although not shown in FIG. 6, in the address period PA, the positive bias voltage (not the ground voltage V _G ) is applied to the X electrodes for more efficient and stable discharge during the address discharge between the Y electrode and the address electrode. Ve) may be applied.

Referring to the discharge process, the reset period PR initializes the wall charge state of the cell by applying a reset signal to the Y electrode lines and forcibly performing a write discharge. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. The cells initialized by the reset period PR have similar wall charge conditions inside the cells. In the rising lamps t2 to t3 of the Y electrode lines during the reset period PR, the first weak discharge occurs and a large amount of negative charges are accumulated on the Y electrode lines, and positive charges are accumulated on the address electrode and the X electrode lines.

Subsequently, in the falling lamps t3 to t4 of the Y electrode lines, the voltage of the Y electrode lines gradually decreases while the second weak discharge occurs, so that the negative charges of the Y electrode lines are gradually erased and discharged into the discharge space. Due to the weak discharge in the discharge space, the inside of the discharge cell is initialized. When the positive bias voltage is not applied to the X electrode lines during the falling ramp of the Y electrode lines, the voltage of the Y electrode lines is smaller than the conventional one at the time t4 for the initialization discharge in the X electrode lines and the Y electrode lines. The voltage must drop to Vnf. Therefore, a voltage lower than the ground voltage V _G is applied to the Y electrode lines in the address period. However, even if a positive bias voltage Vb is applied to the X electrode lines during the down ramp, it is of course within the scope of the present invention, irrespective of the gist of the present invention.

In the reset period PR, the ramp-up pulses t2 to t3 causing the first weak discharge are applied to the Y electrodes Y1 to Yn from a voltage higher than the reference potential by a predetermined voltage V _T1 . In this case, when the ramp-up pulses t2 to t3 start to be applied from a voltage higher than the reference potential by the pulse size Vs of the scan pulse, a circuit for applying the ramp-up pulse in addition to the power supply circuit and the switching circuit used for the scan pulse, The increase in manufacturing costs due to the installation can be reduced. The ramp-down pulses t3 to t4 causing the second weak discharge are applied to the Y electrodes Y1 to Yn from a voltage higher by a predetermined voltage V _T2 than the reference potential. In this case, when the ramp-down pulses t3 to t4 start to be applied from a voltage higher than the reference potential by the pulse size Vs of the scan pulse, the circuit for applying the ramp-down pulse in addition to the power supply circuit and the switching circuit used for the scan pulse are separately provided. The increase in manufacturing costs due to the installation can be reduced.

In the address period PA, while the scan high level V _SC-H is applied to the plurality of Y electrodes, the scan low level V _SC-L lower than the scan high level is applied to each Y electrode. When the pulses are sequentially applied, the address electrodes are turned on at the same time, so that a large amount of negative charge is emitted near the Y electrode and a large amount of positive charge is emitted near the address electrode in the selected display cell, thereby generating a large amount of positive charge near the Y electrode. Piles up and becomes ready for maintenance discharge.

After the address period PA is performed, alternating sustain pulses in which the positive sustain voltage Vs + and the negative sustain voltage Vs- are alternately applied to the Y electrode lines are performed. The sustain discharge period PS is performed. In one embodiment, Vs + may have a voltage of 160 to 210 Volts.

At the time when the sustain pulse is applied, positive charges accumulated in the address period are accumulated on the Y electrode lines and negative charges are accumulated on the X electrode lines. On the other hand, the positive charge accumulated in the Y electrode lines during the start of the application to the Y electrode lines toward the positive sustain voltage (Vs +) of the alternating sustain pulse consisting of a positive sustain voltage (Vs +) and a negative sustain voltage (Vs-). Is discharged to the space charge, negative charge is also discharged to the space charge in the X electrode lines, and weak discharge is started by the influence of the space charge. When a Vs + voltage (for example, 160 to 210 volts) is applied, more positive charges are discharged in the Y electrode lines and more negative charges are discharged in the space charge in the X electrode lines, and a fast and strong sustain discharge is generated based on the weak discharge. This is done. This primary sustain discharge is the difference between the positive charge accumulated near the Y electrode lines and the Vs + voltage and the negative charge accumulated near the X electrode lines (ie, the sum of the absolute values of all potential values). It is done while exceeding. When the primary sustain discharge occurs, negative charges accumulate near the Y electrode lines and positive charges accumulate near the X electrode lines.

Subsequently, when a negative sustain voltage Vs- starts to be applied to the Y electrode lines, positive charges begin to be discharged into the space charges in the X electrode lines, and negative charges begin to be discharged into the space charges in the Y electrode lines. When the value Vs- is reached, the secondary sustain discharge is performed. This secondary sustain discharge is obtained by subtracting the sum of the negative charge and the Vs-voltage accumulated near the Y electrode lines from the potential due to the positive charge accumulated near the X electrode lines (ie, the sum of the absolute values of all potential values). Is made while exceeding the discharge start voltage. When the primary sustain discharge occurs, positive charges accumulate near the Y electrode lines, just as before the primary sustain discharge, and negative charges accumulate near the X electrode lines. After that, the third sustain discharge occurs by the same action as the first sustain discharge, and then the fourth sustain discharge occurs by the same action as the second sustain discharge. The alternate sustain pulses last for a predetermined time for each subfield, and such sustain discharge is continued.

In order to perform the above-described address period and sustain discharge period, a driving device for applying a scanning pulse having a pulse size (V _SC-H -V _SC-L ) of a voltage difference for performing address discharge to each of the Y electrodes. In addition, a driving device for applying a sustaining pulse having a pulse size Vs of the voltage difference for performing the sustaining discharge is required, and these driving devices have become a major factor in raising the cost of the plasma display device.

Therefore, in the present invention, the pulse sizes (V _{SC -H} -V _SC-L ) of the scanning pulses applied to the respective Y electrodes and the pulse sizes (| + Vs |, | -Vs |) of the sustaining pulses are the same. It is possible to reduce the manufacturing cost increase in the power supply circuit and the switching circuit.

On the other hand, the address discharge is near the scan low-level voltage V _SC-L and the Y electrode of the scanning pulse applied to the Y electrode at the voltage V _A1 of the display data signal and the potential due to the positive charge accumulated near the address electrode. It is caused by the energy minus the potential due to accumulated negative charges (that is, the sum of the absolute values of all potentials). Therefore, when a scanning pulse is applied to the Y electrode in the address period PA, the more negative charge is accumulated near the Y electrode (the dielectric layer covering the Y electrode), the more advantageous for the address discharge. Therefore, as shown in FIG. 6, when the pulse size (V _SC-H -V _SC-L ) of the scanning pulse applied to the Y electrode is increased by the pulse size (Vs) of the sustain pulse, the potential between the Y electrode and the address electrode is further increased. Grows Therefore, the voltage of the display data signal required for causing the address discharge between the Y electrode and the address electrode can be relatively lowered. Therefore, the voltage V _A1 of the display data signal of FIG. 6 can be lower than the voltage V _A of the display data signal of FIG. 1.

Meanwhile, the display panel driving method according to the present invention described above may be embodied as computer readable codes on a computer readable recording medium. Computer-readable recording media include any type of recording device that stores programs or data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage, and the like. Here, the program stored in the recording medium refers to a series of instruction instructions used directly or indirectly in an apparatus having an information processing capability such as a computer to obtain a specific result. Thus, the term computer is used to mean all devices having an information processing capability for performing a specific function by a program, including a memory, an input / output device, and an arithmetic device, regardless of the name actually used. Even in the case of a device for driving a panel, its use is limited to a specific field of panel driving, and in reality, it is a kind of computer.

In particular, the display panel driving method according to the present invention is an integrated circuit, for example, a field programmable gate array (FPGA), which is prepared by a schematic or ultra high-speed integrated circuit hardware description language (VHDL) on a computer, and connected to a computer. It can be implemented by. The recording medium includes such a programmable integrated circuit.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the plasma display panel driving method of the present invention has the following effects.

First, since the pulse size (voltage difference) of the scan pulse applied to the Y electrodes of the discharge cell selected in the address period and the pulse size (voltage difference) of the sustain pulse applied to the Y electrodes in the sustain discharge period are the same, The cost of the power supply circuit and the switching circuit, which is the biggest cost increase factor in the panel driving device, can be reduced.

Second, as the size of the scan pulse is increased by the size of the sustain pulse, the voltage of the display data signal for generating the address discharge can be reduced. Therefore, the manufacturing cost of an address driver and generation of electromagnetic noise can be reduced.

Third, the voltage difference between the start voltage of the ramp-up pulse applied to the Y electrodes in the reset period and the reference voltage is the same as the pulse size (voltage difference) of the sustain pulse applied to the Y electrodes in the sustain discharge period, and also in the reset period. Since the voltage difference between the start voltage and the reference voltage of the ramp-down pulse applied to the Y electrodes is the same as the pulse size (voltage difference) of the sustain pulse applied to the Y electrodes in the sustain discharge period, The cost of the power supply circuit and the switching circuit, which are a significant cost increase factor, can be reduced.

The invention is not limited to the examples described above and represented in the drawings. Those skilled in the art taught by the above-described embodiments, many modifications to the above-described embodiments are possible by substitution, erasure, merging, etc. within the scope and object of the present invention described in the following claims.

1 is a signal waveform diagram illustrating an example of a driving signal applied to a conventional plasma display panel.

2 is a diagram illustrating a structure of a plasma display panel.

3 is a block diagram showing a conventional driving device of the plasma display panel.

4 illustrates a conventional address-display separation driving method for the plasma display panel of FIG. 2.

5 is a signal waveform diagram illustrating a method of driving a plasma display panel according to a first embodiment of the present invention.

6 is a signal waveform diagram illustrating a method of driving a plasma display panel according to a second embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

Lowest potential of the rampdown pulse during the reset period applied to the Vnf ... Y electrode

High level voltage of the address period applied to the V _SC-H .... Y electrode

V _SC-L Low level voltage of address period applied to Y electrode

V _A , V _A1 ... voltage of the display data signal applied to the address electrode

Vs ... voltage of sustain pulse applied to Y electrode and / or X electrode

V _G ... ground voltage

PR ... Reset period

PA ... address period

PS ... oil fat war

Claims (5)

A method of driving a plasma display panel by a drive waveform consisting of a reset period, an address period, and a sustain discharge period, In the address period, a scan high level voltage is applied to the plurality of first electrodes, and a scan pulse having a scan low level lower than the scan high level is sequentially applied to each of the first electrodes, and the address electrode A display data signal for a first electrode to which the scan pulse is applied, a bias voltage for an address is applied to the second electrodes, And a sustain pulse having the same pulse size as the scan pulse is alternately applied to the plurality of first electrodes and the plurality of second electrodes in the sustain discharge period. The method of claim 1, In the reset period, A first initialization discharge by starting to apply a ramp-up pulse from a voltage higher than the reference potential to the first electrodes by the pulse size of the scanning pulse, And a second initialization discharge by which a ramp-down pulse is applied from a voltage higher than the reference potential by the magnitude of the scanning pulse. A method of driving a plasma display panel by a drive waveform consisting of a reset period, an address period, and a sustain discharge period, In the address period, a scan high level voltage is applied to the plurality of first electrodes, and a scan pulse having a scan low level lower than the scan high level is sequentially applied to each of the first electrodes, and the address electrode Display data signals for the first electrodes to which the scan pulses are applied In the sustain discharge period, a positive sustain pulse and a negative sustain pulse having the same pulse size as the scan pulse are alternately applied to the plurality of first electrodes, A method of driving a plasma display panel, characterized in that a fixed voltage is applied to the second electrodes. The method of claim 3, In the reset period, A first initialization discharge by starting to apply a ramp-up pulse from a voltage higher than the reference potential to the first electrodes by the pulse size of the scanning pulse, And a second initialization discharge by which a ramp-down pulse is applied from a voltage higher than the reference potential by the magnitude of the scanning pulse. A recording medium having recorded thereon a program for executing the method of any one of claims 1 to 4 on a computer.