KR20060001639A - Driving method of plasma display panel - Google Patents

Abstract

The present invention relates to a plasma display panel in which first and second storage electrode lines are formed in parallel with each other and address electrode lines are crossed with respect to the first and second storage electrode lines. A method of driving a plasma display panel, which is divided into a plurality of subfields, wherein a reset period, an address period, and a sustain discharge period are performed in each of the subfields. A reset signal is applied, a scan signal is applied to the first sustain electrode lines in the address period, and an address signal is applied to the address electrode lines, and alternately holds the first sustain electrode lines in the sustain discharge period. A pulse is applied, and the bias voltage is applied to the second sustain electrode lines. The present invention provides a method of driving a plasma display panel in which an address signal is applied to all of the first storage electrode lines, and then a pulse is applied to the address electrode lines to prevent charge accumulation.

Description

Driving method of plasma display panel {Driving method of plasma display panel}

1 is a waveform diagram illustrating a conventional plasma display panel driving signal.

2 is a perspective view of a plasma display panel.

3 is a block diagram illustrating a plasma display panel driver.

FIG. 4 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of a plasma display panel.

5 is a waveform diagram illustrating a plasma display panel driving signal according to a first exemplary embodiment of the present invention.

6 is a waveform diagram illustrating a plasma display panel driving signal according to a second embodiment of the present invention.

7 is a waveform diagram illustrating a plasma display panel driving signal according to a third exemplary embodiment of the present invention.

8 is a waveform diagram illustrating a plasma display panel driving signal according to a fourth exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>                 

V _sch .... high level voltage in the address period

V _scl .... Low-Level Voltage in Address Period

Va ... address data voltage

Var ... address reset voltage

Vas ... charge prevention voltage

Vs + ... positive holding voltage (maximum voltage value)

Vs -... Negative sustain voltage (lowest voltage value)

Vb, Vb '... Bias voltage

V _G ... ground voltage

PR ... Reset period

PA ... address period

PS ... oil fat war

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel. In particular, when a constant bias voltage is applied to an X electrode and an alternating sustain pulse is applied to a Y electrode to generate a sustain discharge, the discharge is applied by applying a positive pulse so that a positive charge is not accumulated on the address electrode. The present invention relates to a plasma display panel driving method capable of improving reliability.

In a typical plasma display panel, Y storage electrode lines and X storage electrode lines are formed to be parallel to each other between the front substrate and the rear substrate spaced apart from each other, and the address electrode lines are formed to cross the Y and X storage electrode lines. do. For the Y and X sustain electrode lines and the address electrode lines, the unit frame is divided into a plurality of subfields for time division gray scale display, and the resetting, addressing, and display-holding steps in each of the subfields are performed. The drive signal waveform is applied so that they are performed.

FIG. 1 shows driving signals applied to electrode lines of a plasma display panel in each unit subfield according to a waveform diagram showing a plasma display panel driving signal. The conventional resetting method included in the driving method of Fig. 1 is taught in Japanese Laid-Open Patent Publications 214,823 and 242,224.

Referring to FIG. 1, in the rising period of the resetting time PR of the unit subfield SF, the potential rises to the second potential V _S ′ in the Y electrode lines and then the second potential V _S ′. The voltage is continuously raised to the first potential V _S '+ V _SET ' which is higher than the fifth potential V _SET ′. Here, the ground potential V _G is applied to the X electrode lines and the address electrode lines. Thus, a weak discharge occurs between the Y electrode lines and the X electrode lines, while a weaker discharge occurs between the Y electrode lines and the address electrode lines. Accordingly, a large number of negative wall charges are formed around the Y electrode lines, positive wall charges are formed around the X electrode lines, and less positive wall charges are formed around the address electrode lines.

In the falling period of the reset time PR, while the potential applied to the X electrode lines is maintained at the bias potential V _b ′, the potential applied to the Y electrode lines is the second potential V _S ′. To the third potential V _nf ′ continuously. Here, the ground potential V _G is applied to the address electrode lines. Thus, due to the weak discharge between the X electrode lines and the Y electrode lines, some of the negative wall charges around the Y electrode lines move around the X electrode lines. Accordingly, the wall electric-potential of the X electrode lines X ₁ ,..., X _n is lower than the wall potential of the address electrode lines and higher than the wall potential of the Y electrode lines.

Accordingly, the addressing voltage V _a '-V _scl ' required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered in the subsequent addressing period PA. On the other hand, since the ground potential V _G is applied to all the address electrode lines, the address electrode lines discharge the X electrode lines and the Y electrode lines, and as a result, the positive electrode around the address electrode lines is discharged. Wall charges disappear.

In a subsequent addressing period PA, a display data signal is applied to the address electrode lines while a predetermined bias voltage V _b ′ is applied to the X electrode lines, and is lower than the second potential V _S. As the scan pulses of the low level potential V _scl are sequentially applied to the Y electrode lines biased at 6 potentials V _sch , smooth addressing may be performed. Display data signals applied to the address electrode lines are applied with the ground potential (V _G) in the case where the positive addressing voltage (V _a ') if the selected display cell, otherwise. Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the low level potential V _scl is applied, wall charges are formed by the addressing discharge in the corresponding display cell. In wall charges are not formed.

In the subsequent sustain discharge period PS, the sustain pulses of the second potential V _S 'are alternately applied to all the Y electrode lines and the X electrode lines, so that the wall charges are formed at the corresponding addressing time PA. It causes a discharge for display-maintenance in the cells.

However, in the waveform diagram according to the conventional driving method as described above, sustain pulses of the second potential V _S ′ are alternately applied to the X electrode lines in the sustain discharge period PS, similarly to the Y electrode lines. In addition, an expensive driving circuit must be used for the X driver as well as the address driver and the Y driver. Therefore, according to the conventional driving method, there is a large cost required for driving the plasma display panel.

 The present invention is to solve the above problems, an object of the present invention is to provide a plasma display panel driving method that can reduce the manufacturing cost of the plasma display device by reducing the price of the driving circuit required for driving the plasma display panel. have.

Another object of the present invention is to provide a plasma display panel driving method capable of improving reliability of sustain discharge by eliminating positive charges that may accumulate in the address electrode lines in the sustain discharge period.

In order to achieve the above object, the present invention,

For a plasma display panel in which first and second storage electrode lines are formed in parallel with each other and address electrode lines are intersected with respect to the first and second storage electrode lines, a plurality of sub units for time division gray scale display are provided. A method of driving a plasma display panel divided into fields, wherein a reset period, an address period, and a sustain discharge period are performed in each of the subfields,

A reset signal is applied to the first sustain electrode lines in the reset period, a scan signal is applied to the first sustain electrode lines and an address signal is applied to the address electrode lines in the address period, and the sustain discharge is applied. In the period, an alternate sustain pulse is applied to the first sustain electrode lines,

A bias voltage is applied to the second sustain electrode lines.

After the address signal is applied to all of the first sustain electrode lines, a driving method of the plasma display panel is applied to apply a pulse to prevent charge accumulation on the address electrode lines.

According to the present invention, since only a bias voltage is applied to the second sustain electrode lines and no alternating sustain pulses are applied, an expensive driving circuit for driving the second sustain electrode lines is not required. Can be reduced. In addition, by removing the charge accumulated in the address electrode lines in the sustain discharge period, it is possible to improve the reliability of the sustain discharge between the first sustain electrode lines and the second sustain electrode lines.

According to another feature of the invention, the pulse for preventing the charge accumulation may have a high level potential higher than the ground potential.

According to another feature of the present invention, the high level potential of the pulse for preventing the charge accumulation may have a size of 1/4 to 3/4 of the maximum voltage value of the alternate sustain pulse applied to the first sustain electrode lines. have. The pulse for preventing the charge accumulation may be applied from the completion of the address signal until the completion of the first period of the alternate sustain pulse.

The bias voltage applied to the second sustain electrode lines is preferably an intermediate voltage between the highest voltage and the lowest voltage of the alternate sustain pulse, and the intermediate voltage is more preferably a ground voltage.

On the other hand, the bias voltage applied to the second sustain electrode lines,

In the reset period and the sustain discharge period, a first bias voltage having a ground potential may be applied, and in the address period, a second bias voltage of both potentials may be applied.

On the other hand, the driving method can be recorded as a program for executing in a computer. That is, the driving method can be driven by a computer after being recorded on a recording medium as a program so that the plasma display panel can be driven.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

2 is a perspective view showing the structure of a plasma display panel.

Referring to FIG. 2, between the front and rear glass substrates 100 and 106 of the conventional surface discharge plasma display panel 1, the address electrode lines A ₁ , A ₂ ,..., A _m , Dielectric layers 102 and 110, Y electrode lines Y ₁ , ..., Y _n , X electrode lines X ₁ , ..., X _n , fluorescent layer 112, barrier rib 114, and As a protective layer, the magnesium monoxide (MgO) layer 104 is provided, for example.

The address electrode lines A ₁ , A ₂ ,..., A _m are formed in a predetermined pattern on the front side of the rear glass substrate 106. The lower dielectric layer 110 is applied in front of the address electrode lines A ₁ , A ₂ ,..., A _m . In front of the lower dielectric layer 110, barrier ribs 114 are formed in a direction parallel to the address electrode lines A ₁ , A ₂ ,..., A _m . These partitions 114 partition the discharge area of each display cell and serve to prevent optical interference between each display cell. The fluorescent layer 112 is formed between the partition walls 114.

The X electrode lines X ₁ , ..., X _n and the Y electrode lines Y ₁ , ..., Y _n are address electrode lines A ₁ , A ₂ , ..., A _m . It is formed in a predetermined pattern on the back of the front glass substrate 100 to be orthogonal to the. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) are transparent electrode lines (X _na ) made of a transparent conductive material such as indium tin oxide (ITO). , Y _na ) and metal electrode lines X _nb and Y _nb for increasing conductivity may be formed. The front dielectric layer 102 is formed by applying the entire surface to the rear of the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ ,..., Y _n ). A protective layer 104 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying a front surface to the back of the front dielectric layer 102. The plasma forming gas is sealed in the discharge space 108.

A driving scheme generally applied to such a plasma display panel is a method in which initialization, address, and display holding steps are sequentially performed in a unit sub-field. In the initialization step, the charge states of the display cells to be driven are made uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the display holding step, display discharge is performed in the display cells to be selected. At this time, a plasma is formed from the plasma forming gas of the display cells performing display discharge, and the fluorescent layer 112 of the display cells is excited by ultraviolet radiation from the plasma to generate light.

3 is a block diagram illustrating a general driving device of the plasma display panel.

Referring to the drawings, a typical driving device of the plasma display panel 1 includes an image processor 200, a controller 202, an address driver 206, an X driver 208, and a Y driver 204.

The image processing unit 200 converts an external analog image signal into a digital signal, and internal image signals, for example, 8-bit red (R), green (G) and blue (B) image data, clock signals, vertical and horizontal, respectively. Generate synchronization signals.

The logic controller 202 generates the driving control signals SA, SY, and SX according to the internal image signal from the image processor 200. The address driver 206 processes the address signal SA among the drive control signals SA, SY, and SX from the controller 202 to generate a display data signal, and generates the display data signal through the address electrode lines. To apply. The X driver 208 processes the X driving control signal SX among the driving control signals SA, SY, and SX from the controller 202 and applies the X driving control signal SX to the X electrode lines. The Y driver 204 processes the Y driving control signal SY among the driving control signals SA, SY, and SX from the controller 202 and applies the Y driving control signal SY to the Y electrode lines.

As a driving method of the plasma display panel 1 having the above-described structure, an address-display separation driving method mainly used is disclosed in US Patent No. 5,541,618.

4 shows a conventional address-display separation driving method for Y electrode lines of a plasma display panel.

Referring to the drawings, a unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ..., SF8 is divided into a reset period (not shown), an address period A1, ..., A8, and sustain discharge periods S1, ..., S8. do.

In each address period A1, ..., A8, a display data signal is applied to the address electrode lines AR1, AG1, ..., AGm, ABm in FIG. Scan pulses corresponding to..., Yn) are sequentially applied.

In each sustain discharge period (S1, ..., S8), pulses for display discharge alternately in the Y electrode lines (Y1, ..., Yn) and the X electrode lines (X1, ..., Xn). Is applied to cause display discharge in discharge cells in which wall charges are formed in the address periods A1, ..., A8.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gray levels, each subfield is sequentially held at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128 in order. The number of pulses can be assigned. In order to obtain luminance of 133 gray levels, cells may be addressed and sustained and discharged during the subfield 1 period, the subfield 3 period, and the subfield 8 period.

The number of sustain discharges allocated to each subfield may be variably determined according to the weights of the subfields according to the automatic power control (APC) step. In addition, the number of sustain discharges allocated to each subfield is. Various modifications are possible in consideration of gamma characteristics or panel characteristics. For example, the gradation level assigned to subfield 4 may be lowered from 8 to 6, and the gradation level assigned to subfield 6 may be increased from 32 to 34. In addition, the number of subfields forming one frame can be variously modified according to design specifications.

The basic concept of the plasma display panel driving method according to the present invention is to apply a predetermined bias voltage to the X electrode lines without applying a high frequency pulse, thereby reducing the cost of the driving circuit and at the same time the address electrode line in the sustain discharge period. By applying a pulse of a predetermined positive potential to the field to remove the positive charge that can accumulate in the address electrode to improve the reliability of the address discharge between the Y electrode and the X electrode.

FIG. 5 is a waveform diagram illustrating a plasma display panel driving signal according to a first embodiment of the present invention, wherein the address electrode lines in one subfield SF in an ADS (Address Display Separation) driving scheme of an AC plasma display are shown in FIG. , Driving signals applied to the X electrode lines and the Y electrode lines. Referring to FIG. 5, one subfield SF includes a reset period PR, an address period PA, and a sustain discharge period PS. The characteristic of the driving signal shown in FIG. 5 is that a predetermined bias voltage V _b is applied to the X electrode lines in the address period PA, and the X electrode line in the reset period PR and the sustain discharge period PS. The ground voltage (V _G ) is applied to the field continuously.

Further, optionally, the driving signal applied to the Y electrode lines may not have a section in which the ground potential is maintained. If the ground potential is not applied to the pulses applied to the Y electrode lines, the ground switch circuit is not required, thereby further reducing the manufacturing cost.

In the driving signal of FIG. 5, the sustain pulses applied to the Y electrode lines in the sustain discharge period PS are alternately applied not only with the positive sustain voltage Vs + but also with the pulse size of the negative sustain voltage Vs−. (Hereinafter, this pulse is referred to as an alternating sustain pulse.)

The bias voltage applied to the X electrode lines is preferably an intermediate voltage between the highest voltage value and the lowest voltage value of the alternate sustain pulse in the reset period PR and the sustain discharge period PS. Alternately a sustain pulse is maintained because of the voltage of Vs + and Vs-, the bias voltage applied to the X electrode lines is preferably the ground voltage (V _G) of an intermediate voltage Vs + and Vs-. In the address period PA, the second bias voltage V _b at both potentials is applied. The second bias voltage V _b is applied for more efficient and stable discharge upon address discharge between the Y electrode and the address electrode.

Referring to the discharge process, the reset period PR initializes the wall charge state of the cell by applying a reset signal to the Y electrode lines and forcibly performing a write discharge. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement. In the cells initialized by the reset period PR, all of the wall charge conditions inside the cell are similarly formed. In the rising ramp of the Y electrode lines in the reset period PR, a large amount of negative charges are accumulated on the Y electrode lines, and positive charges are accumulated on the address electrode and the X electrode lines.

Subsequently, in the falling lamps of the Y electrode lines, the voltage of the Y electrode lines gradually decreases, so that the negative charges of the Y electrode lines are gradually erased and discharged into the discharge space to generate the space charge. The discharge cell is initialized due to the discharge in the discharge space. When the positive bias voltage Vb 'is not applied to the X electrode lines during the falling ramp of the Y electrode lines, the voltage of the Y electrode lines is higher than that of the prior art for the initialization discharge in the X electrode lines and the Y electrode lines. It must drop to a small Vnf voltage. Therefore, a voltage lower than the ground voltage V _G is applied to the Y electrode lines in the address period. However, even if a positive bias voltage Vb 'is applied to the X electrode lines during the down ramp, it is, of course, within the scope of the present invention, irrespective of the gist of the present invention.

The address period PA is performed after the reset period PR is performed. At this time, in the address period PA, the scan voltage Vscl is applied to the Y electrode lines at the cell positions to be displayed, and the address voltage Va is applied to the address electrode to be turned on at the same time to select the display cell. Display data signals applied to the address electrode lines are applied with the ground potential (V _G) in the case where the positive addressing voltage (V _a ') if the selected display cell, otherwise. Accordingly, the low level electric potential (V _scl) scan pulse is applied to the positive addressing voltage (V _a) the display data signal is applied when the corresponding by the address discharge in the display cell wall of the charge during which are formed of, the right display that Wall charges are not formed in the cell.

After the address period PA is performed, while the ground voltage V _G is applied as the bias voltage to the X electrode lines, the positive sustain voltage Vs + and the negative sustain voltage Vs− are applied to the Y electrode lines. By alternating sustain pulses The sustain discharge period PS is performed. In one embodiment, Vs + may have a voltage of 160 to 210 Volts.

At the time when the sustain pulse is applied, positive charges accumulated in the address period are accumulated on the Y electrode lines and negative charges are accumulated on the X electrode lines. On the other hand, the positive charge accumulated in the Y electrode lines during the start of the application to the Y electrode lines toward the positive sustain voltage (Vs +) of the alternating sustain pulse consisting of a positive sustain voltage (Vs +) and a negative sustain voltage (Vs-). Is discharged to the space charge, negative charge is also discharged to the space charge in the X electrode lines, and weak discharge is started by the influence of the space charge. When a Vs + voltage (for example, 160 to 210 volts) is applied, more positive charges are discharged in the Y electrode lines and more negative charges are discharged in the space charge in the X electrode lines, and a fast and strong sustain discharge is generated based on the weak discharge. This is done. This primary sustain discharge is the difference between the positive charge accumulated near the Y electrode lines and the Vs + voltage and the negative charge accumulated near the X electrode lines (ie, the sum of the absolute values of all potential values). It is done while exceeding. When the primary sustain discharge occurs, negative charges accumulate near the Y electrode lines and positive charges accumulate near the X electrode lines.

Subsequently, when a negative sustain voltage Vs- starts to be applied to the Y electrode lines, positive charges begin to be discharged into the space charges in the X electrode lines, and negative charges begin to be discharged into the space charges in the Y electrode lines. When the value Vs- is reached, the secondary sustain discharge is performed. This secondary sustain discharge is obtained by subtracting the sum of the negative charge and the Vs-voltage accumulated near the Y electrode lines from the potential due to the positive charge accumulated near the X electrode lines (ie, the sum of the absolute values of all potential values). Is made while exceeding the discharge start voltage. When the primary sustain discharge occurs, positive charges accumulate near the Y electrode lines, just as before the primary sustain discharge, and negative charges accumulate near the X electrode lines. After that, the third sustain discharge occurs by the same action as the first sustain discharge, and then the fourth sustain discharge occurs by the same action as the second sustain discharge. The alternate sustain pulses last for a predetermined time for each subfield, and such sustain discharge is continued.

However, when the sustain discharge occurs, a part of the positive charges discharged from the Y electrode converge toward the address electrode having a relatively low voltage and accumulate near the address electrode (i.e., the dielectric on the address electrode). Due to the positive charge accumulated on the address electrode, a potential difference occurs between the Y electrode and the address electrode, and a potential difference occurs between the X electrode and the address electrode, which increases the possibility of erroneous discharge during the sustain discharge between the Y electrode and the X electrode. In the case of the signal waveform of FIG. 5, the charges accumulated in the address electrode lines are positive charges, but negative charges may be accumulated in the address electrode lines instead of the positive charges depending on the waveform of the sustain pulse.

Therefore, in the plasma display panel driving method according to the present invention, after the address signal is applied to all the Y electrode lines, a pulse for preventing charge accumulation is applied to the address electrode lines, thereby improving the reliability of the sustain discharge. . The pulse to prevent charge accumulation of positive charges has a high level potential (+ | Vas |) higher than the ground potential. In contrast, the pulse for preventing charge accumulation of negative charge may have a low level potential (-| Vas |) lower than the ground potential. In the following, Vas is referred to as charge accumulation preventing voltage.

The magnitude of the high level potential (+ | Vas |) of the pulse to prevent charge accumulation, that is, the magnitude of the charge accumulation prevention voltage Vas, should preferably have a minimum size within a range capable of achieving the object of the present invention. Do. The charge accumulation prevention voltage Va suitable to generate reliable sustain discharge preferably has a size of 1/4 to 3/4 of the maximum voltage value Vs + of the alternate sustain pulses applied to the Y electrode lines.

The pulse for preventing charge accumulation need not be applied for the entire period of the sustain discharge period PS. The most positive charge builds up on the address electrode when the first sustain pulse is applied. Therefore, the pulse for preventing the charge accumulation is preferably applied from the completion of the address signal to the completion of the first period of the alternate sustain pulse. FIG. 6 is a waveform diagram illustrating a plasma display panel driving signal according to a second exemplary embodiment of the present invention, in which charge accumulation prevention pulses applied to an address electrode line are applied until completion of the first period PS1 among alternating sustain pulses. Indicates.

Since the charge accumulation prevention pulse applied to the address electrode line should be applied after the completion of the address signal, the charge accumulation prevention pulse may start to be applied immediately after the completion of the address signal, but may be applied from the start of the sustain discharge period PS. . In the waveform diagram of FIG. 6, the charge accumulation prevention pulse is applied from the start point of the sustain discharge period PS.

7 is a waveform diagram illustrating a plasma display panel driving signal according to a third exemplary embodiment of the present invention.

When the driving signal of FIG. 7 is compared with the driving signal of FIG. 5, in the driving signal of FIG. 5, a predetermined bias voltage V _b is applied to the X electrode lines in the address period PA, and the reset period PR and the sustain signal are applied. in the discharge period (PS) on the other hand, a ground voltage (V _G) is continuously applied, in the drive signal of Figure 7 differs from point to which the a ground voltage (V _G) biased at all time periods (PA, PR, PS) . The plasma display apparatus driven by the waveform diagram of FIG. 7 does not require any driving circuit and / or switching circuit for driving the X electrode lines, thereby further reducing the manufacturing cost of the plasma display apparatus.

In the driving signal of FIG. 7, the ground voltage V _G is applied to the X electrode lines during the address period PA, unlike the waveform of FIG. 5, so that the Y electrode lines are maintained in order to maintain the potential difference from the Y electrode lines. The low level (V _scl ) and high level (V _sch ) voltages of the scan pulse signal applied are much lower than those in the drive signal of FIG. 5. Unlike the driving signal of FIG. 5, since the positive voltage V _b ′ is not applied to the X electrode lines in the driving signal of FIG. 7, to perform an initialization discharge while maintaining the potential difference between the X electrode lines and the Y electrode lines, a reset is performed. This is because the voltage at the end of the period PR should be much lower than before.

8 is a waveform diagram illustrating a plasma display panel driving signal according to a fourth exemplary embodiment of the present invention. When the driving signal of FIG. 8 is compared with the driving signal of FIG. 5, the driving signal of FIG. 8 rises from the ramp-up period of the address period PR (from zero potential to Vs + potential and Vset potential in the Y electrode lines of FIG. 8). Period), a pulse having a high level potential Var higher than the ground potential is applied to the address electrode lines. As shown in FIG. 8, when a predetermined positive potential pulse is applied to the address electrode lines, a negative charge is easily accumulated at the Y electrode, thereby reducing the magnitude of the Vset potential, thereby reducing power consumption and noise generation. Has the effect of.

On the other hand, the display panel driving method according to the present invention described above can be implemented as a computer-readable code on a computer-readable recording medium. Computer-readable recording media include any type of recording device that stores programs or data that can be read by a computer system. Examples of computer-readable recording media include ROM, RAM, CD-ROM, magnetic tape, hard disk, floppy disk, flash memory, optical data storage, and the like.

Here, the program stored in the recording medium refers to a series of instruction instructions used directly or indirectly in an apparatus having an information processing capability such as a computer to obtain a specific result. Thus, the term computer is used to mean all devices having an information processing capability for performing a specific function by a program, including a memory, an input / output device, and an arithmetic device, regardless of the name actually used. Even in the case of a device for driving a panel, its use is limited to a specific field of panel driving, and in reality, it is a kind of computer.

In particular, the method for driving a display panel according to the present invention is an integrated circuit, for example, a field programmable gate array (FPGA), which is written on a computer by a schematic or ultra high-speed integrated circuit hardware description language (VHDL) or the like and connected to a computer. It can be implemented by. The recording medium includes such a programmable integrated circuit.

The best embodiments have been disclosed in the drawings and specification above. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the present invention as described above, the following effects can be obtained.

First, since only a bias voltage is applied to the X electrode lines and no alternate sustain pulse is applied, an expensive driving circuit for driving the X electrode lines is not required, thereby reducing the manufacturing cost of the plasma display apparatus. In addition, if the ground potential is not applied to the pulses applied to the Y electrode lines, the ground switch circuit is not required, thereby further reducing the manufacturing cost.

Second, there is provided a plasma display panel driving method capable of high-reliability sustain discharge without disturbing sustain discharge between the Y electrode and the X electrode by eliminating charges that may accumulate in the address electrode lines at the start of the address discharge period. .

Third, since the utilization rate of the space charge is large in the sustain discharge period, it is possible to drive at a low voltage in the address period, and the utilization of the space charge in the sustain discharge period is large.

As noted above, the best embodiments have been disclosed in the drawings and specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (8)

For a plasma display panel in which first and second storage electrode lines are formed in parallel with each other and address electrode lines are intersected with respect to the first and second storage electrode lines, a plurality of sub units for time division gray scale display are provided. A method of driving a plasma display panel divided into fields, wherein a reset period, an address period, and a sustain discharge period are performed in each of the subfields, A reset signal is applied to the first sustain electrode lines in the reset period, a scan signal is applied to the first sustain electrode lines and an address signal is applied to the address electrode lines in the address period, and the sustain discharge is applied. In the period, an alternate sustain pulse is applied to the first sustain electrode lines, A bias voltage is applied to the second sustain electrode lines. And applying a pulse to prevent charge accumulation on the address electrode lines after an address signal is applied to all of the first sustain electrode lines. The method of claim 1, And a pulse for preventing charge accumulation has a high level potential higher than a ground potential. The method of claim 2, The high level potential of the pulse for preventing the charge accumulation has a size of 1/4 to 3/4 of the maximum voltage value of the alternate sustain pulse applied to the first sustain electrode lines. . The method of claim 1, And a pulse for preventing the charge accumulation is applied from the completion of the address signal until the completion of the first period of the alternate sustaining pulses. The method of claim 1, And a bias voltage applied to the second sustain electrode lines is an intermediate voltage between the highest voltage value and the lowest voltage value of the alternate sustain pulse. The method of claim 5, And the intermediate voltage is a ground voltage. The method of claim 1, The bias voltage applied to the second sustain electrode lines is And a first bias voltage having a ground potential in the reset period and the sustain discharge period, and a second bias voltage of both potentials in the address period. A recording medium on which a program for executing the method of any one of claims 1 to 7 is recorded on a computer.

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