KR100563072B1 - Driving method and driving apparatus of plasma display panel - Google Patents

Abstract

The present invention aims to reduce the manufacturing cost by reducing the type of power source used in the driving method and driving apparatus for driving the plasma display panel.

In order to achieve the above object, the present invention provides a plasma display panel including address electrode lines and scan electrode lines and sustain electrode lines that intersect the address electrode lines. A driving method and a driving apparatus of a plasma display panel divided into a plurality of subfields, in which reset, address, and sustain discharge steps are performed in each of the subfields, in the reset step, at a first voltage to the scan electrode lines. Reaching a third voltage having a rising slope and increasing by a second voltage, reaching a fourth voltage with a falling slope at a third voltage, and in the addressing step, a fifth voltage is applied to the scan electrode lines, sequentially A scan pulse having a sixth voltage is applied, and the seventh voltage is applied to the address electrode lines according to the scan pulse. And applying a display data signal having, is applied to an eighth voltage to the sustain electrode line, in the sustain discharge period, sustain pulses having a first voltage to the scan electrode lines and sustain electrode lines are alternately applied to each other,

The fifth voltage is half the magnitude of the first voltage, and the driving method and the driving apparatus of the plasma display panel are provided.

Description

Driving method and driving apparatus for plasma display panel {Driving method and driving apparatus of plasma display panel}

1 is a view schematically showing an electrode arrangement of a plasma display panel.

FIG. 2 is a timing diagram illustrating an example of a conventional driving signal applied to each electrode of the plasma display panel in FIG. 1.

3 is a block diagram schematically illustrating a driving apparatus of a plasma display panel for realizing a method of driving a plasma display panel of the present invention.

4 is a timing diagram showing a driving signal as a driving method of the plasma display panel of the present invention.

5 is a circuit diagram showing a driving device of the plasma display panel of the present invention.

Explanation of symbols on the main parts of the drawings

Ce ... discharge cell, PR ... reset period,

PA ... address period, PS ... oil fat period,

1 ... plasma display panel, 300 image processing unit,

302 ... logic control section, 304 ... Y drive section,

306 ... address drive, 308 ... X drives,

Vs ... first voltage or sustain discharge voltage,

Vset ... second voltage or rising voltage,

Vset + Vs ... 3rd voltage or peak rising voltage,

Vnf ... fourth voltage or lowest falling voltage,

Vsch ... scan high voltage,

0.5Vs ... fifth voltage or the scan high voltage of FIGS. 4 and 5,

Vscl ... sixth voltage or scan low voltage,

Va ... seventh voltage or address voltage,

Vb ... the eighth voltage or the bias voltage,

Y-ERC ... Y energy recovery circuit, X-ERC ... X energy recovery circuit,

702 ... Y energy recovery drive, 712 ... X energy recovery drive.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method and a driving apparatus of a plasma display panel for reducing a manufacturing cost by reducing the type of power applied.

1 is a view schematically showing an electrode arrangement of a plasma display panel.

Referring to FIG. 1, an electrode structure of a plasma display panel includes scan electrode lines and sustain electrode lines disposed in parallel to a horizontal direction of the panel, and perpendicularly cross the scan electrode lines and sustain electrode lines. There are address electrode lines arranged. A portion where the scan electrode line, the sustain electrode line, and the address electrode line cross each other defines a discharge cell Ce, and the discharge cell Ce serves as a pixel of the plasma display panel. In the space of the discharge cell Ce, there are R, G, and B phosphors and a plasma forming gas, and wall charges are discharged inside the discharge cell Ce by the voltage applied to each of the scan electrode, the sustain electrode, and the address electrode. Is generated. Plasma is formed from the plasma forming gas by the wall charge, and phosphors of the discharge cells Ce are excited by ultraviolet radiation from the plasma to generate light.

FIG. 2 is a timing diagram illustrating an example of a conventional driving signal applied to each electrode of the plasma display panel in FIG. 1.

As a driving method of a plasma display panel, an address-display separation driving method which is mainly used is disclosed in US Pat. No. 5,541,618. That is, the unit frame may be divided into a predetermined number, for example, eight subfields to realize time division gray scale display, and each subfield is divided into a reset period, an address period, and a sustain discharge period. The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge period occupied in the unit frame. For example, if a unit frame is represented by eight subfields and 256 gray levels, the number of sustain pulses of 1, 2, 4, 8, 16, 32, 64, and 128 may be assigned to each subfield in turn. In order to obtain the luminance of 133 gray levels, the cells may be addressed and sustained and discharged during the subfield 1, subfield 3, and subfield 8 periods. Meanwhile, the number of sustain discharges allocated to each subfield may be variably determined according to weights of subfields according to APC (Automatic Power Control), and may be modified according to gamma characteristics or panel characteristics.

Referring to FIGS. 1 and 2, one subfield includes a reset period PR, an address period PA, and a sustain discharge period PS, and address electrode lines A1, A2, ..., Am), driving signals are applied to sustain electrode lines X1, X2, ..., Xn and scan electrode lines Y1, ..., Yn, respectively.

First, the reset period PR initializes the wall charge state of all the discharge cells Ce by applying reset pulses to all the scan electrode lines Y1,..., And Yn to perform reset discharge. The reset period PR is carried out before entering the address period PA, which is carried out over the entire screen, thus making it possible to create a fairly even and evenly distributed wall charge arrangement.

Next, in the address period PA, the bias voltage Vb is applied to the sustain electrode lines X1, X2, ..., Xn to select the cell to be turned on, and the scan electrode lines Y1. The scan high voltage Vsch is applied to Yn, and the scan pulses having the scan low voltage Vscl are sequentially applied to the scan electrode lines Y1, Y2, ..., Yn. A display data signal having an address voltage Va is applied to the address electrode lines A1, A2, ..., Am. As the scan pulse and the display data signal are applied, address discharge is performed in the selected discharge cell.

Next, in the sustain discharge period PS, sustain electrode lines X1, X2, ..., Xn and scan electrode lines such that sustain discharge is performed in the cell to be turned on selected in the address period PA. A sustain pulse having a sustain discharge voltage Vs is applied to (Y1, ..., Yn) alternately. The sustain discharge is performed by the wall charge accumulated in the discharge cell selected by the address discharge and the applied sustain discharge voltage Vs. Plasma is formed from the plasma forming gas of the discharge cells which perform the sustain discharge, and the phosphors of the discharge cells are excited by ultraviolet radiation from the plasma to generate light.

Meanwhile, in order to drive the plasma display panel, various voltages must be supplied from a power supply device (not shown) in the plasma display panel. As shown in FIG. 2, the sustain discharge voltage Vs, the rising voltage Vset, the falling lowest voltage Vnf, the scan high voltage Vsch, the scan low voltage Vscl, the address voltage Va, and the bias voltage Vb) must be supplied from the power supply to the driving device (not shown) of the plasma display panel. Since the power supply device receives the AC power and outputs the DC power, a plurality of converters are required to output all of the various voltages. Therefore, as the type of voltage increases, the manufacturing cost of the plasma display panel increases.

SUMMARY OF THE INVENTION In order to solve the above problems, an object of the present invention is to provide a driving method and a driving apparatus of a plasma display panel which reduces the type of power used to drive the plasma display panel, thereby reducing the manufacturing cost.

In order to achieve the above object, the present invention provides a plasma display panel including address electrode lines and scan electrode lines and sustain electrode lines intersecting the address electrode lines, wherein the unit frame is time-division gray scale display. In the driving method of the plasma display panel divided into a plurality of subfields for performing the reset, address, and sustain discharge step in each of the subfields,

In the reset step, the scan electrode lines reach a third voltage having a rising slope at a first voltage and increased by a second voltage, a fourth voltage having a falling slope at a third voltage,

In the address step, while the fifth voltage is applied to the scan electrode lines, the scan pulses having the sixth voltage are sequentially applied, and the display data signal having the seventh voltage is applied to the address electrode lines according to the scan pulse. An eighth voltage is applied to the sustain electrode lines,

In the sustain discharge step, sustain pulses having a first voltage are alternately applied to the scan electrode lines and the sustain electrode lines,

The fifth voltage has a magnitude equal to half the magnitude of the first voltage.

In order to achieve the above object, the present invention provides a plasma display panel driving apparatus for outputting a driving signal for driving a plasma display panel.

A main switch MM having one end connected to the scan electrode Cp of the plasma display panel;

A first energy recovery circuit connected to the other end of the main switch and including a first energy storage capacitor for charging or discharging charges accumulated in the scan electrodes of the panel, and a first energy recovery driver;

First and second switches having one end connected to the first voltage terminal Vs and the ground voltage terminal, and the other end connected to the other end of the main switch, respectively;

Third and fourth switches having one end connected to each of the fifth voltage terminal Vsch and the sixth voltage terminal Vscl, and the other end connected to one end of the main switch, respectively;

A first capacitor connected between the second voltage terminal Vset and the other end of the main switch, and a fifth switch connected between the second voltage terminal and one end of the main switch;

A sixth switch connected between the other end of the main switch and the fourth voltage terminal Vnf; And

A seventh switch connected between the first energy storage capacitor and the fifth voltage terminal,

In the reset step, when the fifth switch is turned on, the first switch is turned on to apply a rising ramp signal to the scan electrode, and then the main switch and the sixth switch are turned on at the same time so that the falling ramp signal is turned on. Is applied to the scan electrode,

In the addressing step, the third switch and the seventh switch are turned on, and the fourth switch is turned on while the third switch is turned off in an addressing period,

In the sustain discharge step, a driving apparatus of a plasma display panel in which the first switch and the second switch are alternately turned on is provided.

According to another aspect of the present invention, in the driving circuit, is connected to the sustain electrode (second end of the Cp) of the plasma display panel,

A second energy recovery circuit including a second energy storage capacitor for charging or discharging charges accumulated in the sustain electrode of the panel, and a second energy recovery driver; And

Eighth, ninth, and eighth ends of which are respectively connected to the sustain discharge voltage terminal Vs, the ground voltage terminal, and the bias voltage terminal Vb, and the other ends are respectively connected to the sustain electrode Cp of the panel. 10 switches may be further provided.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

Japanese Laid-Open Patent Publication No. 1999-120924 discloses a structure of a conventional plasma display panel. That is, between the front and rear glass substrates of a conventional plasma display panel, the address electrode lines A1, A2, Am, dielectric layer, scan electrode lines Y1, Yn, sustain Electrode lines X1, ..., Xn, fluorescent layers, barrier ribs and magnesium monoxide (MgO) protective layers are provided.

The address electrode lines A1, A2, ..., Am are formed in a predetermined pattern on the front side of the rear glass substrate. The lower dielectric layer is applied in front of the address electrode lines A1, A2, ..., Am. In front of the lower dielectric layer, barrier ribs are formed in a direction parallel to the address electrode lines A1, A2, ..., Am. These partitions partition the discharge area of each display cell and serve to prevent optical interference between each display cell. The fluorescent layer is applied in front of the dielectric layer on the address electrode lines A1, A2, ..., Am between the partition walls, and the red light emitting fluorescent layer, the green light emitting fluorescent layer, and the blue light emitting fluorescent layer are sequentially disposed.

The sustain electrode lines X1, ..., Xn and the scan electrode lines Y1, ..., Yn are formed so as to be orthogonal to the address electrode lines A1, A2, ..., Am. It is formed in a constant pattern on the back. Each intersection sets a corresponding display cell. Each sustain electrode line (X1, ..., Xn) and each scan electrode line (Y1, ..., Yn) have conductivity and transparent electrode line (Xna, Yna) of transparent conductive material such as ITO (Indium Tin Oxide) Metal electrode lines (Xnb, Ynb) to increase the can be formed by combining. The front dielectric layer is formed by applying the entire surface to the back of the sustain electrode lines X1, ..., Xn and the scan electrode lines Y1, ..., Yn. A protective layer for protecting the panel from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer. The plasma forming gas is sealed in the discharge space.

The driving method generally applied to the plasma display panel is a method in which the reset, address and sustain discharge steps are sequentially performed in the unit sub-field. In the reset step, the charge states of the display cells to be driven are made uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the sustain discharge step, display discharge is performed in the display cells to be selected. At this time, a plasma is formed from the plasma forming gas of the display cells which perform the display discharge, and the fluorescent layers of the display cells are excited by ultraviolet radiation from the plasma to generate light.

It should be noted that the method of driving the plasma display panel according to the present invention is not limited to the plasma display panel having the above structure, and can be applied to all plasma display panels having the three-electrode structure.

3 is a block diagram schematically illustrating a driving apparatus of a plasma display panel for realizing a method of driving a plasma display panel of the present invention.

Referring to FIGS. 1 and 3, a driving device for driving a plasma display panel includes an image processor 300, a logic controller 302, an address driver 306, an X driver 308, and a Y driver 304. It includes.

The image processor 300 receives an external image signal and performs image processing to output an internal image signal. The internal image signals include 8-bit red (R), green (G), and blue (B) image data, clock signals, and vertical and horizontal sync signals, respectively.

The logic controller 302 receives the internal image signal from the image processor 300 and undergoes gamma correction, automatic power control (APC), and the like, and scans the address electrode lines A1, A2,. Outputs drive control signals SA, SY, and SX for controlling drive signals applied to each of the electrode lines Y1, ..., Yn and sustain electrode lines X1, ..., Xn. .

The address driver 306 receives and processes the address signal SA from the driving control signals SA, SY, and SX from the logic controller 302 to generate a display data signal, and generates the display data signal. It is applied to the electrode lines A1, A2, ..., Am.

The X driver 308 receives the X driving control signal SX from the driving control signals SA, SY, and SX from the logic controller 302, processes the X driving control signal SX, and maintains the sustain electrode lines X1,..., Xn. To apply.

The Y driver 304 receives and processes the Y driving control signal SY from the driving control signals SA, SY, and SX from the logic controller 302 to scan electrode lines Y1,..., Yn. To apply.

4 is a timing diagram showing a driving signal as a driving method of the plasma display panel of the present invention.

1 and 4, in the reset period PR, a reset pulse is applied to all scan electrode lines to force a write discharge, thereby initializing the wall charge state of all cells. The reset period PR is performed before entering the address period PR, which is carried out over the entire screen, thus making it possible to create a wall distribution of wall charges with a fairly even and desired distribution. The cells initialized by the reset period PR have similar wall charge conditions inside the cells.

For this purpose, in the reset period PR, the ground voltage Vg is first applied to the scan electrode lines Y1, ..., Yn. Next, the sustain discharge voltage Vs, which is the first voltage, is rapidly applied at a time t1, and a rising ramp signal is applied from the time t1 to t2 so that the rising voltage Vset is a second voltage than the first voltage Vs. It increases and reaches the 3rd voltage, the highest rising voltage (Vset + Vs). Next, a first voltage Vs is applied at time t2, and a falling ramp signal is applied at time t2 to t3 to reach the fourth falling voltage, Vnf. The erase pulse is applied to the sustain electrode lines X1, ..., Xn until time t1, and then the ground voltage Vg is applied from time t1 to t2, and the bias voltage is an eighth voltage from time t2 to t3. (Vb) is applied. The ground voltage Vg is applied to the address electrode lines A1, A2, ..., Am during the reset period PR.

In order to select a cell to be turned on during the address period PA, that is, from time t3 to time t4, the fifth voltage 0.5Vs is first applied to the scan electrode lines Y1, ..., Yn with a scan high voltage. After being applied, a scan pulse having a scan low voltage Vscl, which is a sixth voltage, is sequentially applied to each scan electrode line. A display data signal having an address voltage Va, which is a seventh voltage, is applied to the address electrode lines A1, A2, ..., Am in accordance with the scan pulse. The eighth voltage Vb is continuously applied to the sustain electrode lines X1,..., Xn.

An object of the present invention is to reduce the type of power supplied from the power supply (not shown) to the driving device of the plasma display panel in order to reduce the manufacturing cost of the plasma display panel. Conventionally, the scan high voltage Vsch of FIG. 2 is used as the fifth voltage. However, in the present invention, the fifth voltage 0.5Vs, which is half the magnitude of the first voltage Vs, is used as the scan high voltage Vsch. Characterized in that. This may be implemented using an energy storage capacitor of an energy recovery circuit in the driving apparatus of the plasma display panel, and a detailed description thereof will be described with reference to FIG. 5.

In the sustain discharge period PS, the sustain discharge voltage Vs and the ground voltage Vg are applied to the scan electrode lines Y1, ..., Yn and the sustain electrode lines X1, ..., Xn. Holding pulses are alternately applied. The ground voltage Vg is applied to the address electrode lines A1, A2, ..., Am.

In detail, the first voltage Vs is rapidly applied at the time t1 to the scan electrode lines Y1,..., And Yn in the reset period PR. A rising ramp signal is applied from t1 to t2 to reach the third voltage Vset + Vs that is increased by the second voltage Vset. The first initialization discharge occurs while the rising ramp signal is applied. The first initialization discharge is a weak discharge generated by the application of a rising ramp signal having an insignificant slope, and as the weak discharge occurs, negative charges begin to accumulate in the vicinity of the scan electrode lines Y1, ..., Yn. . At a time t2, the voltage drops rapidly to the first voltage, and a falling ramp signal is applied from the time t2 to the time t3 to finally reach the fourth voltage Vnf. The second initialization discharge is generated while the falling ramp signal is applied. The second initialization discharge is a weak discharge generated by the application of a falling ramp signal having an insignificant slope, and the negative charge accumulated in the vicinity of the scan electrode lines Y1,... Is released. In the reset period PR, a negative charge appropriate for generating an address discharge remains near the scan electrode lines Y1, ..., Yn, and the address electrode lines A1, A2, ..., Am ) A positive amount of positive charge will remain.

In the address period PA, an address discharge occurs to select a cell to be turned on. First, the fifth voltage 0.5Vs is applied to the scan electrodes, and then the scan pulses having the sixth negative voltage Vscl are sequentially applied to the scan electrode lines, and the address electrode lines A1, A2,. Am) is applied with a display data signal having a seventh voltage Va in accordance with the scan pulse. That is, the seventh voltage Va applied to the address electrode A, the sixth voltage Vscl applied to the scan electrode Y, and the wall voltage due to the negative charge near the scan electrode Y and the vicinity of the address electrode The address discharge is performed in the discharge cell by the wall voltage caused by the positive charge of. After the address discharge is performed, positive charges are accumulated near the scan electrode Y, and negative charges are accumulated near the sustain electrode X.

For example, when the first voltage Vs is about 170V, the fifth voltage 0.5Vs is about 85V. When the conventional scan high voltage is about 20V, the fifth voltage 0.5Vs, which is the scan high voltage Vsch of the present invention, increases about 65V as compared with the conventional art. However, since the address discharge is mainly caused by the potential difference between the seventh voltage Va applied to the address electrode and the sixth voltage Vscl applied to the scan electrode, the fifth voltage 0.5Vs of the present invention is applied to the scan electrode. Even if it is applied, it does not have a large influence on address discharge, but rather reduces the manufacturing cost of the plasma display panel which is an object of the present invention.

In the sustain discharge period PS, a sustain discharge occurs in a cell selected in the address period PA. First, when the first voltage Vs is applied to the scan electrode Y and the ground voltage Vg is applied to the sustain electrode X, the first voltage Vs applied to the scan electrode Y and the sustain voltage are maintained. The primary sustain discharge is performed inside the discharge cell by the ground voltage Vg applied to the electrode X, the positive charge near the scan electrode Y and the negative charge near the sustain electrode X. After the first sustain discharge is performed, negative charges are accumulated near the scan electrode Y, and positive charges are accumulated near the sustain electrode X. Next, when the ground voltage Vg is applied to the scan electrode Y and the first voltage Vs is simultaneously applied to the sustain electrode X, the first voltage Vs applied to the sustain electrode X and the first voltage Vs are applied. The second sustain discharge is performed in the discharge cell by the ground voltage Vg applied to the scan electrode Y, the positive charge near the sustain electrode X and the negative charge near the scan electrode Y. Next, the first voltage Vs is applied to the scan electrode Y, and the ground voltage Vg is applied to the sustain electrode X, and the above process is repeated. In this way, the sustain pulse is alternately applied to the scan electrode Y and the sustain electrode X, and sustain discharge is continuously performed.

5 is a circuit diagram showing a driving device of the plasma display panel of the present invention.

Hereinafter, a description will be given with reference to FIGS. 1 and 3 to 5. The panel capacitor Cp represents the capacitance of the plasma display panel, and the scan electrode Y is connected to the first end of the panel capacitor Cp, and the sustain electrode X is connected to the second end of the panel capacitor Cp.

First, a part of the Y driving unit 304 of FIG. 3 of the driving apparatus of FIG. 5 will be described.

One end of the main switch MM is connected to the first end of the panel capacitor Cp. At the other end of the main switch MM, a first energy storage capacitor Cyerc for charging or discharging charges accumulated in the scan electrode Y of the panel and a first energy recovery driver 702 are provided. The recovery circuit Y-ERC is connected. In addition, a first switch M1 for switching the first voltage Vs is connected between the other end of the main switch MM and the first voltage terminal Vs, and the other end of the main switch MM is grounded. The second switch M2 for switching the ground voltage Vg is connected therebetween. In addition, a third switch M3 for switching the fifth voltage 0.5Vs is connected between one end of the main switch MM and the fifth voltage terminal Vsch, and one end of the main switch MM. The fourth switch M4 for switching the sixth voltage Vscl is connected between the sixth voltage terminals Vscl. In addition, a first capacitor C1 is connected between the other end of the main switch MM and the second voltage terminal Vset, and a fifth switch is connected between one end of the main switch MM and the second voltage terminal Vset. A fifth switch M6 for switching the fourth voltage Vnf is connected between the other end of the main switch MM and the fourth voltage terminal Vnf.

Meanwhile, according to an object of the present invention, a seventh switch M7 is connected between the first energy storage capacitor Cyerc and the fifth voltage terminal Vsch. This supplies a fifth voltage (0.5Vs) stored in the first energy storage capacitor (Cyerc) to the fifth voltage terminal (Vsch).

Next, the X driver 308 of FIG. 3 among the driving apparatus of FIG. 5 will be described.

The second end of the panel capacitor Cp includes a second energy storage capacitor Cxerc for charging or discharging the charge accumulated on the sustain electrode X of the panel, and a second energy recovery driver 712. An energy recovery circuit (X-ERC) is connected. In addition, an eighth switch M8 for switching the first voltage Vs is connected between the second terminal of the panel capacitor Cp and the first voltage terminal Vs, and the second terminal of the panel capacitor Cp is grounded. A ninth switch M9 for switching the ground voltage is connected therebetween. In addition, a tenth switch M10 for switching the eighth voltage Vb is connected between the second terminal of the panel capacitor Cp and the eighth voltage terminal Vb.

Hereinafter, the operation of the driving apparatus of FIG. 5 for applying the driving signal of FIG. 4 will be described. First, the driving signals applied to the scan electrode lines Y1, ..., Yn will be described.

In the reset period PR, the ground voltage Vg is applied until the time t1. To this end, the second switch M2 and the main switch MM are turned on, and the other switches are turned off. Therefore, the ground voltage Vg is applied to the first terminal of the panel capacitor Cp, that is, the scan electrode Y.

Next, the first voltage Vs is suddenly applied at time t1. To this end, the first switch M1 and the main switch MM are turned on, and the other switches are turned off. Therefore, the first voltage Vs is applied to the first terminal of the panel capacitor Cp, that is, the scan electrode Y.

Next, from time t1 to time t2, a voltage is applied with a rising slope at the first voltage Vs to finally reach the third voltage. To this end, the first switch M1 is turned on, the first voltage Vs is stored in the first capacitor C1, and the fifth switch M5 is turned on, thereby increasing the slope from the first voltage Vs. And reaches the third voltage Vset + Vs which is increased by the second voltage Vset. The rising slope here is implemented by the fifth switch M5.

Next, the first voltage Vs is rapidly applied at the time t2. To this end, the first switch M1 and the main switch MM are turned on, and the other switches are turned off.

Next, from time t2 to time t3, a voltage is applied with a falling slope at the first voltage Vs to finally reach the fourth voltage. For this purpose, the sixth switch M6 and the main switch MM are turned on, and the other switches are turned off.

Next, during the address period PR, i.e., the period from time t4 to time t5, the fifth voltage 0.5Vs is applied to the scan electrode Y as the scan high voltage Vsch. To this end, the seventh switch M7 and the third switch M3 are turned on, and the other switches are turned off. The fifth voltage 0.5Vs stored in the first energy storage capacitor Cyerc reaches the fifth voltage terminal Vsch when the seventh switch M7 is turned on, and the third switch M3 is turned on. It is turned on and applied to the first end of the panel capacitor Cp, that is, the scan electrode Y.

The fifth voltage 0.5Vs stored in the first energy storage capacitor Cyerc is a voltage stored by charging the charge of the panel capacitor Cp.

The sixth voltage Vscl is sequentially applied to each scan electrode line. For this purpose, the sixth switch M6 is turned on and the other switches are turned off.

Next, the sustain pulse having the first voltage Vs and the ground voltage Vg alternates between the scan electrode Y and the sustain electrode X during the sustain discharge period PS, that is, from the time t5 to the time t6. Is authorized.

First, when the first voltage Vs of the scan electrode Y is applied, for this purpose, the first switch M1 and the main switch MM are turned on, and the other switches are turned off. When the ground voltage Vg is applied to the scan electrode Y, the second switch M2 and the main switch MM are turned on, and the other switches are turned off.

The driving signal applied to the sustain electrode lines X1,..., Xn during the operation of the driving apparatus of FIG. 5 for applying the driving signal of FIG. 4 will be described.

The eighth voltage Vb applied to the reset period PR and the address period PA is applied to the second terminal of the panel capacitor Cp, that is, the sustain electrode X. To this end, the tenth switch M8 This turn is on.

In the sustain discharge period PS, a sustain pulse having the first voltage Vs and the ground voltage Vg is applied. First, in order for the ground voltage Vg to be applied to the second terminal of the panel capacitor Cp, that is, the sustain electrode X, the ninth switch M9 is turned on and the other switches are turned off. Next, in order for the first voltage Vs to be applied to the second terminal of the panel capacitor Cp, that is, the sustain electrode X, the eighth switch M8 is turned on and the other switches are turned off.

 According to an exemplary embodiment of the present invention, the scan voltage is applied to the scan high voltage terminal Vsch by using the fifth voltage 0.5Vs stored in the first energy storage capacitor Cyerc. To this end, the first energy storage capacitor Cyerc is connected to the scan high voltage terminal Vsch through a seventh switch.

According to the present invention as described above, the following effects can be obtained.

The present invention provides a driving method of a plasma display panel using a fifth voltage, which is half the size of the first voltage, for a scan high voltage (Vsch) applied in an address period. By connecting the first high energy storage capacitor (Cyerc) and the scan high voltage terminal (Vsch) of the Y energy recovery circuit (Y-ERC) provided in the Y driving unit, it is possible to reduce the number of power supplied from the power supply, This can reduce the number of converters used in the power supply, which in turn reduces the manufacturing cost of the plasma display panel.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Claims (3)

For a plasma display panel including address electrode lines and scan electrode lines and sustain electrode lines intersecting the address electrode lines, the unit frame is divided into a plurality of subfields for time division gray scale display, and the subfield A driving method of a plasma display panel in which reset, address, and sustain discharge steps are performed in each of the above, In the reset step, the scan electrode lines reach a third voltage having a rising slope at a first voltage and increased by a second voltage, reaching a fourth voltage having a falling slope at the third voltage, In the address step, while a fifth voltage is applied to the scan electrode lines, scan pulses having a sixth voltage are sequentially applied, and display data signals having a seventh voltage according to the scan pulses to the address electrode lines. Is applied, an eighth voltage is applied to the sustain electrode lines, In the sustain discharge step, sustain pulses having the first voltage are alternately applied to the scan electrode lines and the sustain electrode lines, The magnitude of the fifth voltage is half the magnitude of the first voltage. In the driving device of the plasma display panel for outputting a driving signal for driving the plasma display panel, A main switch MM having one end connected to the scan electrode Cp of the plasma display panel; A first energy recovery circuit connected to the other end of the main switch and having a first energy storage capacitor and a first energy recovery driver for charging or discharging charges accumulated in the scan electrode of the panel; First and second switches having one end connected to a first voltage terminal Vs and a ground voltage terminal, and the other end connected to the other end of the main switch, respectively; Third and fourth switches having one end connected to a fifth voltage terminal Vsch and a sixth voltage terminal Vscl, respectively, and the other ends connected to one end of the main switch, respectively; A first capacitor connected between a second voltage terminal (Vset) and the other end of the main switch, and a fifth switch connected between the second voltage terminal and one end of the main switch; A sixth switch connected between the other end of the main switch and a fourth voltage terminal Vnf; And A seventh switch connected between the first energy storage capacitor and the fifth voltage terminal; In the reset step, when the fifth switch is turned on, the first switch is turned on to apply a rising ramp signal to the scan electrode, and then the main switch and the sixth switch are turned on at the same time so that the falling ramp signal is turned on. Is applied to the scan electrode, In the addressing step, the third switch and the seventh switch are turned on, and the fourth switch is turned on while the third switch is turned off in an addressing period, The driving device of the plasma display panel in which the first switch and the second switch are alternately turned on in the sustain discharge step. The method of claim 2, Is connected to the sustain electrode C2 of the plasma display panel; A second energy recovery circuit including a second energy storage capacitor and a second energy recovery driver for charging or discharging charges accumulated in the sustain electrode of the panel; And And further comprising eighth, ninth, and tenth switches each having one end connected to the sustain discharge voltage terminal Vs, the ground voltage terminal, and the bias voltage terminal Vb, and the other end connected to the sustain electrode of the panel. A drive device for a plasma display panel.

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