KR20050072504A - Optic mask for crystallization and manufacturing method of thin film transistor array panel using the same - Google Patents

Abstract

The crystallization photomask according to the present invention is a crystallization mask for locally irradiating a laser beam in a crystallization process of crystallizing amorphous silicon, and the photomask has a slit defining a light-transmitting region through which the laser beam is transmitted. At least one slit region, wherein the slit is formed at an angle to the moving direction of the mask in the crystallization process, the slit region is a first portion having a first length, a second length longer than the first length The branch comprises a second portion.

Description

Optical mask for crystallization and manufacturing method of thin film transistor array panel using the same}

The present invention relates to a crystallization photomask for crystallizing amorphous silicon with polycrystalline silicon and a method of manufacturing a thin film transistor array panel using the same.

Generally, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used in semiconductor layers of switching elements of display devices that use glass having a low melting point as a substrate.

However, the amorphous silicon thin film has difficulty in large area of the display device due to problems such as low field effect mobility. Therefore, there is a need for the application of polycrystalline silicon having high field effect mobility, high frequency operating characteristics, and low leakage current electrical characteristics.

Methods for forming such polycrystalline silicon include ELA (eximer laser anneal, ELA), furnace anneal (chamber anneal), etc. Recently, SLS (sequential lateral) that induces lateral growth of silicon crystals by laser to produce polycrystalline silicon solidification, hereinafter referred to as SLS) technology.

The SLS technology takes advantage of the fact that silicon particles grow in the direction perpendicular to the interface between the liquid region and the solid region, and the transmission region of the slit formed with the laser beam having energy for melting silicon into the liquid phase is masked. By passing through and laterally growing the silicon particles by a predetermined length, the amorphous silicon is crystallized.

In such a polycrystallization process, since the characteristics of the thin film transistor change depending on the growth direction of the grains, it is preferable that the grain growth direction is uniform.

However, in the case where the slit is formed at an arbitrary angle with respect to the direction of movement of the photomask, a portion where amorphous silicon is not crystallized may occur at the boundary of the shot, which is severe when the misalignment of the mask occurs. appear.

If the semiconductor layer or the like of the thin film transistor is located in such a portion, pixel defects or the like may occur, resulting in a problem of lowering display characteristics.

The present invention provides a crystallization photomask capable of uniformly securing the characteristics of a thin film transistor and a method of manufacturing the thin film transistor array panel using the same.

The crystallization photomask according to the present invention for achieving the above object is a crystallization mask for locally irradiating a laser beam in the crystallization process of crystallizing amorphous silicon, the photomask defines a light-transmitting region through which the laser beam is transmitted. The slit includes at least one slit region in which the slits are uniformly arranged, and the slits are formed to be inclined at a predetermined angle with respect to the moving direction of the mask in the crystallization process, and the slit region is a first portion having a first length, a first And a second portion having a second length longer than the length.

The second length is preferably longer by the alignment error range of the mask than the first length.

It is preferable that the slits of the different slit regions are arranged to be offset to each other.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor array panel, the method including forming an amorphous silicon film on an insulating substrate, and forming a first portion having a slit of a first length in the amorphous silicon film and a slit of a second length. Irradiating and irradiating the amorphous silicon film with a laser through a photomask including a second portion of the branch to repeat the steps of forming a polycrystalline silicon film, patterning the polycrystalline silicon film to form a semiconductor layer, covering the semiconductor layer Forming a gate insulating film to form a gate insulating film, forming a gate line overlapping a portion of the semiconductor layer on the gate insulating film, and doping a predetermined region of the semiconductor layer at a high concentration to form a source region and a drain region, and the gate Forming a first interlayer insulating film to cover the lines and the semiconductor layer, the source zero on the first interlayer insulating film Forming a data electrode having a source electrode connected to the drain electrode and a drain electrode connected to the drain region; forming a second insulating interlayer on the data line and the drain electrode; and forming a pixel electrode connected to the drain electrode on the second insulating interlayer. Forming a step.

Or forming an amorphous silicon film on the insulating substrate, irradiating a laser to the amorphous silicon film through an optical mask including an optical mask including a first part having a slit of a first length and a second part having a slit of a second length in the amorphous silicon film. And repeating the step of moving to form a polycrystalline silicon film, patterning the polycrystalline silicon film to form a semiconductor layer, forming a gate insulating film to cover the semiconductor layer, and partially overlapping the semiconductor layer on the gate insulating film. Forming a gate line and a data metal piece, forming a source region and a drain region by highly doping conductive impurities in a predetermined region of the semiconductor layer, forming an interlayer insulating film to cover the semiconductor layer, and forming a source on the interlayer insulating film. A data connection part connected to the region and the data metal piece, and a pixel electrode connected to the drain region. And a step of.

The method may further include forming a lightly doped region by doping the semiconductor layer at a lower concentration than the source and drain regions.

And forming a blocking film between the insulating substrate and the semiconductor layer.

At this time, the slits are preferably arranged inclined by a predetermined angle with respect to the moving direction of the photomask.

The photomask preferably has a first region and a second region having a first portion and a second portion, and slits of the first region and the second region are arranged to be shifted.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The photomask for crystallization according to the embodiment of the present invention includes a slit having a first length and a slit having a second length. This will be described in detail through a method of manufacturing a thin film transistor array panel.

 [First Embodiment]

1 is a layout view of a thin film transistor array panel for explaining an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG. 1.

As illustrated, a blocking film 111 made of silicon oxide or the like is formed on the transparent insulating substrate 110. The semiconductor layer 150 is formed on the blocking layer 111 and includes a source region 153 and a drain region 155 doped with impurities, and a channel region 154 formed of an intrinsic semiconductor. Is formed. A lightly doped drain 152 is formed between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer 150.

The lightly doped region 152 prevents leakage current or punch through. In the source region 153 and the drain region 155, conductive impurities are heavily doped, and in the lightly doped region 152, the conductive impurities are less doped than the source region 153 and the drain region 155. .

The conductive impurity is a P-type or N-type impurity, and boron (B) and gallium (Ga) are used as the P-type impurity, and phosphorus (P), arsenic (As), etc. are used as the N-type impurity. This can be used.

A gate insulating layer 140 made of silicon nitride, silicon oxide, or the like is formed on the semiconductor layer 150. In addition, a gate line 121 extending in one direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends to overlap the channel region 154 of the semiconductor layer 150. The lightly doped region 152 may be formed to overlap (not shown) the gate line 121. The portion overlapping the channel region 154 is used as the gate electrode 124 of the thin film transistor.

In addition, the storage electrode line 131 for increasing the storage capacitance of the pixel is parallel to the gate line 121 and is formed in the same layer with the same material. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 overlapping the storage electrode 133 becomes the storage electrode region 157. One end of the gate line 121 may be formed wider than the width of the gate line 121 in order to connect to an external circuit (not shown).

The first interlayer insulating layer 601 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131. The first interlayer insulating layer 601 includes first and second contact holes 161 and 162 exposing the source region 153 and the drain region 155, respectively.

A data line 171 is formed on the first interlayer insulating layer 601 to cross the gate line 121 to define a pixel area. A portion or branched portion of the data line 171 is connected to the source region 153 through the first contact hole 161, and the portion 173 connected to the source region 153 is a source electrode (eg, a thin film transistor). 173). One end of the data line 171 may be formed wider than the width of the data line 171 to connect to an external circuit.

A drain electrode 175 is formed on the same layer as the data line 171 and is separated from the source electrode 173 and connected to the drain region 155 through the second contact hole 162.

A second interlayer insulating layer 602 is formed on the first interlayer insulating layer 601 including the drain electrode 175 and the data line 171. The second interlayer insulating layer 602 has a third contact hole 163 exposing the drain electrode 175.

The pixel electrode 190 connected to the drain electrode 175 is formed on the second interlayer insulating layer 602 through the third contact hole 163.

A method of manufacturing the thin film transistor array panel according to the first embodiment of the present invention described above will be described in detail with reference to FIGS. 1 and 2 described above with reference to FIGS. 3A to 13B.

3A, 6A, 8A, and 9A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line IIIb-IIIb 'of FIG. 3A. 4 and 5 illustrate crystallization using a photomask pattern according to the present invention, FIG. 6B is a cross-sectional view taken along line VIb-VIb 'of FIG. 6A, and FIG. 7 is a next step of FIG. 6B. 8B is a cross-sectional view taken along the line VIIIb-VIIIb 'of FIG. 8A, and FIG. 9B is a cross-sectional view taken along the line IXb-IXb' of FIG. 9A.

First, as shown in FIGS. 3A and 3B, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film which is not doped with impurities is formed to a thickness of 400 to 1,200 kPa by a method such as chemical vapor deposition.

The amorphous silicon film is then crystallized by a sequential lateral solid phase crystallization method to form a polycrystalline silicon film. The polysilicon film is patterned by a photolithography process using a photomask to form a semiconductor layer 150 made of polycrystalline silicon.

A method of crystallizing with the SLS method will be described in more detail with reference to FIGS. 4 and 5 as follows. 4 is a layout view illustrating a slit of an optical mask according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating a moving state of the optical mask according to an exemplary embodiment of the present invention.

In order to polycrystalline amorphous silicon, as shown in FIG. 4, the mask MP having a predetermined pattern is aligned on the amorphous silicon film 10.

The photomask MP shown in FIG. 4 is divided into A area A and B area B having the same pattern, and each of the areas A and B has slits S1 and S2 through which a laser beam is transmitted. ) Are arranged at regular intervals to form a slit row. At this time, the slits disposed in the A region A and the B region B are arranged to be offset from each other, and are tilted by a predetermined angle with respect to the moving direction of the photomask during the crystallization process.

In addition, the slit S1 located at one end part in each area | region is formed long in length compared with the slit S2 located in the other part. At least one slit (S1) longer than the other slits is preferable, and as the angle formed by the slit with respect to the moving direction of the mask increases, the number of long slits is preferably increased by several.

Next, when the laser is irradiated to the amorphous silicon film 10 through the slits S1 and S2 of the aligned photomask, the amorphous silicon irradiated with the laser through the slits S1 and S2 turns into a liquid phase and the portion of the portion where the laser is not irradiated. Amorphous silicon remains solid. Therefore, crystallization proceeds at the interface between the liquid phase and the solid phase, and grains grow perpendicularly to the interface of the solid phase.

Subsequently, the optical mask is moved horizontally as shown in FIG. 5 and then crystallized by irradiating a laser. Here, grains grown perpendicular to the boundary of the solid phase meet and stop growth. At this time, the process of irradiating and moving the laser proceeds with respect to the entire amorphous silicon film. After the movement in the horizontal direction, the crystal is crystallized while moving vertically and horizontally moving in the opposite direction. In other words, the amorphous silicon film is crystallized into polycrystalline silicon while the photomask is moved in a zigzag form.

In this case, when the at least one slit S1 disposed at the edge is formed longer than the other slit S2 as in the present invention, the amorphous part positioned at the boundary portion Q of the shot even if misalignment occurs in the optical system or the optical mask. Silicon can be fully crystallized.

Here, the length of the slit S1 located at the edge is preferably as long as the alignment error range of the mask compared to the other portion S2, and in the embodiment of the present invention, it is longer by 3 to 4um. In addition, a plurality of slits S1 having a long length may be formed in accordance with an angle at which the slits S1 and S2 are inclined.

6A and 6B, an insulating material such as silicon nitride or silicon oxide is deposited on the semiconductor layer 150 by chemical vapor deposition to form a gate insulating layer 140. Thereafter, silver (Ag), copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof is deposited on the gate insulating layer 140 to form a metal film.

After the photoresist is coated on the metal layer, the photoresist pattern PR is formed by a photo process using a photomask. The gate layer 121 and the storage electrode line 131 are formed by wet or dry etching the metal layer by an etching process. At this time, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photosensitive film pattern PR.

Side surfaces of the gate line 121 and the storage electrode line 131 are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.

Thereafter, the semiconductor layer 150 is doped with a high concentration of conductive impurities using the photoresist pattern PR as a mask to form source and drain regions 153 and 155.

Next, as shown in FIG. 7, after removing the photoresist pattern PR, the semiconductor layer 150 is lightly doped with a conductive dopant in a low concentration doping region 152 using the gate line 121 and the storage electrode line 131 as a mask. The semiconductor layer 150 having () is completed. When the gate line 121 is not formed of a high heat resistant and high chemical material such as titanium, an impurity may be doped after forming the photoresist pattern PR to reduce damage to the wiring.

The lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern PR as described above, or by forming spacers or the like on sidewalls of the gate line 121.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

Subsequently, as shown in FIGS. 8A and 8B, a first interlayer insulating film 601 is formed on the entire surface of the substrate 110 and etched by a photolithography process to expose the source and drain regions 153 and 155. The contact holes 161 and 162 are formed.

The interlayer insulating layer 160 has excellent planarization characteristics, and is formed of a-Si: C: O, a-Si: O: organic material having photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). Low dielectric constant insulating materials, such as F, or an inorganic material, such as silicon nitride can be formed.

Next, tungsten, titanium, aluminum, or an alloy thereof is deposited on the first interlayer insulating film 601 in a single layer or a plurality of layers to form a metal film. Subsequently, the metal layer is patterned by a photolithography process, and the data line 171 and the drain electrode 175 having the source electrode 173 connected to the source region 153 and the drain region 155 through the contact holes 161 and 162, respectively. ).

Sidewalls of the data line 171 and the drain electrode 175 may be formed to be tapered to improve adhesion to the upper layer.

As shown in FIGS. 9A and 9B, a second interlayer insulating film 602 covering the data line 171 and the drain electrode 175 is formed. Thereafter, the second interlayer insulating layer 602 is patterned by a photolithography process to form a third contact hole 163 exposing the drain electrode 175. The second interlayer insulating film 602 may also be formed of the same material as the first interlayer insulating film 601.

1 and 2, a transparent conductive film such as indium zinc oxide (IZO), indium tin oxide (ITO), or the like is formed on the second interlayer insulating film, and then patterned and drained through the third contact hole 163. The pixel electrode 190 connected to the electrode 175 is formed.

When the second interlayer insulating layer 602 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the data line and the gate line to improve the aperture ratio of the pixel region.

 Second Embodiment

FIG. 10 is a layout view of a TFT panel for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view taken along the line XI-XI′-XI ″ of FIG. 10.

In Embodiment 2, the data connection part 171b and the pixel electrode 190 are formed on the same layer using the same material, and the pixel electrode 190 and the data connection part 171b are formed on the source and drain regions 153 and 155 of the semiconductor layer 150. ), Since the contact holes 161 and 162 for connecting to the plurality of holes are simultaneously formed, the number of masks can be reduced as compared with the first embodiment.

More specifically, as shown in FIGS. 10 and 11, the blocking layer 111 is formed on the transparent insulating substrate 110. A semiconductor layer including a source region 153, a drain region 155, and a channel region 154 formed of an intrinsic semiconductor between the conductive layer and the dopant having a high concentration of conductive impurities on the blocking layer 111. 150 is formed. Further, conductive impurities are doped at a lower concentration than the source and drain regions between the source region 153 and the channel region 154 and the drain region 155 and the channel region 154 of the semiconductor layer 150.

The gate insulating layer 140 is formed on the substrate 110 including the semiconductor layer 150. A gate line 121 extending in the horizontal direction is formed on the gate insulating layer 140, and a portion of the gate line 121 extends in the vertical direction to partially overlap the semiconductor layer 150, and overlaps the semiconductor layer 150. A portion of the gate line 121 is used as the gate electrode 124.

One end of the gate line 121 may be formed larger than the width of the gate line 121 to receive a scan signal from an external circuit (not shown).

In addition, the storage electrode line 131 is formed in the same layer with the same material as the gate line 121 so that the storage electrode line 131 is formed to be parallel to the gate line 121 and is positioned in parallel. A portion of the storage electrode line 131 overlapping the semiconductor layer 150 becomes the storage electrode 133, and the semiconductor layer 150 disposed under the storage electrode 133 becomes the storage electrode region 157.

The data metal piece 171a is formed at a distance from the gate line 121 and extends in a direction perpendicular to the gate line 121, and is formed on the same layer as the gate line 121. The data metal piece 171a is formed not to be connected to the gate line 121 between two adjacent gate lines 121. In addition, the data metal piece 171a may enlarge and form one end of the data metal piece 171a in the outermost row in order to receive an image signal from an external circuit (not shown).

An interlayer insulating layer 160 is formed on the gate insulating layer 140 including the gate line 121 and the storage electrode line 131.

The data connection part 171b, the pixel electrode 190, and the contact auxiliary member 82 are formed on the interlayer insulating layer 160. The data connection part 171b is formed to cross the gate line 121 and the storage electrode line 131 in the vertical direction.

The data metal piece 171a is connected to the data connecting portion 171b through the third contact hole 163 formed in the interlayer insulating layer 160, and the data connecting portion 171b is connected to the source through the first contact hole 161. It is connected to the area 153. That is, the data metal pieces 171a separated by the data connection part 171b are connected across the gate line 121 and the storage electrode line 131. The pixel electrode 190 is connected to the drain region 155 through a second contact hole 162 formed over the interlayer insulating layer 160 and the gate insulating layer 140, and the contact auxiliary member 82 is interlayered. The fourth contact hole 164 formed in the insulating layer 160 is connected to one end of the gate line 121 and the data metal piece 171a, respectively.

The contact auxiliary member 82 is not essential to serve to protect adhesion between the end of the data line 171a and the external device and to protect them, and application thereof is optional. In particular, when the driving circuit is formed together with the thin film transistor in the display area, it is not formed.

A method of manufacturing the thin film transistor array panel according to the second embodiment of the present invention described above will be described in detail with reference to FIGS. 10 and 11 together with FIGS. 12A to 15B.

12A, 13A, and 15A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention, and FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb′-XIIb ″ of FIG. 12A. FIG. 13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of 12A, FIG. 14 is a cross-sectional view at the next step of FIG. 13B, and FIG. 15B is taken along the line XVb-XVb'-XVb" of FIG. 15A. It is a cross section.

First, as shown in FIGS. 12A and 12B, the blocking layer 111 is formed on the transparent insulating substrate 110. In this case, glass, quartz, sapphire, or the like may be used as the transparent insulating substrate 110, and the blocking layer is formed by depositing silicon oxide (SiO ₂ ) or silicon nitride (SiNx) to a thickness of about 1,000 GPa. Subsequently, impurities such as a native oxide film on the blocking film 111 are removed by cleaning.

Next, an amorphous silicon film which is not doped with impurities is formed to a thickness of 400 to 1,200 kPa by a method such as chemical vapor deposition.

Then, the amorphous silicon film is crystallized by the SLS method to form a polycrystalline silicon film. The method of crystallization is the same as that described in FIGS. 4 and 5 of the first embodiment.

The polysilicon film is patterned by a photolithography process using a photomask to form a semiconductor layer 150 made of polycrystalline silicon. Therefore, the semiconductor layer 150 has the same crystal pattern as in the first embodiment.

13A and 13B, the polycrystalline silicon film is patterned by a photolithography process using a photomask to form a semiconductor layer 150 made of polycrystalline silicon.

The gate insulating layer 140 is formed by depositing an insulating material such as silicon nitride or silicon oxide on the semiconductor layer 150 by chemical vapor deposition. Thereafter, copper (Cu), silver (Ag), titanium (Ti), aluminum (Al), tungsten (W), or an alloy thereof is deposited on the gate insulating layer 140 to form a metal film.

After the photoresist is coated on the metal layer, the photoresist pattern PR is formed by a photo process using a photomask. The metal film is wet or dry etched by the etching process to form the gate line 121, the storage electrode line 131, and the data metal piece 171a. At this time, the metal film is over-etched to form a width of the gate line 121 and the storage electrode line 131 smaller than that of the photoresist pattern PR.

Side surfaces of the gate line 121, the storage electrode line 131, and the data metal piece 171a are formed to be tapered to increase adhesion to the upper layer. If the storage capacitor is sufficient, the storage electrode line 131 is not formed.

Thereafter, the semiconductor layer 150 is doped with a high concentration of conductive impurities using the photoresist pattern PR as a mask to form source and drain regions 153 and 155.

Next, as shown in FIG. 14, after removing the photoresist pattern PR, the semiconductor layer 150 is lightly doped with a conductive dopant in the low concentration doped region 152 using the gate line 121 and the storage electrode line 131 as a mask. The semiconductor layer 150 having () is completed. When the gate line 121 is not formed of a high heat resistant and high chemical material such as titanium, an impurity may be doped after forming the photoresist pattern PR to reduce damage to the wiring.

The lightly doped region 152 may be formed by using metal layers having different etching ratios in addition to the photoresist pattern PR as described above, or by forming spacers or the like on sidewalls of the gate line 121.

In addition, the semiconductor layer 150A may be exposed to the outside of the storage electrode lines 131 and 133 because of the difference in length and width of the semiconductor layer 150 and the storage electrode lines 131 and 133. These regions are also doped, adjacent to the sustain electrode region 157 and separated from the drain region 155.

As shown in FIGS. 15A and 15B, an interlayer insulating layer 160 is formed of an insulating material on the entire surface of the substrate on which the source region 153, the drain region 155, and the channel region 154 are formed. The interlayer insulating layer 160 is an organic material having excellent planarization characteristics and a photosensitive property, a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or inorganic material formed by plasma chemical vapor deposition. It may be formed of silicon nitride or the like.

Thereafter, the first contact hole 161 exposing the source region 153, the second contact hole 162 exposing the drain region 155, and the data metal piece 171a are exposed on the interlayer insulating layer 160. The third contact hole 163 and the fourth contact hole 164 exposing one end of the data metal piece 171a are formed.

When the interlayer insulating film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

As shown in FIGS. 10 and 11, a conductive layer is formed of a transparent conductive material on the interlayer insulating layer 160 including the first to fourth contact holes 161 to 164, and then patterned to form a data connection part 171b. And the pixel electrode 190 and the contact assistant member 82.

The data metal piece 171a is connected to the data connector 171b through the third contact hole 163, and the data connector 171b is connected to the source region 153 through the first contact hole 161. The pixel electrode 190 is connected to the drain region 155 through the second contact hole 162, and the contact auxiliary member 82 is connected to the data metal piece 171a through the fourth contact hole 164. .

In this case, when the interlayer insulating layer 160 is formed of an organic material having a low dielectric constant, the pixel electrode 190 may overlap the gate line 121 and the data metal piece 171b to improve the aperture ratio of the pixel region.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the length of the slit is different, the amorphous silicon can be crystallized even when misalignment occurs during the movement of the photomask, thereby improving the characteristics of the thin film transistor, thereby improving the reliability of the thin film transistor.

1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II 'of FIG. 1,

3A, 6A, 8A, and 9A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a first exemplary embodiment of the present invention.

3B is a cross-sectional view taken along the line IIIb-IIIb ′ of FIG. 3A;

4 and 5 are views showing the crystallization using the photomask pattern according to the present invention,

FIG. 6B is a cross-sectional view taken along the line VIb-VIb ′ of FIG. 6A;

7 is a cross-sectional view at the next step of FIG. 6B,

FIG. 8B is a cross-sectional view taken along the line VIIIb-VIIIb ′ of FIG. 8A;

FIG. 9B is a cross-sectional view taken along the line IXb-IXb ′ of FIG. 9A;

10 is a layout view of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line XI-XI′-XI ″ of FIG. 10;

12A, 13A, and 15A are layout views in an intermediate step of manufacturing a thin film transistor array panel according to a second exemplary embodiment of the present invention.

12B is a cross-sectional view taken along the line XIIb-XIIb′-XIIb ″ of FIG. 12A, and

13B is a cross-sectional view taken along the line XIIIb-XIIIb'-XIIIb "of 13a,

14 is a sectional view at the next step of FIG. 13B,

15B is a cross-sectional view taken along the line XVb-XVb'-XVb "of FIG. 15A.

※ Explanation of symbols on main parts of drawing ※

110: insulated substrate 121: gate line

124: gate electrode 131: sustain electrode line

133 sustain electrode 140 gate insulating film

150: semiconductor layer 153: source region

154: channel region 155: drain region

171: data line 173: source electrode

175: drain electrode 190: pixel electrode

Claims (9)

A crystallization photomask for locally irradiating a laser beam in a crystallization process of crystallizing amorphous silicon, The photomask includes one or more slit regions in which slits defining a light transmitting region through which the laser beam is transmitted are constantly arranged. The slit is formed to be inclined at a predetermined angle with respect to the movement direction of the mask in the crystallization process, And the slit region includes a first portion having a first length and a second portion having a second length longer than the first length. In claim 1, And the second length is longer than the first length by an alignment error range of the mask. In claim 1, And a slit of the other slit region, wherein the slits of the other slit region are arranged to be offset. Forming an amorphous silicon film on the insulating substrate, Irradiating and moving the laser to the amorphous silicon film through an optical mask including a first part having a slit of a first length and a second part having a slit of a second length in the amorphous silicon film. Forming a polycrystalline silicon film, Patterning the polycrystalline silicon film to form a semiconductor layer, Forming a gate insulating film to cover the semiconductor layer; Forming a gate line partially overlapping the semiconductor layer on the gate insulating layer; Forming a source region and a drain region by highly doping conductive type impurities in a predetermined region of the semiconductor layer, Forming a first interlayer insulating film to cover the gate line and the semiconductor layer; Forming a data line having a source electrode connected to the source region and a drain electrode connected to the drain region on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line and the drain electrode; And forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer. Forming an amorphous silicon film on the insulating substrate, Irradiating and moving the laser to the amorphous silicon film through an optical mask including a first part having a slit of a first length and a second part having a slit of a second length in the amorphous silicon film. Forming a polycrystalline silicon film, Patterning the polycrystalline silicon film to form a semiconductor layer, Forming a gate insulating film to cover the semiconductor layer; Forming a gate line and a data metal piece on which the semiconductor layer partially overlaps with the gate insulating film; Forming a source region and a drain region by highly doping conductive type impurities in a predetermined region of the semiconductor layer, Forming an interlayer insulating film to cover the semiconductor layer; Forming a data connection part connected to the source region and the data metal piece and a pixel electrode connected to the drain area on the interlayer insulating layer. The method of claim 4 or 5, And doping a conductive dopant at a lower concentration than the source and drain regions to form a low concentration doped region in the semiconductor layer. The method of claim 4 or 5, And forming a blocking film between the insulating substrate and the semiconductor layer. The method of claim 4 or 5, And the slits are arranged to be inclined at a predetermined angle with respect to the moving direction of the photomask. The method of claim 4 or 5, The photomask has a first region and a second region having the first portion and the second portion, And the slits of the first region and the second region are arranged to be offset.