KR20050058118A - Semiconductor devices having shoulder patterns and fabrication methods thereof - Google Patents

Abstract

Provided are semiconductor devices having shoulder patterns and methods of manufacturing the same. These devices and manufacturing methods provide a way to electrically insulate the plug pattern and the wiring patterns by placing the plug pattern between two adjacent wiring patterns whose sidewalls facing each other are covered with shoulder patterns. To this end, the devices and methods of manufacturing the same include two adjacent wiring patterns disposed on the semiconductor substrate. Each of the wiring patterns is formed of a wiring film pattern and a wiring capping film pattern that are sequentially stacked. Wiring spacers are formed on sidewalls of the wiring patterns, respectively, and the wiring spacers are covered with a buried insulating film. A partial etching process is performed on the wiring spacers together with the buried insulating layer and the wiring patterns to expose the wiring capping layer pattern. At this time, the etching process forms wiring spacer patterns and shoulder patterns on sidewalls of the wiring patterns, together with buried insulation patterns on sides of the wiring patterns. The shoulder patterns are located on sidewalls of the wiring patterns facing each other. The buried insulation layer pattern between the wiring patterns is removed, and a plug pattern is disposed between the wiring patterns. As a result, the semiconductor device having the shoulder patterns may increase process freedom by removing an electrical short circuit through the shoulder pattern between the wiring patterns and the plug pattern.

Description

Semiconductor devices having shoulder patterns and fabrication methods therefor {Semiconductor Devices Having Shoulder Patterns And Fabrication Methods Thereof}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices and methods of manufacturing the same, and more particularly, to semiconductor devices having shoulder patterns and methods of manufacturing the same.

In general, the semiconductor device may include two adjacent wiring patterns and a plug pattern disposed between the patterns. The wiring patterns may be gate patterns, bit line patterns, metal layer patterns, and the like, and the plug pattern may be a node electrically connected to individual devices. In this case, the wiring pattern and the plug pattern may be formed on the semiconductor substrate with a spacer pattern or a spacer pattern and a buried insulating film pattern interposed therebetween. Through this, the wiring pattern is electrically insulated from the plug pattern through the spacer pattern or the spacer pattern and the buried insulation pattern.

However, the wiring patterns have a structure in which the width between the patterns becomes narrower as the design rule of the semiconductor device is reduced, thus making it difficult to fill the plug pattern without voids. The void due to the plug pattern may be removed by the profile of the spacer patterns formed on the sidewalls of the wiring patterns. However, the semiconductor manufacturing process from forming the spacer patterns to forming the adjacent plug pattern may be performed by the thickness of the spacer patterns. It is possible to increase the leakage current between the wiring pattern and the plug pattern by reducing the voltage.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide semiconductor devices having shoulder patterns suitable for electrically insulating two adjacent wiring patterns on a semiconductor substrate and a plug pattern disposed between the patterns.

Another object of the present invention is to provide methods for manufacturing semiconductor devices having shoulder patterns capable of preventing an electrical short circuit between two adjacent wiring patterns on the top of the semiconductor substrate and a plug pattern disposed between the patterns. have.

An embodiment of the present invention provides a semiconductor device having shoulder patterns.

The device includes two adjacent wiring patterns disposed on top of a semiconductor substrate. The wiring patterns include a wiring film pattern and a wiring capping film pattern that are sequentially stacked. Shoulder patterns are disposed on sidewalls facing each other between the wiring patterns, and wiring spacer patterns are disposed on the remaining sidewalls of the wiring patterns, respectively. A plug pattern in contact with shoulder patterns is positioned between the wiring patterns. At this time, the wiring spacer patterns have upper surfaces thereof with flat surfaces along with the lower sides. In addition, the shoulder patterns have the same thickness as the wiring spacer patterns positioned on opposite sides of the wiring patterns on the extension lines connecting the upper surfaces of the wiring film patterns.

An embodiment of the present invention provides a method of manufacturing a semiconductor device having shoulder patterns.

This manufacturing method includes forming two wiring patterns adjacent to an upper portion of a semiconductor substrate, and forming wiring spacers on sidewalls of the patterns, respectively. Each of the wiring patterns is formed of a wiring film pattern and a wiring capping film pattern which are sequentially stacked. A buried insulating film is formed on the semiconductor substrate having the wiring spacers, and a partial etching process is performed on the wiring spacers together with the buried insulating film and the wiring patterns. In this case, the etching process exposes the wiring capping layer pattern to form buried insulating layer patterns on sides of the wiring patterns, and simultaneously forms wiring spacer patterns and shoulder patterns on sidewalls of the wiring patterns. The shoulder patterns are located on sidewalls of the wiring patterns that face each other. Subsequently, the buried insulating film pattern between the wiring patterns is removed from the semiconductor substrate, and a plug pattern filling the wiring patterns is formed. The plug pattern is in contact with shoulder patterns and electrically insulated from the wiring film patterns.

1 is a layout view of a semiconductor device according to the present invention, and FIG. 2 is a cross-sectional view of the semiconductor device taken along the line II ′ of FIG. 1.

1 to 2, a semiconductor substrate having an active region 15 is covered with a dielectric film 20, and two wiring patterns 60 adjacent to the dielectric film 20 are disposed. The shoulder patterns 74 and the wiring spacer patterns 72 are respectively covered on sidewalls facing each other of the wiring patterns 60 and the remaining sidewalls of the patterns 60. The dielectric film 20 is an insulating film formed through a thermal oxidation process, and each of the wiring patterns 60 is a wiring film pattern 35 and a wiring capping film pattern 45 that are sequentially stacked. The interconnection film pattern 35 is preferably a doped polysilicon film or a doped polysilicon film and a metal silicide film sequentially stacked. The wiring capping layer pattern 45 may be a nitride layer, and the shoulder patterns 74 and the wiring spacer patterns 72 may be insulating layers having the same etching rate as the wiring capping layer pattern 45.

A buried insulation layer pattern 83 is disposed on sides of the wiring patterns 45 covered with the wiring spacer patterns 72, and a plug pattern 115 is positioned between the wiring patterns 45. At this time, the plug pattern 115 is electrically insulated from the wiring film patterns 35 due to the shoulder patterns 74 and the wiring capping film patterns 45. In addition, the wiring spacer patterns 72 may have upper surfaces of the patterns 72 having flat surfaces together with lower surfaces thereof, and the shoulder patterns 74 contacting the plug pattern 115 may have a wiring pattern ( It has the same thickness as the wiring spacer patterns 72 on the opposite side with the wiring patterns 45 therebetween on the extension line connecting the upper surfaces of the 35. The buried insulating layer pattern 83 is an insulating layer having an etching rate different from that of the wiring spacer patterns 72, and the plug pattern 115 is a doped polysilicon layer.

Now, the manufacturing method of the present invention will be described in more detail with reference to the accompanying drawings.

3 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device, taken along the line II ′ of FIG. 1.

1 to 3 to 11, a dielectric film 20 is formed on a semiconductor substrate having an active region 15, and a wiring film 30 and a wiring capping film 40 are formed on the dielectric film 20. Form in turn. Two adjacent photoresist patterns 50 are formed on the wiring capping layer 40 and run parallel to the upper portion of the active region 15, and the photoresist patterns 50 and the dielectric layer 20 are etched. Using the mask as a mask, the etching process is sequentially performed on the wiring capping film 40 and the wiring film 30 to form the wiring patterns 60. Each of the wiring patterns 60 is formed of a wiring film pattern 35 and a wiring capping film pattern 45. The wiring capping film 40 may be formed of a nitride film, and the dielectric film 20 may be formed of an insulating film having an etching rate different from that of the wiring capping film 40. The wiring film 30 is preferably formed of a doped polysilicon film or a doped polysilicon film and a metal silicide film sequentially stacked. In addition, the wiring film 30 may be formed of a metal film having a high temperature melting point.

Wiring spacers 70 are formed on sidewalls of the wiring patterns 60, and a buried insulating layer 80 covering the wiring spacers 70 and the wiring patterns 60 is formed. A planarization process is performed on a semiconductor substrate having the buried insulating film 80. The planarization process partially etches the wiring spacers 70 together with the buried insulating layer 80 and the wiring patterns 60 to expose the wiring layer patterns 35. At this time, the planarization process forms buried insulating film patterns 83 on the side portions of the wiring patterns 60 and simultaneously forms shoulder patterns 74 and wiring spacer patterns 72 on sidewalls of the wiring patterns 60. do. The shoulder patterns 74 are formed on sidewalls facing each other of the wiring patterns 60. The shoulder and wiring spacer patterns 74, 72 have upper surfaces A with flat surfaces with the lower sides B, and the upper sides A of the patterns 74, 72 have a lower side. It is preferable to form in width smaller than (B). The buried insulating film 80 may be formed of an insulating film having an etching rate different from that of the wiring capping film pattern 45. A photoresist film 90 is formed on the semiconductor substrate having the shoulder patterns 74 and the wiring spacer patterns 72 as shown in FIG. 7.

The reason for having flat surfaces on the upper sides A of the shoulder and wiring spacer patterns 72 and 74 will be described in more detail below. After the planarization process is performed on the buried insulating film 80 so that the upper surface of the wiring capping layer pattern 45 of FIG. 6 is exposed, the resultant shown in FIG. 8 may be obtained by applying the photoresist film 90. The planarization process forms buried insulating film patterns 86 on sides of the wiring patterns 60, and the buried insulating film pattern 86 has a thickness from the upper surface of the semiconductor substrate 10 to the top thereof. Thicker than (83). The photoresist film 91 has a pattern hole 92 exposing the buried insulating film pattern 86 between the wiring patterns 60. That is, the pattern hole 92 is disposed between the wiring patterns 60 to overlap the wiring patterns 60. An etching process 94 is performed on the buried insulating film pattern 86 through the pattern hole 92 by using the photoresist film 91 as an etching mask. The etching process 94 forms a polymer by reacting process gases with the wiring capping layer patterns 45 and the wiring spacers 70 in the pattern hole 92 together with the photoresist layer 91 to form a buried material. The insulating film pattern 86 is etched.

However, the etching process 94 has a low polymer production rate due to the small amount of material of the wiring capping film patterns 45 and the wiring spacers 70 in the pattern hole 92 that will react with the process gases at the beginning of the process 94. Has Accordingly, the upper caps D and F of the wiring capping layer patterns 45 and the wiring spacers 70 in the pattern hole 92 may not be partially protected by a polymer, and the buried insulating layer pattern 86 and the dielectric layer ( 20) together, the semiconductor substrate 10 is removed in a direction 96 toward the upper surface of the semiconductor substrate 10. As a result, the etching process 94 deforms the wiring spacers 70 covering the sidewalls between the wiring patterns 60 into spacer patterns 76, and at the same time, the wiring capping film pattern together with the spacer patterns 76. The removed portion of the 45 forms a plug hole 98 with a dotted line trajectory.

In addition, the thickness E of the spacer patterns 76 of FIG. 8 may be equal to the thickness C of the opposite wiring spacers 70 with the wiring patterns 60 therebetween on the extension line connecting the upper surfaces of the wiring film patterns 35. different. This is a structure vulnerable to electrically insulating the conductive film pattern and the wiring film patterns 35 using the spacer patterns 76 when the conductive film pattern (not shown in the figure) is disposed between the wiring patterns 60. Indicates. The fragile structure causes leakage current to flow through the patterns 76 while the semiconductor device having the spacer patterns 76 is driven so that the wiring film patterns 35 and the conductive film patterns are electrically shorted.

As a remedy for this, a pattern contact hole 100 is formed in the film 90 by using a known photo process on the semiconductor substrate having the photoresist film 90 in FIG. The pattern contact hole 100 is disposed between the wiring patterns 60 and at the same time overlaps the wiring patterns 60 to form the wiring capping layer patterns 45 and the shoulder patterns 74 in the contact hole 100. In addition, the buried insulating film pattern 83 is exposed. An etching process 102 is performed on the buried insulating film pattern 83 through the pattern contact hole 100 by using the photoresist film 90 as an etching mask, and the etching process 102 includes the wiring capping film pattern 45. ) And the buried insulating film pattern 83 between the wiring patterns 60 together with a portion of the upper sides G and H of the shoulder patterns 74 in the direction 104 toward the upper surface of the semiconductor substrate 10. Remove The removed amounts of the portions of the upper sides G and H of the wiring capping layer patterns 45 and the shoulder patterns 74 may be the upper sides D and F of the wiring capping layer patterns and the wiring spacers of FIG. 8. It is less than a part of). This is because the etching process 102 has a material amount of the wiring capping layer patterns 45 and the shoulder patterns 74 in the pattern contact hole 100 that will react with the process gases at the beginning of the process 102. This is because it is larger than the inside of the pattern hole 92 and has a high polymer production rate. This is because the polymer generated during the removal of the buried insulating layer pattern 83 through the etching process 102 protects the upper surfaces of the wiring capping layer patterns 45 and the sidewalls of the shoulder patterns 74 in comparison with FIG. 8. to be. Accordingly, the etching process 102 removes the buried insulating film pattern 83 and the dielectric film 20 between the wiring patterns 60 to form a plug contact hole 106 having a dotted line trajectory.

The plug film 110 is formed on the semiconductor substrate having the plug contact hole 106, and the wiring capping film patterns 45 and the shoulder pattern 74 are etch stoppers, and the plug film 110 is planarized. The process is performed to form the plug pattern 115. The plug pattern 115 fills the wiring patterns 60. In addition, the shoulder patterns 74 in contact with the plug pattern 115 may be formed on the opposite side of the wiring spacer patterns 72 on the extension line connecting the upper surfaces of the wiring layer patterns 35 with the wiring patterns 60 therebetween. Maintain the same thickness J. Accordingly, the plug pattern 115 is electrically insulated from the wiring film patterns 35 by the wiring capping film patterns 45 and the shoulder patterns 74 than in FIG. 8.

As described above, the present invention includes a plug pattern between the shoulder patterns and the wiring patterns on sidewalls facing each other between two adjacent wiring patterns to prevent electrical shorting of the wiring patterns and the plug pattern. Through this, the semiconductor device having the shoulder pattern can be secured from the semiconductor substrate with high yield.

1 is a layout view of a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device taken along the line II ′ of FIG. 1. FIG.

3 through 11 are cross-sectional views illustrating a method of manufacturing a semiconductor device, taken along the line II ′ of FIG. 1.

Claims (12)

Disposed on the semiconductor substrate, each of which includes two adjacent wiring patterns in which a wiring film pattern and a wiring capping film pattern are sequentially stacked; Shoulder patterns and wiring spacer patterns disposed on the sidewalls facing each other between the wiring patterns and the remaining sidewalls of the patterns, respectively; A plug pattern positioned between the wiring patterns and contacting the shoulder patterns, The wiring spacer patterns have flat surfaces at their upper sides along with the lower sides, and the shoulder patterns have the same thickness as the wiring spacer patterns positioned opposite to each other on the extension lines connecting the upper surfaces of the wiring film patterns. A semiconductor device characterized by having. The method of claim 1, And wherein the wiring film is a doped polysilicon film and a metal silicide film which are sequentially stacked. The method of claim 1, And the wiring capping film pattern is a nitride film. The method of claim 1, And the shoulder patterns and the wiring spacer patterns are insulating layers having the same etching rate as that of the wiring capping layer pattern. The method of claim 1, And the plug pattern is a conductive layer having an etching rate different from that of the shoulder patterns. Forming two adjacent wiring patterns of a wiring film pattern and a wiring capping film pattern, which are sequentially stacked on the semiconductor substrate, Wiring spacers are formed on sidewalls of the wiring patterns, Forming a buried insulating film covering the wiring spacers, A partial etching process is performed on the wiring spacers together with the buried insulation layer and the wiring patterns to expose the wiring layer capping layer pattern, wherein the etching process is performed along with the buried insulation layer patterns on the sides of the wiring patterns. Forming wiring spacer patterns and shoulder patterns on sidewalls of the wiring patterns, Removing the buried insulating film pattern between the wiring patterns from the semiconductor substrate, It is disposed between the wiring patterns to form a plug pattern to fill therebetween, And the shoulder patterns are formed on sidewalls of wiring patterns that face each other, and the plug pattern is in contact with the shoulder patterns to electrically insulate the wiring film patterns. The method of claim 6, And wherein the wiring film pattern is formed of a doped polysilicon film and a metal silicide film that are sequentially stacked. The method of claim 6, And the wiring capping film pattern is formed of a nitride film. The method of claim 6, And the shoulder patterns and the wiring spacer patterns are formed of an insulating layer having the same etching rate as that of the wiring spacers. The method of claim 6, And said plug pattern is a doped polysilicon film. The method of claim 6, And the buried insulation film is formed of an insulation film having an etching rate different from that of the shoulder patterns. The method of claim 6, And the etching process flattens the upper portion of the semiconductor substrate having the buried insulating film.