KR20050045392A - Method of forming metal line in semiconductor devices - Google Patents
Method of forming metal line in semiconductor devices Download PDFInfo
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- KR20050045392A KR20050045392A KR1020030079444A KR20030079444A KR20050045392A KR 20050045392 A KR20050045392 A KR 20050045392A KR 1020030079444 A KR1020030079444 A KR 1020030079444A KR 20030079444 A KR20030079444 A KR 20030079444A KR 20050045392 A KR20050045392 A KR 20050045392A
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- film
- insulating film
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- 238000000034 method Methods 0.000 title claims abstract description 51
- 239000002184 metal Substances 0.000 title claims abstract description 39
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 39
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 239000007769 metal material Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 32
- 239000010949 copper Substances 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000007789 gas Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910008486 TiSix Inorganic materials 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000001465 metallisation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- -1 that is Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체소자의 금속배선 형성방법에 관한 것으로, 본 발명의 사상은 하부 구조가 형성된 반도체 기판에 제1 절연막, 식각 정지막 및 제2 절연막을 순차적으로 형성하는 단계, 상기 형성된 결과물의 제2 절연막, 식각 정지막 및 제1 절연막을 패터닝하여 서로 상이한 지점에서 상기 하부구조가 노출되는 다수의 비아홀을 형성하고, 상기 형성된 결과물의 제2 절연막 및 식각 정지막을 재패터닝하여 상기 다수의 비아홀의 상부에 각각에 대응하여 다수의 트렌치 패턴을 형성하는 단계, 상기 형성된 다수의 비아홀 및 트렌치 패턴에 금속물질을 매립하여 다수의 비아 및 트렌치를 형성하는 단계, 상기 제2 절연막을 제거하는 공정을 수행하는 단계 및 상기 제거된 제2 절연막을 포함한 결과물 전면에 제3 절연막을 형성하는 단계를 포함한다. The present invention relates to a method for forming a metal wiring of a semiconductor device, and the idea of the present invention is to sequentially form a first insulating film, an etch stop film and a second insulating film on a semiconductor substrate having a lower structure, the second resultant Patterning an insulating film, an etch stop film, and a first insulating film to form a plurality of via holes through which the substructure is exposed at different points, and re-patterning the resultant second insulating film and the etch stop film to form an upper portion of the plurality of via holes. Forming a plurality of trench patterns in correspondence with each other, embedding a metal material in the formed plurality of via holes and trench patterns, forming a plurality of vias and trenches, and removing the second insulating layer; And forming a third insulating film on the entire surface of the resultant including the removed second insulating film.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 더욱 상세하게는 다마신 공정을 통해 형성하는 반도체 소자의 금속배선 형성방법에 관한 것이다. The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device formed through a damascene process.
최근 다마신 공정을 통한 금속배선 형성 공정은 반도체 소자의 고집적화로 인해 금속배선 대비 절연막의 확보가 어려워짐에 따라 금속배선간의 단락 즉, 크로스 토크(crosstalk)의 발생을 증가시키게 된다. 다시 말해, 트렌치 패턴 형성을 통한 금속배선 형성 공정시 동일 피치(pitch)에서 금속배선 대비 일정 비율 이상의 절연막 형성 확보가 중요하지만, 기존 사진식각 공정, 금속물질 매립 전 수행하는 세정 공정 및 금속물질 매립 후 수행하는 평탄화 공정 등의 공정을 통해, 절연막이 과하게 제거되어, 원하는 절연막의 폭보다 더 좁아지게 된다.Recently, the metallization process through the damascene process increases the short circuit between the metallization lines, that is, the occurrence of crosstalk, as it is difficult to secure an insulating film relative to the metallization due to the high integration of semiconductor devices. In other words, during the formation of the metal wiring through the formation of the trench pattern, it is important to secure the formation of an insulating film more than a certain ratio with the metal wiring at the same pitch. Through a process such as a planarization process to be performed, the insulating film is excessively removed, so that it becomes narrower than the width of the desired insulating film.
따라서 이와 같은 구조로 형성된 절연막에 의해 정의되는 트렌치 패턴에는 금속물질이 매립되어 금속배선을 형성하게 되는 데, 이 금속배선은 이웃한 금속배선간과 간격이 좁아지게 되어, 금속배선 상호 간의 교란 즉, 크로스 토크(crosstalk)의 발생이 빈번하게 되어, 금속배선의 신뢰성을 저하시키는 문제점이 있다. Therefore, in the trench pattern defined by the insulating layer formed in such a structure, a metal material is embedded to form a metal wiring. The metal wiring has a narrow gap between neighboring metal wirings. There is a problem that the occurrence of torque (crosstalk) is frequent, which lowers the reliability of the metal wiring.
상술한 문제점을 해결하기 위한 본 발명의 목적은 반도체 소자의 고집적화로 인해 발생되는 금속배선의 신뢰성 저하를 방지할 수 있는 반도체 소자의 금속배선 형성방법을 제공함에 있다. An object of the present invention for solving the above problems is to provide a method for forming a metal wiring of the semiconductor device that can prevent the degradation of the reliability of the metal wiring caused by the high integration of the semiconductor device.
상술한 목적을 달성하기 위한 본 발명의 사상은 하부 구조가 형성된 반도체 기판에 제1 절연막, 식각 정지막 및 제2 절연막을 순차적으로 형성하는 단계, 상기 형성된 결과물의 제2 절연막, 식각 정지막 및 제1 절연막을 패터닝하여 서로 상이한 지점에서 상기 하부구조가 노출되는 다수의 비아홀을 형성하고, 상기 형성된 결과물의 제2 절연막 및 식각 정지막을 재패터닝하여 상기 다수의 비아홀의 상부에 각각에 대응하여 다수의 트렌치 패턴을 형성하는 단계, 상기 형성된 다수의 비아홀 및 트렌치 패턴에 금속물질을 매립하여 다수의 비아 및 트렌치를 형성하는 단계, 상기 제2 절연막을 제거하는 공정을 수행하는 단계 및 상기 제거된 제2 절연막을 포함한 결과물 전면에 제3 절연막을 형성하는 단계를 포함한다. The idea of the present invention for achieving the above object is to sequentially form a first insulating film, an etch stop film and a second insulating film on a semiconductor substrate having a lower structure, the second insulating film, an etch stop film and the resultant Patterning the insulating film to form a plurality of via holes through which the substructures are exposed at different points; and re-patterning the second insulating film and the etch stop layer of the formed resultant to form a plurality of trenches corresponding to the upper portions of the plurality of via holes, respectively. Forming a pattern, embedding a metal material in the formed plurality of via holes and trench patterns, forming a plurality of vias and trenches, performing a process of removing the second insulating film, and removing the second insulating film Forming a third insulating film on the entire surface of the resulting product.
상기 제2 절연막을 제거하는 공정은 상기 형성된 트렌치의 폭 및 두께를 줄어들게 함과 동시에 상기 식각 정지막의 두께 또한 감소시키기 위해 수행하는 것이 바람직하다. The removing of the second insulating layer may be performed to reduce the width and thickness of the formed trench and to reduce the thickness of the etch stop layer.
상기 제2 절연막을 제거하는 공정은 웨트 딥(t dip)공정과 건식식각공정 중 어느 하나를 수행하는 것이 바람직하다. The removing of the second insulating layer may be performed by any one of a wet dip process and a dry etching process.
상기 웨트 딥 공정은 BOE(20: 1~ 300: 1), HF(50: 1~ 100: 1 ) 및 BOE와 HF의 혼합액 중 어느 하나를 사용하여 상기 의 단독 사용 의 단독 사용하거나 두 가지의 혼합 용액을 사용하여 상기 제2 절연막을 제거한 후 상기 트렌치에 매립된 금속물질을 일정 두께 감소시키는 적합한 식각액을 사용하는 것이 바람직하다. The wet dip process may be performed alone or in combination of the above, using any one of BOE (20: 1 to 300: 1), HF (50: 1 to 100: 1), and a mixture of BOE and HF. It is preferable to use a suitable etchant that removes the second insulating film using a solution and then reduces the thickness of the metal material embedded in the trench.
상기 건식 식각공정은 C5F8+O2/CF4+CH2F2 /CHF3+O2의 조합으로 상기 제2 절연막을 제거한 후 상기 트렌치에 매립된 금속물질을 일정 두께 감소시키는 적합한 식각가스를 사용하는 것이 바람직하다.The dry etching process is suitable for reducing the thickness of the metal material embedded in the trench after removing the second insulating film by a combination of C 5 F 8 + O 2 / CF 4 + CH 2 F 2 / CHF 3 + O 2 . Preference is given to using gases.
상기 제1 절연막은 SiO2, BPSG막, PSG막, FSG막, PE-TEOS막, PE-SiH4막, HDP USG막, HDP PSG막, APL 산화막 중 어느 하나인 것이 바람직하다.The first insulating film is preferably any one of SiO 2 , BPSG film, PSG film, FSG film, PE-TEOS film, PE-SiH 4 film, HDP USG film, HDP PSG film, and APL oxide film.
상기 제2 절연막은 실리콘 질화막(SiN), SiON막 중 어느 하나인 것이 바람직하다. The second insulating film is preferably any one of a silicon nitride film (SiN) and a SiON film.
상기 제3 절연막은 3이하의 k를 가지는 유전막질로 형성하는 것이 바람직하다. The third insulating film is preferably formed of a dielectric film having a k of 3 or less.
이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명한다. 그러나, 본 발명의 실시예들은 여러 가지 다른 형태로 변형될 수 있지만 본 발명의 범위가 아래에서 상술하는 실시예들로 인해 한정되어지는 것으로 해석되어져서는 안 된다. 본 발명의 실시예들은 당업계에서 평균적인 지식을 가진 자에게 본 발명을 보다 완전하게 설명하기 위해 제공되어지는 것이다. 따라서 도면에서의 막의 두께 등은 보다 명확한 설명을 강조하기 위해서 과장되어진 것이며, 도면상에서 동일한 부호로 표시된 요소는 동일한 요소를 의미한다. 또한 어떤 막이 다른 막 또는 반도체 기판의 '상'에 있다 또는 접촉하고 있다 라고 기재되는 경우에, 상기 어떤 막은 상기 다른 막 또는 반도체 기판에 직접 접촉하여 존재할 수 있고, 또는 그 사이에 제 3의 막이 개재되어질 수도 있다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. Therefore, the thickness of the film and the like in the drawings are exaggerated to emphasize a more clear description, the elements denoted by the same reference numerals in the drawings means the same elements. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.
도 1 내지 도 5는 본 발명의 바람직한 실시예인 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이다. 1 to 5 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention.
도 1을 참조하면, 트랜지스터와 같은 하부구조를 가진 반도체 기판(10) 상에 제1 절연막(12), 식각 정지막(14), 희생 산화막(16)을 순차적으로 형성한다. 상기 희생 산화막(16)은 실리콘 산화막(SiO2), BPSG막, PSG막, FSG막, PE-TEOS막, PE-SiH4막, HDP USG막, HDP PSG막, APL 산화막과 같은 산화막으로, 2000~ 4000Å정도의 두께로 형성하고, 상기 식각 정지막(14)은 실리콘 질화막(SiN), SiON막과 같은 질화막으로, 300~ 1000Å정도의 두께로 형성한다. 상기 희생 산화막(16)은 이후 공정을 통해 제거되는 막질이기 때문에 이 막의 제거가 용이한 막질을 사용하는 것이 바람직하다.Referring to FIG. 1, a first insulating layer 12, an etch stop layer 14, and a sacrificial oxide layer 16 are sequentially formed on a semiconductor substrate 10 having a substructure such as a transistor. The sacrificial oxide film 16 is an oxide film such as a silicon oxide film (SiO 2 ), a BPSG film, a PSG film, an FSG film, a PE-TEOS film, a PE-SiH 4 film, an HDP USG film, an HDP PSG film, and an APL oxide film. The etch stop layer 14 is formed of a nitride film such as a silicon nitride film (SiN) or a SiON film, and has a thickness of about 300 to 1000 mW. Since the sacrificial oxide film 16 is a film quality removed through a subsequent process, it is preferable to use a film quality in which the film is easily removed.
도 2를 참조하면, 상기 반도체 기판(미도시)에 형성된 하부 구조가 노출되도록 하기 위해 듀얼 다마신 공정을 수행하여, 비아홀(VH) 및 트렌치 패턴(TP)을 형성한다. 즉, 상기 반도체 기판(미도시)에 형성된 희생 산화막(16) 상부에 비아홀을 정의할 제1 포토레지스트 패턴(미도시)을 형성하고, 이 포토레지스트 패턴(미도시)을 식각 마스크로 희생 산화막(16), 식각 정지막(14), 제1 절연막(12)까지 식각하여 하부 구조가 노출되도록 비아홀(VH)을 형성하고, 제1 포토레지스트 패턴(미도시)을 제거한다. 상기 형성된 비아홀(VH)이 형성된 결과물의 희생 산화막(16) 상부에 트렌치 패턴을 정의하는 제2 포토레지스트 패턴(미도시)을 형성한 후 이를 식각 마스크로 희생 산화막(16), 식각 정지막(14)까지만 식각하여 트렌치 패턴(TP)을 형성하고, 제2 포토레지스트 패턴(미도시)을 제거한다. Referring to FIG. 2, a dual damascene process is performed to expose a lower structure formed on the semiconductor substrate (not shown) to form a via hole VH and a trench pattern TP. That is, a first photoresist pattern (not shown) defining a via hole is formed on the sacrificial oxide film 16 formed on the semiconductor substrate (not shown), and the photoresist pattern (not shown) is used as an etching mask. 16), the via hole VH is formed to be etched to the etch stop layer 14 and the first insulating layer 12 to expose the underlying structure, and the first photoresist pattern (not shown) is removed. A second photoresist pattern (not shown) defining a trench pattern is formed on the sacrificial oxide layer 16 of the resultant formed via hole VH. The sacrificial oxide layer 16 and the etch stop layer 14 are formed using an etching mask. To form a trench pattern TP and to remove the second photoresist pattern (not shown).
도 3을 참조하면, 상기 비아홀(VH) 및 트렌치 패턴(TP)을 포함한 반도체 기판 전면에 확산 방지막(미도시) 및 구리 시드층과 같은 금속 시드층(미도시)을 순차적으로 형성한 후 전기 도금 공정을 통해 구리층과 같은 금속층(미도시)을 형성한다. 이 형성된 금속층(미도시)에 희생 산화막(16)이 노출될 때까지 평탄화 공정을 수행하여 비아홀(VH) 및 트렌치 패턴(TP) 내부에만 금속층(22)이 매립되도록 함으로써 비아(V) 및 제1 트렌치(T1)의 형성을 완료한다. 상기 금속층은 구리(Cu) 이외에 W, TiSix, TiN, Al과 같은 금속을 사용할 수 있다. Referring to FIG. 3, electroplating is performed after sequentially forming a metal seed layer (not shown) such as a diffusion barrier layer (not shown) and a copper seed layer on an entire surface of the semiconductor substrate including the via hole (VH) and the trench pattern (TP). The process forms a metal layer (not shown) such as a copper layer. The planarization process is performed until the sacrificial oxide layer 16 is exposed to the formed metal layer (not shown) so that the metal layer 22 is embedded only in the via hole VH and the trench pattern TP, thereby forming the via V and the first layer. The formation of the trench T1 is completed. The metal layer may use a metal such as W, TiSix, TiN, and Al in addition to copper (Cu).
도 4를 참조하면, 상기 비아(V) 및 제1 트렌치(T1)의 형성 완료한 후 웨트 딥(Wet dip)공정 또는 건식식각공정을 수행한다. 이 공정을 통해 희생 산화막(16)이 제거되면서 동시에 제1 트렌치(T1)의 표면과 측면이 다소 제거되어 제2 트렌치(T2)를 형성하게 된다. Referring to FIG. 4, after the formation of the vias V and the first trenches T1 is completed, a wet dip process or a dry etching process may be performed. Through this process, the sacrificial oxide layer 16 is removed and at the same time, the surface and side surfaces of the first trenches T1 are somewhat removed to form the second trenches T2.
상기 공정을 통해 제1 트렌치(T1)보다 폭(도 3의 c1)과 두께(도 3의 b1)가 제거되어 형성된 제2 트렌치(T2; 제2 트렌치의 폭은 c1- γ, 두께는 b1- β)를 형성함으로써, 제2 트렌치(T2)와 인접한 제2 트렌치(T2)간의 폭(제1 트렌치간의 폭은 도 3의 a1, 제2 트렌치 간의 폭은 a1+ α)이 증가하게 되어, 트렌치 상호 간의 교란 즉, 크로스 토크(crosstalk)의 발생을 억제할 수 있게 된다. 또한 상기 공정을 통해 식각 정지막(14)의 소정 깊이만 식각(식각 공정이전의 식각 정지막(14)은 도 3의 d1, 식각공정을 통해 소정깊이 제거된 식각 정지막(14)은 d1- δ)되어, 상기 제2 트렌치(T2) 상호간의 교란 즉, 크로스 토크 발생이 억제되는 효과를 더 가지면서 동시에 하부의 제1 절연막(12)에 대해서는 식각되는 것을 방지할 수 있다. 한편, 상기 희생산화막의 제거 및 제2 트렌치의 형성 공정시 상기 식각 정지막(14)은 모두 제거되어도 무방하다. The second trench T2 formed by removing the width (c1 of FIG. 3) and the thickness (b1 of FIG. 3) from the first trench T1 through the above process; the width of the second trench is c1- γ and the thickness is b1-. By forming β), the width between the second trenches T2 and the adjacent second trenches T2 (the width between the first trenches is a1 in FIG. 3 and the width between the second trenches is a1 + α) is increased. The disturbance between them, i.e., the occurrence of crosstalk, can be suppressed. In addition, only the predetermined depth of the etch stop layer 14 is etched through the above process (the etch stop layer 14 before the etching process is shown in FIG. 3 d1, and the etch stop layer 14 removed through the etching process is d1-d1). δ), the second trenches T2 can be prevented from being etched with respect to the first insulating layer 12 at the same time, while having an effect of suppressing the disturbance between the second trenches T2, that is, cross talk. Meanwhile, all of the etch stop layers 14 may be removed during the process of removing the sacrificial oxide layer and forming the second trench.
상기 웨트 딥 공정은 BOE(20: 1~ 300: 1) 또는 HF(50: 1~ 100: 1 )를 단독 사용하거나 두 가지의 혼합 용액을 사용하여 산화막을 제거한 후 트렌치(T1)에 매립된 금속물질을 일정 두께 감소시키기 위한 적합한 식각액을 사용한다. The wet dip process is a metal buried in the trench (T1) after removing the oxide film using BOE (20: 1 ~ 300: 1) or HF (50: 1 ~ 100: 1) alone or using a mixture of the two Use a suitable etchant to reduce the material to a certain thickness.
본 발명의 일 실시예에서는 구리물질을 제거하는 식각액 즉, 20~ 500: 1의 비율로 혼합된 HNO3 또는 H2SO4를 사용한다. 또한, 구리(Cu) 이외의 금속물질 즉, W, TiSix, TiN, Al과 같은 물질이 트렌치에 매립될 때는 그에 적합한 식각액을 사용할 수 있다.In an embodiment of the present invention, an etching solution for removing copper material, that is, HNO 3 or H 2 SO 4 mixed at a ratio of 20 to 500: 1 is used. In addition, when a metal material other than copper (Cu), that is, materials such as W, TiSix, TiN, and Al are embedded in the trench, an etchant suitable for the same may be used.
또한, 상기 건식식각 공정은 C5F8+O2/CF4+CH2F 2/CHF3+O2의 조합으로 산화막을 제거한 후 트렌치(T1)에 매립된 금속물질을 일정 두께 감소시키기 위해 적합한 식각가스를 사용한다.In addition, the dry etching process is to remove the oxide film by a combination of C 5 F 8 + O 2 / CF 4 + CH 2 F 2 / CHF 3 + O 2 to reduce the thickness of the metal material embedded in the trench (T1) to a certain thickness. Use suitable etching gas.
본 발명의 일 실시예에서는 구리 물질을 제거하는 식각가스 즉, F나 Cl기가 포함된 가스를 사용한다. 또한, 구리(Cu) 이외의 금속물질 즉, W, TiSix, TiN, Al과 같은 물질이 트렌치에 매립될 때는 그에 적합한 식각가스를 사용할 수 있다. In an embodiment of the present invention, an etching gas for removing copper material, that is, a gas containing F or Cl groups is used. In addition, when a metal material other than copper (Cu), that is, a material such as W, TiSix, TiN, Al is embedded in the trench, an etching gas suitable for the same may be used.
도 5를 참조하면, 상기 형성된 결과물에 저유전막질로 형성된 제2 절연막(18)을 형성한다. 상기 결과물 전면에 형성되는 제2 절연막(18)은 상기 인접한 제2 트렌치(T2)간을 절연시키는 금속층간절연막(Inter metal dielectric)으로써의 역할을 수행하는 데, 상기 저유전막질(3 이하의 k를 가지는 유전막질)로 형성되는 제2 절연막(18)은 PECVD, APCVD 등의 방식으로 형성하는 것이 바람직하다. 상기 저유전막질로 형성되는 제2 절연막으로 트렌치 간의 층간 절연막을 형성하는 것은 금속배선간의 커패시턴스를 감소시키기 때문이다.Referring to FIG. 5, a second insulating film 18 formed of low dielectric film quality is formed on the resultant. The second insulating film 18 formed on the entire surface of the resultant product serves as an inter metal dielectric to insulate the adjacent second trenches T2. It is preferable that the second insulating film 18 formed of a dielectric film having a thickness of 2) is formed by PECVD, APCVD, or the like. The formation of the interlayer insulating film between trenches with the second insulating film formed of the low dielectric film quality is because the capacitance between metal wirings is reduced.
상기 제2 절연막(18)을 패터닝하여 하부의 제2 트렌치(T2)와 연결되는 콘택홀(미도시)을 형성한 후 금속물질을 매립하여 금속 콘택(미도시)을 형성하는 공정이 추가적으로 더 진행될 수 있다. The process of patterning the second insulating layer 18 to form a contact hole (not shown) connected to the lower second trench T2 and then filling a metal material to form a metal contact (not shown) may be further performed. Can be.
부가적인 설명을 추가하면, 상기 크로스 토크 발생을 억제하기 위해서는 금속 배선 간의 상호간의 폭을 증가시키고, 금속배선의 높이가 낮으면 가능하다. 따라서 상기 희생산화막의 제거로 인해 금속배선의 폭과 두께가 감소하게 된다. 더욱이, 식각 정지막의 제거로 인해 크로스 토크발생을 억제하는 저유전체막질이 이후에 더 형성될 수 있기 때문에 식각 정지막의 제거도 크로스 토크 발생을 억제하는 효과를 가진다. In addition to the additional explanation, in order to suppress the occurrence of the cross talk, it is possible to increase the width between the metal wires and to lower the height of the metal wires. Therefore, the width and thickness of the metal wirings are reduced due to the removal of the sacrificial oxide film. Furthermore, since the low dielectric film quality which suppresses cross talk generation due to the removal of the etch stop film can be further formed later, the removal of the etch stop film also has the effect of suppressing cross talk generation.
본 발명에 의하면, 상기 희생 산화막에 트렌치 패턴을 형성한 후 희생 산화막 제거공정을 수행하여 희생 산화막의 제거뿐만 아니라 금속배선의 소정 폭 및 두께의 식각, 식각 정지막의 소정 두께의 식각으로 인해, 금속배선 간은 넓어진 폭을 갖게 되고, 상기 넓어진 폭을 가진 금속배선 간에 저유전막질을 형성함으로써 이웃한 금속배선간의 상호 간의 교란 즉, 크로스 토크(crosstalk)의 발생을 억제하게 되고, 금속배선의 신뢰성을 향상시킬 수 있게 된다. According to the present invention, after forming a trench pattern in the sacrificial oxide film, the sacrificial oxide film removing process is performed to remove not only the sacrificial oxide film but also the etching of the predetermined width and thickness of the metal wiring and the etching of the predetermined thickness of the etch stop film. The gap has a wider width, and the low dielectric film quality is formed between the wider metal wires, thereby suppressing mutual disturbance, that is, the occurrence of crosstalk, between the adjacent metal wires, and improving the reliability of the metal wires. You can do it.
이상에서 살펴본 바와 같이 본 발명에 의하면, 상기 희생 산화막에 트렌치 패턴을 형성한 후 희생 산화막 제거공정을 수행하여 희생 산화막의 제거뿐만 아니라 금속배선의 소정 폭 및 두께의 식각, 식각 정지막의 소정 두께의 식각으로 인해, 금속배선 간은 넓어진 폭을 갖게 되고, 상기 넓어진 폭을 가진 금속배선 간에 저유전막질을 형성함으로써 이웃한 금속배선간의 상호 간의 교란 즉, 크로스 토크(crosstalk)의 발생을 억제하게 되고, 금속배선의 신뢰성을 향상시킬 수 있게 되는 효과가 있다. As described above, according to the present invention, after forming a trench pattern in the sacrificial oxide film, the sacrificial oxide film removing process is performed to remove not only the sacrificial oxide film, but also the etching of the predetermined width and thickness of the metal wiring and the etching of the predetermined thickness of the etch stop film. As a result, the metal wires have a wider width, and the low dielectric film quality is formed between the metal wires having the wider widths, thereby suppressing the occurrence of crosstalk between adjacent metal wires, that is, crosstalk. There is an effect that can improve the reliability of the wiring.
본 발명은 구체적인 실시 예에 대해서만 상세히 설명하였지만 본 발명의 기술적 사상의 범위 내에서 변형이나 변경할 수 있음은 본 발명이 속하는 분야의 당업자에게는 명백한 것이며, 그러한 변형이나 변경은 본 발명의 특허청구범위에 속한다 할 것이다.Although the present invention has been described in detail only with respect to specific embodiments, it is apparent to those skilled in the art that modifications or changes can be made within the scope of the technical idea of the present invention, and such modifications or changes belong to the claims of the present invention. something to do.
도 1 내지 도 5는 본 발명의 바람직한 실시예인 반도체 소자의 금속배선 형성방법을 설명하기 위한 단면도들이다. 1 to 5 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to an exemplary embodiment of the present invention.
*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *
12: 제1 절연막 14: 식각정지막12: first insulating film 14: etch stop film
16: 희생산화막 V: 비아16: Sacrificial Oxide V: Via
T1: 제1 트렌치 T2: 제2 트렌치T1: first trench T2: second trench
18: 제2 절연막18: second insulating film
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