KR20050038500A - Semiconductor chip having three dimension type ubm for flip chip bonding and mounting structure thereof - Google Patents

Semiconductor chip having three dimension type ubm for flip chip bonding and mounting structure thereof Download PDF

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Publication number
KR20050038500A
KR20050038500A KR1020030073863A KR20030073863A KR20050038500A KR 20050038500 A KR20050038500 A KR 20050038500A KR 1020030073863 A KR1020030073863 A KR 1020030073863A KR 20030073863 A KR20030073863 A KR 20030073863A KR 20050038500 A KR20050038500 A KR 20050038500A
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South Korea
Prior art keywords
metal layer
lower metal
bump
layer
solder
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KR1020030073863A
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Korean (ko)
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KR100659527B1 (en
Inventor
정세영
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삼성전자주식회사
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Priority to KR1020030073863A priority Critical patent/KR100659527B1/en
Priority to US10/911,705 priority patent/US7208842B2/en
Publication of KR20050038500A publication Critical patent/KR20050038500A/en
Application granted granted Critical
Publication of KR100659527B1 publication Critical patent/KR100659527B1/en
Priority to US11/709,800 priority patent/US7338891B2/en

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    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

본 발명은 전극패드에 솔더 범프가 형성된 플립 칩 본딩용 반도체 칩과 그 실장 구조에 관한 것이다. 집적회로가 형성된 반도체 기판과, 집적회로와 연결되어 외부와의 전기적 연결을 위하여 반도체 기판 상에 형성된 전극패드와, 전극패드의 적어도 일부분을 노출시키며 반도체 기판 상에 형성된 패시베이션층과, 전극패드와 접속되어 전극패드 부분 및 그 주변의 패시베이션층에 형성되는 제 1범프 하부 금속층과, 제 1범프 하부 금속층 상에 소정 높이의 링 형태를 가지며 형성된 3차원 범프 하부 금속층과, 제 1범프 하부 금속층 상에 3차원 범프 하부 금속층을 덮으며 형성된 솔더층, 및 폴리머 코어가 내장되어 있으며 그 폴리머 코어가 3차원 범프 하부 금속층에 일정 부분이 삽입된 형태를 갖도록 솔더층 상에 형성된 솔더 범프를 포함하는 것을 특징으로 하는 플립 칩 본딩용 반도체 칩을 제공하고, 그리고 그 반도체 칩이 기판 접촉패드와 그 기판 접촉패드에 3차원 범프 하부 금속층과 대응되는 위치에 소정 높이로 형성되어 솔더 범프의 폴리머 코어를 지지하는 지지층을 갖는 기판을 포함하며, 폴리머 코어가 3차원 범프 하부 금속층과 3차원 패드 상부 금속층 사이에 끼워진 형태로 범프 본딩된 것을 특징으로 하는 실장 구조를 제공함으로써, 솔더 범프 자체의 응력 완충 효과가 크게 향상되어 언더필 물질을 주입하지 않고도 솔더 범프 자체의 접합력이 확보되며 열팽창계수 차이 등에 기인하여 범프에 집중되는 응력이 완화되는 효과를 얻을 수 있다.The present invention relates to a semiconductor chip for flip chip bonding in which solder bumps are formed on an electrode pad and a mounting structure thereof. A semiconductor substrate on which an integrated circuit is formed, an electrode pad formed on the semiconductor substrate connected to the integrated circuit for electrical connection with the outside, a passivation layer formed on the semiconductor substrate to expose at least a portion of the electrode pad, and an electrode pad connected thereto And a three-dimensional bump lower metal layer formed on the electrode pad portion and a passivation layer around the first bump lower metal layer, and having a ring shape having a predetermined height on the first bump lower metal layer. A solder layer formed covering the dimensional bump lower metal layer, and a solder bump formed on the solder layer such that the polymer core is embedded and a portion of the polymer core is inserted into the 3D bump lower metal layer. A semiconductor chip for flip chip bonding is provided, and the semiconductor chip is in contact with a substrate contact pad and the substrate. A pad having a support layer supporting a polymer core of a solder bump formed at a predetermined height at a position corresponding to the 3D bump lower metal layer on the pad, wherein the polymer core is sandwiched between the 3D bump lower metal layer and the 3D pad upper metal layer By providing a mounting structure characterized in that the bump bonding in the form, the stress buffering effect of the solder bump itself is greatly improved to ensure the bonding force of the solder bump itself without injecting the underfill material and concentrate on the bump due to the difference in thermal expansion coefficient The effect of relieving stress can be obtained.

Description

3차원 범프 하부 금속층을 갖는 플립 칩 본딩용 반도체 칩과 그 실장 구조{SEMICONDUCTOR CHIP HAVING THREE DIMENSION TYPE UBM FOR FLIP CHIP BONDING AND MOUNTING STRUCTURE THEREOF}Semiconductor chip for flip chip bonding having three-dimensional bump lower metal layer and its mounting structure {SEMICONDUCTOR CHIP HAVING THREE DIMENSION TYPE UBM FOR FLIP CHIP BONDING AND MOUNTING STRUCTURE THEREOF}

본 발명은 반도체 장치에 관한 것으로 더욱 상세하게는 플립 칩 본딩을 위하여 전극패드에 솔더 범프가 형성된 플립 칩 본딩용 반도체 칩과 그 실장 구조에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a semiconductor chip for flip chip bonding in which solder bumps are formed on an electrode pad for flip chip bonding, and a mounting structure thereof.

반도체 소자(semiconductor device)는 반도체 산업의 발전과 사용자의 고속화와 고집적화에 대한 요구에 따라 점점 더 크기가 감소되고 입출력 핀 수가 증가되고 있다. 이에 따라 반도체 칩 패키지의 구조는 핀 삽입형에서 표면실장형으로 급격히 변화되어 왔으며, 외부접속단자가 면 배열된 볼 그리드 어레이(Ball Grid Array) 패키지와 칩 크기 수준의 패키지 크기를 갖는 칩 스케일 패키지(Chip Scale Package) 등 다양한 패키지 형태가 개발되어 왔다.Semiconductor devices are becoming smaller in size and increasing in number of input / output pins due to the development of the semiconductor industry and the demand for high speed and high integration of users. Accordingly, the structure of the semiconductor chip package has changed drastically from a pin insertion type to a surface mount type, and a chip scale package (Chip) having a package size of a chip size and a ball grid array package having externally connected terminals Various package types such as Scale Package have been developed.

상호접속 기술에 있어서는 도전성 금속선을 이용하는 와이어 본딩(wire bonding)과 테이프 배선 기판을 이용하는 탭(TAB; Tape Automated Bonding), 및 도전성 재질의 범프를 이용하여 반도체 칩을 기판에 직접 실장하는 플립 칩 본딩(Flip Chip Bonding) 등 다양한 기술이 알려져 있다. 그 중에서 플립 칩 본딩은 고속화와 고밀도화 및 소형화 등에 있어서 다른 상호접속 기술에 비하여 그 효과가 우수하여 최근의 반도체 칩 패키지 제조에 많이 적용되고 있는 실정이다. 플립 칩 본딩용 반도체 칩과 그 실장 구조를 이하에서 소개하기로 한다.In the interconnect technology, wire bonding using a conductive metal wire, tape automated bonding (TAB) using a tape wiring board, and flip chip bonding that directly mounts a semiconductor chip to a substrate using a bump of a conductive material ( Various techniques, such as Flip Chip Bonding), are known. Among them, flip chip bonding is excellent in its effects compared to other interconnect technologies in speed, density, and miniaturization, and is widely applied to the manufacture of semiconductor chips in recent years. A flip chip bonding semiconductor chip and its mounting structure will be described below.

도 1은 종래 기술에 따른 플립 칩 본딩용 반도체 칩의 부분 단면도이고, 도 2는 종래 기술에 따른 플립 칩 본딩용 반도체 칩이 인쇄회로기판에 실장된 상태를 나타낸 부분 단면도이다.1 is a partial cross-sectional view of a flip chip bonding semiconductor chip according to the prior art, and FIG. 2 is a partial cross-sectional view showing a state in which the flip chip bonding semiconductor chip according to the prior art is mounted on a printed circuit board.

도 1에 도시된 것과 같이 일반적으로 플립 칩 본딩에 이용되는 반도체 칩(100)은 전극패드(102)와 접속되어 도전성 재질의 범프, 예컨대 볼 형태의 솔더 범프(110)가 형성된 구조이다. 반도체 기판(101) 상부에는 외부와의 전기적 연결을 위하여 알루미늄 또는 구리 재질의 전극패드(102)가 형성되어 있고, 그 전극패드(102)가 노출되도록 하여 패시베이션층(passivation layer; 103)이 덮여져 있다. 솔더 범프(110)는 노출된 전극패드(102) 상부에 형성되는 데, 솔더 범프(110)와 전극패드(102) 사이에는 다층으로 이루어진 범프 하부 금속층(UBM; Under Barrier Metallurgy, 109)이 형성된다.As shown in FIG. 1, a semiconductor chip 100 generally used for flip chip bonding is connected to an electrode pad 102 to form a bump of a conductive material, eg, a solder bump 110 having a ball shape. An electrode pad 102 made of aluminum or copper is formed on the semiconductor substrate 101 to make an electrical connection with the outside, and the passivation layer 103 is covered by exposing the electrode pad 102. have. The solder bumps 110 are formed on the exposed electrode pads 102, and a lower bump metal layer UBM (UBM) 109 is formed between the solder bumps 110 and the electrode pads 102. .

범프 하부 금속층(109)은 전극패드(102) 상에 형성되어 솔더 범프(110)의 솔더 성분이 전극패드(102)와 반도체 기판(101)으로 침투되지 않도록 막아주는 확산 방지의 역할을 하는 장벽 금속층(barrier metal layer, 107)과 그 장벽 금속층(107) 위에 형성되어 솔더 범프(110)가 잘 접합될 수 있도록 하기 위한 솔더 웨팅층(solder wetting layer, 108) 등을 포함하여 이루어진다.The bump lower metal layer 109 is formed on the electrode pad 102 to prevent diffusion of the solder component of the solder bump 110 into the electrode pad 102 and the semiconductor substrate 101. and a solder wetting layer 108 formed on the barrier metal layer 107 and the barrier metal layer 107 to allow the solder bumps 110 to be bonded well.

이 플립 칩 본딩용 반도체 칩(100)은 도 2에 도시된 것과 같이 인쇄회로기판(130)의 서브스트레이트(131)에 마련되어 있는 기판 접촉패드(132)와 솔더 범프(110)가 접합되어 전기적인 연결과 물리적인 결합을 이루게 된다. 도시되지 않았지만 보통 반도체 칩(110)과 인쇄회로기판(130) 사이는 언더필 수지(underfill resin)가 채워져 접합 부분이 외부환경으로부터 보호되도록 함으로써 상호연결에 대한 신뢰성이 향상되도록 하고 있다.As shown in FIG. 2, the flip chip bonding semiconductor chip 100 is electrically bonded to the substrate contact pads 132 and the solder bumps 110 provided on the substrate 131 of the printed circuit board 130. A physical connection is made with the connection. Although not shown, an underfill resin is usually filled between the semiconductor chip 110 and the printed circuit board 130 to improve the reliability of the interconnection by protecting the joint from the external environment.

그런데, 앞에서 소개한 바와 같은 종래의 플립 칩 본딩용 반도체 칩과 그 실장 구조로서 최근의 칩 소형화에 대응하기에는 몇 가지 어려움이 따른다. 칩 소형화를 위하여 범프 크기의 축소 요구와 그에 따른 반도체 칩과 인쇄회로기판 사이의 간격 감소가 요구되는데, 언더필 물질의 입자 크기로 인하여 언더필이 잘 이루어지지 않는 등 공정 진행에 어려움이 존재한다. 이와 같은 문제를 해소하기 위한 방안으로서 언더필 물질 내부에 포함된 입자의 크기를 축소시킨 언더필 물질의 개발이 필요하나 그 개발 등으로 인한 원가 상승 및 공정 상의 어려움이 따른다. 또한, 범프 크기의 감소로 인하여 접합면적이 감소됨으로써 접합 신뢰성이 감소되는 문제점도 있다.However, there are some difficulties in dealing with the recent miniaturization of the chip as a conventional flip chip bonding semiconductor chip as described above and its mounting structure. In order to reduce the size of the chip, it is required to reduce the bump size and thereby reduce the gap between the semiconductor chip and the printed circuit board. However, due to the particle size of the underfill material, there is a difficulty in the process such as the underfill is not well achieved. In order to solve such a problem, it is necessary to develop an underfill material in which the size of the particles contained in the underfill material is reduced, but cost increases and process difficulties due to the development thereof. In addition, there is a problem in that the joint area is reduced due to the decrease in the bump size, thereby reducing the joint reliability.

본 발명의 목적은 칩 소형화에 대응하여 반도체 칩의 범프와 기판간의 접합력이 향상되어 언더필이 필요 없으며 접합 신뢰성이 향상된 플립 칩 본딩용 반도체 칩과 그 실장 구조를 제공하는 데에 있다.Disclosure of Invention An object of the present invention is to provide a flip chip bonding semiconductor chip and a mounting structure thereof, in which bumps of a semiconductor chip and a substrate are improved in accordance with chip miniaturization, thereby eliminating the need for underfill and improving the bonding reliability.

이와 같은 목적을 달성하기 위한 본 발명에 따른 플립 칩 본딩용 반도체 칩은, 집적회로가 형성된 반도체 기판과, 집적회로와 연결되어 외부와의 전기적 연결을 위하여 반도체 기판 상에 형성된 전극패드와, 전극패드의 적어도 일부분을 노출시키며 반도체 기판 상에 형성된 패시베이션층과, 전극패드와 접속되어 전극패드 부분 및 그 주변의 패시베이션층에 형성되는 제 1범프 하부 금속층과, 제 1범프 하부 금속층 상에 소정 높이의 링 형태를 가지며 형성된 3차원 범프 하부 금속층과, 제 1범프 하부 금속층 상에 3차원 범프 하부 금속층을 덮으며 형성된 솔더층, 및 폴리머 코어(polymer core)가 내장되어 있으며 그 폴리머 코어가 3차원 범프 하부 금속층에 일정 부분이 삽입된 형태를 갖도록 솔더층 상에 형성된 솔더 범프를 포함하는 것을 특징으로 한다.In order to achieve the above object, a semiconductor chip for flip chip bonding according to the present invention includes a semiconductor substrate having an integrated circuit, an electrode pad connected to the integrated circuit and formed on the semiconductor substrate for electrical connection with the outside, and an electrode pad. A passivation layer formed on the semiconductor substrate exposing at least a portion of the substrate, a first bump lower metal layer formed on the electrode pad portion and a passivation layer surrounding the electrode pad portion, and a ring having a predetermined height on the first bump lower metal layer. A three-dimensional bump lower metal layer having a shape, a solder layer formed covering the three-dimensional bump lower metal layer on the first bump lower metal layer, and a polymer core are embedded, and the polymer core is a three-dimensional bump lower metal layer. It characterized in that it comprises a solder bump formed on the solder layer to have a shape in which a predetermined portion is inserted.

여기서, 솔더 범프로서는 볼 범프이고 3차원 범프 하부 금속층으로서는 원형의 링 형상인 것이 바람직하다. 3차원 범프 하부 금속층으로서는 니켈(Ni), 구리(Cu), 팔라듐(Pd), 백금(Pt) 및 그 합금 재질이 적합하다. 그리고, 솔더층으로서는 주석(Sn), 납(Pb), 니켈(Ni), 금(Au), 은(Ag), 구리(Cu), 비스무트(Bi) 및 그 합금 등의 재질이 적합하다. Here, it is preferable that it is a ball bump as a solder bump and a circular ring shape as a 3D bump lower metal layer. As the three-dimensional bump lower metal layer, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt) and alloy materials thereof are suitable. As the solder layer, materials such as tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and alloys thereof are suitable.

또한, 또한 상기 목적을 달성하기 위한 본 발명에 따른 플립 칩 본딩용 반도체 칩 실장 구조는, 전술한 본 발명의 플립 칩 본딩용 반도체 칩과, 기판 접촉패드와 그 기판 접촉패드에 3차원 범프 하부 금속층과 대응되는 위치에 소정 높이로 형성되어 솔더 범프의 폴리머 코어를 지지하는 지지층을 갖는 기판을 포함하며, 폴리머 코어가 3차원 범프 하부 금속층과 3차원 패드 상부 금속층 사이에 끼워진 형태로 범프 본딩된 것을 특징으로 한다.In addition, the flip chip bonding semiconductor chip mounting structure according to the present invention for achieving the above object is a three-dimensional bump lower metal layer on the flip chip bonding semiconductor chip of the present invention, the substrate contact pad and the substrate contact pad. And a substrate having a support layer formed at a predetermined height at a position corresponding to the support layer and supporting the polymer core of the solder bump, wherein the polymer core is bump-bonded in a form sandwiched between the 3D bump lower metal layer and the 3D pad upper metal layer. It is done.

지지층으로서는 기판 접촉패드로부터 소정 높이의 링 형태를 가지는 3차원 구조의 패드 상부 금속층(Top surface metallurgy)인 것이나, 포토 솔더 레지스트층인 것이 바람직하다.The supporting layer is preferably a pad top metallurgy having a three-dimensional structure having a ring shape of a predetermined height from the substrate contact pad, or a photo solder resist layer.

이하 첨부 도면을 참조하여 본 발명에 따른 플립 칩 본딩용 반도체 칩과 실장 구조를 보다 상세하게 설명하고자 한다.Hereinafter, a flip chip bonding semiconductor chip and a mounting structure according to the present invention will be described in detail with reference to the accompanying drawings.

도 3a는 본 발명에 따른 플립 칩 본딩용 반도체 칩을 나타낸 부분 단면도이고, 도 3b는 도 3의 Ⅰ-Ⅰ선에 따른 단면도이며 도 4는 본 발명에 따른 플립 칩 본딩용 반도체 칩의 실장 구조를 나타낸 부분 단면도이며, 도 5는 본 발명에 따른 플립 칩 본딩용 반도체 칩과 종래 기술에 따른 플립 칩 본딩용 반도체 칩의 응력에 대한 시뮬레이션(simulation) 결과를 나타낸 그림이다.3A is a partial cross-sectional view illustrating a flip chip bonding semiconductor chip according to the present invention, FIG. 3B is a cross-sectional view taken along line I-I of FIG. 3, and FIG. 4 is a mounting structure of the flip chip bonding semiconductor chip according to the present invention. 5 is a diagram illustrating a simulation result of stress of a flip chip bonding semiconductor chip according to the present invention and a flip chip bonding semiconductor chip according to the related art.

도 3a와 도 3b에 도시된 바와 같이 본 발명에 따른 플립 칩 본딩용 반도체 칩(300)은 내부에 집적회로가 형성된 반도체 기판(301) 상부에 외부와의 전기적인 연결을 위하여 전극패드(302)가 형성되어 있고, 그 전극패드(302)를 노출시키며 패시베이션층(303)이 덮여져 있다. 전극패드(302)의 주변 일정 부분에서 전극패드(302)와 접합되어 제 1범프 하부 금속층(304)이 형성되어 있고, 그 위에 링 형태의 3차원 범프 하부 금속층(307)이 형성되어 있으며, 제 1범프 하부 금속층(304) 위에 3차원 범프 하부 금속층(307)을 덮으며 솔더층(308)이 형성되어 있고, 그 위에 폴리머 코어(311)가 내장된 솔더 범프(310)가 형성되어 있다.As illustrated in FIGS. 3A and 3B, the flip chip bonding semiconductor chip 300 according to the present invention includes an electrode pad 302 for electrical connection with an outside on a semiconductor substrate 301 having an integrated circuit therein. Is formed, and the passivation layer 303 is covered while exposing the electrode pad 302. The first bump lower metal layer 304 is formed by bonding to the electrode pad 302 at a peripheral portion of the electrode pad 302, and a three-dimensional bump lower metal layer 307 having a ring shape is formed thereon. A solder layer 308 is formed on the one bump lower metal layer 304 to cover the three-dimensional bump lower metal layer 307, and a solder bump 310 in which the polymer core 311 is embedded is formed thereon.

전극패드(302)는 입출력 단자로 사용되며 알루미늄, 구리 등으로 이루어진다. 패시베이션층(303)은 실리콘 질화막, 실리콘 산화막, 폴리이미드(polyimide) 등으로 이루어진다. 패시베이션층(303) 위에 보호층을 더 형성할 수 있으나 그에 대한 설명은 생략한다. 제 1범프 하부 금속층(304)은 크롬(Cr), 티타늄(Ti), 니켈(Ni), 티타늄-텅스텐(TiW) 등 공지의 범프 하부 금속층 재질로 이루어질 수 있으며 솔더 범프(310)의 솔더 성분이 전극패드(302)와 반도체 기판(301)으로 침투되지 않도록 막아주는 확산방지의 역할을 하며, 접합층으로도 작용된다. 3차원 범프 하부 금속층(307)은 니켈(Ni), 구리(Cu), 팔라듐(Pd), 백금(Pt) 및 그 합금으로 이루어질 수 있으며, 폴리머 코어(311)를 지지하는 역할을 한다. 솔더층(308)은 주석(Sn), 납(Pb), 니켈(Ni), 금(Au), 은(Ag), 구리(Cu), 비스무트(Bi) 및 그 합금으로 이루어질 수 있다.The electrode pad 302 is used as an input / output terminal and is made of aluminum, copper, or the like. The passivation layer 303 is made of a silicon nitride film, a silicon oxide film, polyimide, or the like. A passivation layer may be further formed on the passivation layer 303, but a description thereof will be omitted. The first bump lower metal layer 304 may be made of a known bump lower metal layer material such as chromium (Cr), titanium (Ti), nickel (Ni), titanium-tungsten (TiW), and the solder component of the solder bump 310 may be formed. It serves as a diffusion barrier to prevent the electrode pad 302 and the semiconductor substrate 301 from penetrating, and also serves as a bonding layer. The 3D bump lower metal layer 307 may be made of nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), and an alloy thereof, and serves to support the polymer core 311. The solder layer 308 may be formed of tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and an alloy thereof.

3차원 범프 하부 금속층(307)은 일반적인 범프 하부 금속층과 달리 원형의 링 형태로서 소정 높이를 갖도록 3차원 구조로 형성되는 데 이는 후술되는 솔더 범프(310)의 크기 및 형태를 고려하여 결정된다. 즉, 3차원 범프 하부 금속층(307)은 솔더 범프(310)의 폴리머 코어(311)가 끼워질 수 있는 크기와 높이로 형성된다. 그리고, 솔더층(308)은 솔더 범프(310)의 접합이 잘 이루어지도록 하면서 폴리머 코어(311) 내장된 솔더 범프(310)의 상대적으로 적은 솔더의 양을 보충함으로써 원활한 접합력을 확보하기 위해 형성된다.Unlike the general bump lower metal layer 307, the three-dimensional bump lower metal layer 307 is formed in a three-dimensional structure to have a predetermined height as a circular ring shape, which is determined in consideration of the size and shape of the solder bump 310 to be described later. That is, the 3D bump lower metal layer 307 is formed to have a size and a height to which the polymer core 311 of the solder bump 310 may be fitted. In addition, the solder layer 308 is formed to ensure a smooth bonding force by replenishing a relatively small amount of solder of the solder bump 310 embedded in the polymer core 311 while making the bonding of the solder bump 310 well. .

솔더 범프(310)는 볼 범프(ball bump)로서 내부에 폴리머 재질의 코어(311)와 그 코어 주변에 무전해 도금에 의해 형성된 니켈 재질의 접착층(312) 및 그 접착층(312) 외부의 범프 솔더층(313)으로 구성된다. 폴리머 코어(311)와 접착층(312) 및 범프 솔더층(313)의 두께는 필요에 따라 변화될 수 있으나, 현재 폴리머 코어(311)의 직경이 100㎛, 접착층(312)의 두께가 3㎛, 솔더층(313) 두께가 7㎛ 인 것이 상용화되어 있다. 솔더 범프(310)는 링 형태의 3차원 범프 하부 금속층(307)의 구조로 인하여 폴리머 코어(311)가 3차원 범프 하부 금속층(307)에 끼워진 형태로 형성된다.The solder bumps 310 are ball bumps, and a polymer core 311 therein and a nickel adhesive layer 312 formed by electroless plating around the core and bump solder outside the adhesive layer 312 are provided. Consists of layer 313. The thickness of the polymer core 311, the adhesive layer 312, and the bump solder layer 313 may be changed as necessary, but the diameter of the polymer core 311 is 100 μm, the thickness of the adhesive layer 312 is 3 μm, It is commercially available that the thickness of the solder layer 313 is 7 µm. The solder bump 310 is formed in a shape in which the polymer core 311 is inserted into the 3D bump lower metal layer 307 due to the structure of the 3D bump lower metal layer 307 having a ring shape.

전술한 바와 같은 본 발명에 따른 플립 칩 본딩용 반도체 칩은 솔더 범프가 끼워지는 형태를 갖도록 하는 3차원 구조의 범프 하부 금속층에 의하여 응력 완충 효과를 얻을 수 있다. 1차로 코어에 의해 범프에 가해지는 응력이 완화되며 코어를 지지하는 3차원 범프 하부 금속층에 의해 2차로 응력이 완화된다. 한편, 이와 같은 효과는 응력에 대한 시뮬레이션 결과에 의하여 입증된다. 도 4에서 나타난 것과 같이 종래의 범프에 가해지는 응력이 23.6㎏f/㎟이고, 본 발명의 반도체 칩에서 폴리머 코어의 응력이 14.8㎏f/㎟인 것에서도 입증될 수 있다. 한편, 범프 하부 금속층의 형태는 링 형태로 제한되지 않고 필요에 따라 변화될 수 있다. 이와 같은 본 발명의 플립 칩 본딩용 반도체 칩의 실장 구조를 도 5를 참조하여 소개하기로 한다.In the semiconductor chip for flip chip bonding according to the present invention as described above, a stress buffering effect can be obtained by the bump lower metal layer having a shape in which solder bumps are fitted. The stress exerted on the bumps by the core firstly is relaxed and the stress is secondarily relaxed by the three-dimensional bump bottom metal layer supporting the core. On the other hand, this effect is evidenced by the simulation results for stress. As shown in FIG. 4, the stress applied to the conventional bumps is 23.6 kgf / mm 2, and the stress of the polymer core in the semiconductor chip of the present invention is 14.8 kgf / mm 2. Meanwhile, the shape of the bump lower metal layer is not limited to the ring shape and may be changed as necessary. The mounting structure of the flip chip bonding semiconductor chip of the present invention will be described with reference to FIG. 5.

본 발명의 플립 칩 본딩용 반도체 칩(300)은 도 4에 도시된 바와 같이 인쇄회로기판(330)에 직접 실장된다. 인쇄회로기판(330)에는 기판 접촉패드(332)에 3차원 범프 하부 금속층(307)과 대응되며 기판 접촉패드(332)로부터 소정 높이의 링 형태를 가지는 3차원 구조의 패드 상부 금속층(Top surface metallurgy; 335)이 형성되어 있다. 반도체 칩(300)이 인쇄회로기판(330)에 플립 칩 본딩된 후에 솔더 범프(310)는 3차원 범프 하부 금속층(307)과 패드 상부 금속층(335) 사이에 폴리머 코어(311)가 끼워지는 형태로 존재한다. 폴리머 코어(311)는 3차원 범프 하부 금속층(307)과 패드 상부 금속층(335)에 의해 지지되는 구조를 갖는다. 이에 의해 폴리머 코어(311)에 의한 1차 응력 흡수가 이루어지고 그 폴리머 코어(311)를 3차원 범프 하부 금속층(307)과 패드 상부 금속층(335)이 지지함으로써 응력 완중 효과가 극대화되는 구조를 갖게 된다.The flip chip bonding semiconductor chip 300 of the present invention is directly mounted on the printed circuit board 330 as shown in FIG. 4. The printed circuit board 330 corresponds to the three-dimensional bump lower metal layer 307 on the substrate contact pad 332 and has a three-dimensional pad top metal layer having a ring shape having a predetermined height from the substrate contact pad 332. 335 is formed. After the semiconductor chip 300 is flip chip bonded to the printed circuit board 330, the solder bumps 310 have a polymer core 311 sandwiched between the 3D bump lower metal layer 307 and the pad upper metal layer 335. Exists as. The polymer core 311 has a structure supported by the three-dimensional bump lower metal layer 307 and the pad upper metal layer 335. As a result, primary stress absorption is performed by the polymer core 311, and the polymer core 311 is supported by the 3D bump lower metal layer 307 and the pad upper metal layer 335 to have a structure in which the stress relaxation effect is maximized. do.

본 발명의 플립 칩 본딩용 반도체 칩과 그 실장에 적합한 인쇄회로기판의 제조 과정을 소개하기로 한다.A manufacturing process of a flip chip bonding semiconductor chip of the present invention and a printed circuit board suitable for mounting thereof will be described.

도 6a 내지 도 6f는 본 발명의 플립 칩 본딩용 반도체 칩의 제조 과정을 나타낸 부분 단면도이고, 도 6a 내지 도 6d는 본 발명의 플립 칩 본딩용 반도체 칩 실장 구조에 적합한 인쇄회로기판의 제조 과정을 나타낸 부분 단면도이다.6A to 6F are partial cross-sectional views illustrating a manufacturing process of a flip chip bonding semiconductor chip of the present invention, and FIGS. 6A to 6D illustrate a manufacturing process of a printed circuit board suitable for a flip chip bonding semiconductor chip mounting structure of the present invention. Partial cross section shown.

먼저, 도 6a에서와 같이 반도체 기판(301) 상에 복수의 전극패드(302)가 형성되어 있고, 그 전극패드(302)의 적어도 일 부분이 노출되도록 하여 패시베이션층(303)이 형성된 상태의 반도체 칩을 제공하는 단계가 진행된다. 잘 알려진 바와 같이 전극패드(302)는 통상적인 알루미늄이나 구리 등의 금속 재질로 형성한다.First, as shown in FIG. 6A, a plurality of electrode pads 302 are formed on the semiconductor substrate 301, and at least a portion of the electrode pads 302 is exposed to expose the semiconductor with the passivation layer 303 formed thereon. Providing the chip proceeds. As is well known, the electrode pad 302 is formed of a metal material such as aluminum or copper.

다음으로, 도 6b에서와 같이 패시베이션층(303) 및 전극패드(302)의 노출 부분을 덮는 범프 하부 금속층(304)을 형성한다. 범프 하부 금속층(304)은 스퍼터링(sputtering) 공정에 의해 형성될 수 있다.Next, as shown in FIG. 6B, the bump lower metal layer 304 covering the passivation layer 303 and the exposed portion of the electrode pad 302 is formed. The bump lower metal layer 304 may be formed by a sputtering process.

다음으로, 도 6c에서와 같이 범프 하부 금속층(304) 상에 포토레지스트층(305)을 형성한다. 포토레지스트층(305)의 높이는 후술되는 솔더 범프의 크기나 형상을 고려하여 결정될 수 있다.Next, as shown in FIG. 6C, the photoresist layer 305 is formed on the bump lower metal layer 304. The height of the photoresist layer 305 may be determined in consideration of the size or shape of the solder bump described later.

다음으로, 노광 및 현상을 진행하여 도 6d에서와 같이 전극패드(302) 주변 부분에서 포토레지스트층(305)으로부터 원형의 링 형상으로 제 1금속층(304)을 노출시키는 개구부(306)를 형성하는 단계가 진행된다. 이때 개구부(306)의 위치 및 형태는 필요에 따라 달라질 수 있다.Next, exposure and development are performed to form openings 306 exposing the first metal layer 304 in a circular ring shape from the photoresist layer 305 around the electrode pad 302 as shown in FIG. 6D. Step proceeds. At this time, the position and shape of the opening 306 may vary as necessary.

다음으로, 도 6e에서와 같이 개구부(306)에 3차원 범프 하부 금속층(307)을 형성한다. 3차원 범프 하부 금속층(307)은 포토레지스트층(305)에 의해 소정 높이를 갖는 원형의 링 형태로 형성될 수 있다. 3차원 범프 하부 금속층(307)은 전기도금(electroplating)에 의해 형성될 수 있다.Next, a 3D bump lower metal layer 307 is formed in the opening 306 as shown in FIG. 6E. The 3D bump lower metal layer 307 may be formed in a circular ring shape having a predetermined height by the photoresist layer 305. The three-dimensional bump lower metal layer 307 may be formed by electroplating.

다음으로, 도 6f에서와 같이 범프 형성을 위하여 전극패드(302) 주변의 일정 부분의 포토레지스트층(305)을 개방시키고 그 개방된 부분으로부터 노출되는 부분에 솔더층(308)을 형성한다. 솔더층(308)은 이후 공정에서 범프 하부 금속층(307)의 에칭(etching) 과정 및 전극패드(302)와 3차원 범프 하부 금속층(307)으로의 화학적 침투로부터의 보호 및 후술되는 폴리머 코어(311)를 갖는 솔더 범프(310)의 상대적으로 적은 솔더 양의 보충 등을 고려하여 형성된다. 이는 현상 및 도금 과정에 의해 이루어질 수 있다.Next, as shown in FIG. 6F, a portion of the photoresist layer 305 around the electrode pad 302 is opened to form a bump, and a solder layer 308 is formed on a portion exposed from the open portion. The solder layer 308 is protected from chemical etching into the electrode pad 302 and the three-dimensional bump lower metal layer 307 and the polymer core 311 described later in the subsequent process. ) Is formed in consideration of the replenishment of the relatively small amount of solder of the solder bumps 310 having a). This can be done by development and plating process.

다음으로, 포토레지스트층(305)을 제거하고 솔더층(308) 주변의 제 1범프 하부 금속층(304)을 제거하고 폴리머 코어(311)가 내장된 솔더 범프(310)를 형성하면 도 3에서와 같은 본 발명의 플립 칩 본딩용 반도체 칩(300)의 제조가 완료된다. 제 1범프 하부 금속층(304)의 제거에는 통상의 에칭 공정이 적용될 수 있다. 솔더 범프(310)는 링 형태의 3차원 범프 하부 금속층(307)이 형성된 전극패드(302) 상부에 범프 부착 장비를 이용하여 3차원 범프 하부 금속층(307)에 끼워지는 형태로 올려놓음과 동시에 레이저 소오스를 이용한 리플로우 과정을 거쳐 형성될 수 있다.Next, when the photoresist layer 305 is removed, the first bump lower metal layer 304 around the solder layer 308 is removed, and the solder bump 310 having the polymer core 311 is formed, as shown in FIG. 3. The manufacturing of the flip chip bonding semiconductor chip 300 of the present invention is completed. A conventional etching process may be applied to the removal of the first bump lower metal layer 304. The solder bumps 310 are mounted on the electrode pads 302 in which the ring-shaped three-dimensional bump lower metal layer 307 is formed to be fitted to the three-dimensional bump lower metal layer 307 using bump attachment equipment, and at the same time, the laser is mounted. It may be formed through a reflow process using a source.

본 발명의 플립 칩 본딩용 반도체 칩 실장 구조에 적용되는 인쇄회로기판의 제조 과정을 설명하기로 한다.A manufacturing process of a printed circuit board applied to a flip chip bonding semiconductor chip mounting structure of the present invention will be described.

도 7a 내지 도 7d는 본 발명의 플립 칩 본딩용 반도체 칩 실장 구조에 적합한 인쇄회로기판의 제조 과정을 나타낸 부분 단면도이다.7A to 7D are partial cross-sectional views illustrating a manufacturing process of a printed circuit board suitable for a flip chip bonding semiconductor chip mounting structure of the present invention.

먼저, 도 7a에서와 같이 서브스트레이트(331) 상에 회로패턴(도시안됨) 및 접촉패드(332)를 형성하고 접촉패드(332)를 덮는 수지층(333)을 형성한다. 다음으로 도 7b에서와 같이 접촉패드를 노출시키는 링 형태의 개구부(334)를 형성한다. 그리고, 도 7c에서와 같이 그 개구부(334)에 금속 물질을 채워 넣어 패드 상부 금속층(335)을 형성한다. 그 후에 수지층을 제거하면 도 7d에서와 같이 소정 두께의 링 형태를 갖는 3차원 패드 상부 금속층(335)이 형성된 인쇄회로기판(330)이 얻어진다.First, as shown in FIG. 7A, a circuit pattern (not shown) and a contact pad 332 are formed on the substrate 331, and a resin layer 333 is formed to cover the contact pad 332. Next, as shown in FIG. 7B, a ring-shaped opening 334 exposing the contact pad is formed. As shown in FIG. 7C, the pad upper metal layer 335 is formed by filling a metal material into the opening 334. Subsequently, when the resin layer is removed, a printed circuit board 330 having a three-dimensional pad upper metal layer 335 having a ring shape having a predetermined thickness as shown in FIG. 7D is obtained.

한편, 본 발명에 따른 플립 칩 본딩용 반도체 칩과 그 실장 구조는 전술한 실시예에 한정되지 않고 본 발명의 기술적 중심 사상을 벗어나지 않는 범위 내에서 다양하게 변형 실시될 수 있다. 예를 들어, 도 8은 본 발명에 따른 플립 칩 본딩용 반도체 칩의 실장 구조의 다른 예를 나타낸 부분 단면도로서, 도 8에서와 같이 기판 접촉패드(352)의 일정 부분을 노출시키며 서브스트레이트(351) 상에 형성되는 포토 솔더레지스트층(353)이 솔더 범프(310)의 폴리머 코어(311)가 끼워지는 형태로 일정 크기와 높이로 형성되어 폴리머 코어(311)를 지지할 수 있도록 하는 인쇄회로기판(350)을 적용하여 플립 칩 본딩에 대한 신뢰성을 향상할 수도 있다.Meanwhile, the semiconductor chip for flip chip bonding and the mounting structure thereof according to the present invention are not limited to the above-described embodiments and may be variously modified within a range not departing from the technical spirit of the present invention. For example, FIG. 8 is a partial cross-sectional view showing another example of a mounting structure of a flip chip bonding semiconductor chip according to the present invention. As shown in FIG. 8, a portion of the substrate contact pad 352 is exposed and the substrate 351 is exposed. A printed circuit board which is formed on the photo solder resist layer 353 formed at a predetermined size and height in a shape in which the polymer core 311 of the solder bumps 310 is inserted to support the polymer core 311. 350 may be applied to improve reliability for flip chip bonding.

이상과 같은 본 발명에 따른 플립 칩 본딩용 반도체 칩과 그 실장 구조에 의하면, 코어 내장 솔더 범프와 3차원 범프 하부 금속층 및 기판 접촉패드의 3차원 상부 금속층 등에 의해 솔더 범프 자체의 응력 완충 효과가 크게 향상되어 언더필 물질을 주입하지 않고도 솔더 범프 자체의 접합력이 확보되며 열팽창계수 차이 등에 기인하여 범프에 집중되는 응력이 완화되는 효과가 있다.According to the semiconductor chip for flip chip bonding and its mounting structure according to the present invention as described above, the stress buffering effect of the solder bump itself is greatly increased by the core embedded solder bump, the three-dimensional bump lower metal layer, and the three-dimensional upper metal layer of the substrate contact pad. As a result, the bonding force of the solder bumps is secured without injecting the underfill material, and stresses concentrated on the bumps are alleviated due to differences in thermal expansion coefficients.

도 1은 종래 기술에 따른 플립 칩 본딩용 반도체 칩의 부분 단면도,1 is a partial cross-sectional view of a semiconductor chip for flip chip bonding according to the prior art,

도 2는 종래 기술에 따른 플립 칩 본딩용 반도체 칩이 인쇄회로기판에 실장된 상태를 나타낸 부분 단면도,2 is a partial cross-sectional view showing a state in which a flip chip bonding semiconductor chip according to the prior art is mounted on a printed circuit board;

도 3a는 본 발명에 따른 플립 칩 본딩용 반도체 칩을 나타낸 부분 단면도,3A is a partial cross-sectional view illustrating a semiconductor chip for flip chip bonding according to the present invention;

도 3b는 도 3의 Ⅰ-Ⅰ선에 따른 단면도,3B is a cross-sectional view taken along the line I-I of FIG. 3;

도 4는 본 발명에 따른 플립 칩 본딩용 반도체 칩의 실장 구조를 나타낸 부분 단면도,4 is a partial cross-sectional view showing a mounting structure of a semiconductor chip for flip chip bonding according to the present invention;

도 5는 본 발명에 따른 플립 칩 본딩용 반도체 칩과 종래 기술에 따른 플립 칩 본딩용 반도체 칩의 응력에 대한 시뮬레이션(simulation) 결과를 나타낸 그림,5 is a view showing a simulation result of the stress of the flip chip bonding semiconductor chip according to the present invention and the flip chip bonding semiconductor chip according to the prior art,

도 6a 내지 도 6f는 본 발명의 플립 칩 본딩용 반도체 칩의 제조 과정을 나타낸 부분 단면도,6A through 6F are partial cross-sectional views illustrating a manufacturing process of a semiconductor chip for flip chip bonding according to the present invention;

도 7a 내지 도 7d는 본 발명의 플립 칩 본딩용 반도체 칩 실장 구조에 적합한 인쇄회로기판의 제조 과정을 나타낸 부분 단면도, 및7A to 7D are partial cross-sectional views illustrating a manufacturing process of a printed circuit board suitable for a semiconductor chip mounting structure for flip chip bonding according to the present invention; and

도 8은 본 발명에 따른 플립 칩 본딩용 반도체 칩의 실장 구조의 다른 예를 나타낸 부분 단면도이다.8 is a partial cross-sectional view showing another example of a mounting structure of a semiconductor chip for flip chip bonding according to the present invention.

* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings

100,300: 플립 칩 본딩용 반도체 칩 101,301: 반도체 기판100,300: semiconductor chip for flip chip bonding 101,301: semiconductor substrate

102,302: 전극패드 103,303: 패시베이션층102, 302: electrode pad 103,303: passivation layer

105: 비활성화층 107: 장벽 금속층105: passivation layer 107: barrier metal layer

108: 솔더 ??터블층 109,304,307: 범프 하부 금속층108: solder? Able layer 109,304,307: bump lower metal layer

110,310: 솔더 범프 131,331,351: 서브스트레이트110,310: solder bumps 131,331,351: substrate

132,332: 기판 접촉패드 305: 포토레지스트층132,332 substrate contact pad 305 photoresist layer

306: 개구부 308: 솔더층306: opening 308: solder layer

311: 폴리머 코어 312: 접착층311: polymer core 312: adhesive layer

313: 범프 솔더층 330: 인쇄회로기판313: bump solder layer 330: printed circuit board

333: 수지층 353: 포토솔더 레지스트층333: Resin layer 353: photosolder resist layer

335: 패드 상부 금속층(Top Surface Metallurgy)335: Top Surface Metallurgy

Claims (8)

집적회로가 형성된 반도체 기판과;A semiconductor substrate on which an integrated circuit is formed; 상기 집적회로와 연결되어 외부와의 전기적 연결을 위하여 상기 반도체 기판 상에 형성된 전극패드와;An electrode pad connected to the integrated circuit and formed on the semiconductor substrate for electrical connection with the outside; 상기 전극패드의 적어도 일부분을 노출시키며 상기 반도체 기판 상에 형성된 패시베이션층과;A passivation layer formed on the semiconductor substrate to expose at least a portion of the electrode pad; 상기 전극패드와 접속되어 상기 전극패드 부분 및 그 주변의 패시베이션층에 형성되는 제 1범프 하부 금속층과;A first bump lower metal layer connected to the electrode pad and formed on a portion of the electrode pad and a passivation layer around the electrode pad; 상기 제 1범프 하부 금속층 상에 소정 높이의 링 형태를 가지며 형성된 3차원 범프 하부 금속층과;A three-dimensional bump lower metal layer having a ring shape having a predetermined height on the first bump lower metal layer; 상기 제 1범프 하부 금속층 상에 3차원 범프 하부 금속층을 덮으며 형성된 솔더층; 및 A solder layer formed on the first bump lower metal layer to cover the 3D bump lower metal layer; And 폴리머 코어가 내장되어 있으며, 상기 폴리머 코어가 상기 3차원 범프 하부 금속층에 일정 부분이 삽입된 형태를 갖도록 상기 솔더층 상에 형성된 솔더 범프;A solder bump having a polymer core embedded therein and formed on the solder layer such that the polymer core has a shape in which a portion is inserted into the 3D bump lower metal layer; 를 갖는 것을 특징으로 하는 플립 칩 본딩용 반도체 칩.Flip chip bonding semiconductor chip having a. 제 1항에 있어서, 상기 3차원 범프 하부 금속층은 원형의 링 형상인 것을 특징으로 하는 플립 칩 본딩용 반도체 칩.The flip chip bonding semiconductor chip of claim 1, wherein the three-dimensional bump lower metal layer has a circular ring shape. 제 1항에 있어서, 상기 솔더 범프는 볼 범프인 것을 특징으로 하는 플립 칩 본딩용 반도체 칩.2. The semiconductor chip of claim 1, wherein the solder bumps are ball bumps. 제 1항에 있어서, 상기 3차원 범프 하부 금속층은 니켈(Ni), 구리(Cu), 팔라듐(Pd), 백금(Pt) 및 그 합금 중에서 선택되는 것을 특징으로 하는 플립 칩 본딩용 반도체 칩.The semiconductor chip of claim 1, wherein the three-dimensional bump lower metal layer is selected from nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), and an alloy thereof. 제 1항에 있어서, 상기 솔더층은 주석(Sn), 납(Pb), 니켈(Ni), 금(Au), 은(Ag), 구리(Cu), 비스무트(Bi) 및 그 합금 중에서 선택되는 것을 특징으로 하는 플립 칩 본딩용 반도체 칩.The method of claim 1, wherein the solder layer is selected from tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), and alloys thereof. A semiconductor chip for flip chip bonding, characterized in that. 집적회로가 형성된 반도체 기판과, 상기 집적회로와 연결되어 외부와의 전기적 연결을 위하여 상기 반도체 기판 상에 형성된 전극패드와, 상기 전극패드의 적어도 일부분을 노출시키며 상기 반도체 기판 상에 형성된 패시베이션층과, 상기 전극패드와 접속되어 상기 전극패드 부분 및 그 주변의 패시베이션층에 형성되는 제 1범프 하부 금속층과, 상기 제 1범프 하부 금속층 상에 소정 높이의 링 형태를 가지며 형성된 3차원 범프 하부 금속층과, 상기 제 1범프 하부 금속층 상에 3차원 범프 하부 금속층을 덮으며 형성된 솔더층, 및 폴리머 코어가 내장되어 있으며 상기 폴리머 코어가 상기 3차원 범프 하부 금속층에 일정 부분이 삽입된 형태를 갖도록 상기 솔더층 상에 형성된 솔더 범프를 갖는 반도체 칩과; A semiconductor substrate having an integrated circuit formed thereon, an electrode pad formed on the semiconductor substrate connected to the integrated circuit for electrical connection to the outside, a passivation layer formed on the semiconductor substrate exposing at least a portion of the electrode pad; A first bump lower metal layer connected to the electrode pad and formed on a portion of the electrode pad and a passivation layer around the electrode pad, a three-dimensional bump lower metal layer formed on the first bump lower metal layer and having a ring shape having a predetermined height; A solder layer formed on the first bump lower metal layer to cover the 3D bump lower metal layer, and a polymer core is embedded, and the polymer core has a shape in which a portion is inserted into the 3D bump lower metal layer. A semiconductor chip having formed solder bumps; 기판 접촉패드와, 상기 기판 접촉패드에 상기 3차원 범프 하부 금속층과 대응되는 위치에 소정 높이로 형성되어 상기 솔더 범프의 폴리머 코어를 지지하는 지지층을 갖는 기판;을 포함하며,And a substrate having a substrate contact pad and a support layer formed on the substrate contact pad at a predetermined height at a position corresponding to the three-dimensional bump lower metal layer to support the polymer core of the solder bumps. 상기 폴리머 코어가 상기 3차원 범프 하부 금속층과 상기 3차원 패드 상부 금속층 사이에 끼워진 형태로 범프 본딩된 것을 특징으로 하는 플립 칩 본딩용 반도체 칩 실장 구조.And the polymer core is bump-bonded in a form sandwiched between the 3D bump lower metal layer and the 3D pad upper metal layer. 제 6항에 있어서, 상기 지지층은 상기 기판 접촉패드로부터 소정 높이의 링 형태를 가지는 3차원 구조의 패드 상부 금속층(Top surface metallurgy)인 것을 특징으로 하는 플립 칩 본딩용 반도체 칩 실장 구조.7. The semiconductor chip mounting structure of claim 6, wherein the support layer is a top surface metallurgy having a three-dimensional structure having a ring shape having a predetermined height from the substrate contact pad. 제 6항에 있어서, 상기 지지층은 포토 솔더 레지스트층인 것을 특징으로 하는 플립 칩 본딩용 반도체 칩 실장 구조.7. The semiconductor chip mounting structure of claim 6, wherein the support layer is a photo solder resist layer.
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