KR20000042669A - Mounting method of semiconductor package - Google Patents
Mounting method of semiconductor package Download PDFInfo
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- KR20000042669A KR20000042669A KR1019980058920A KR19980058920A KR20000042669A KR 20000042669 A KR20000042669 A KR 20000042669A KR 1019980058920 A KR1019980058920 A KR 1019980058920A KR 19980058920 A KR19980058920 A KR 19980058920A KR 20000042669 A KR20000042669 A KR 20000042669A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/1146—Plating
- H01L2224/11462—Electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13111—Tin [Sn] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/13116—Lead [Pb] as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81909—Post-treatment of the bump connector or bonding area
- H01L2224/81948—Thermal treatments, e.g. annealing, controlled cooling
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
본 발명은 반도체 패키지의 실장 방법에 관한 것으로서, 보다 구체적으로는 복수개의 솔더 볼이 격자 형상으로 배열된 패키지를 기판의 패드에 실장하는 방법에 관한 것이다.The present invention relates to a method for mounting a semiconductor package, and more particularly, to a method for mounting a package in which a plurality of solder balls are arranged in a lattice shape on a pad of a substrate.
패키지의 한 예로서, 가장 범용으로 사용되고 있는 에스오제이(SOJ:Small Outline J-lead) 타입이 있고, 특수한 경우에 사용하는 지프(ZIP: Zigzag Inline Package) 타입이 있으며, 또 규격화되고 있는 메모리 카드(memory card)에 적합하도록 구성된 티에스오피(TSOP: Thin Small Outline Package) 타입 등이 있다.An example of a package is a small outline J-lead (SOJ) type that is most commonly used, and a Zigzag Inline Package (ZIP) type that is used in a special case. There is a Thin Small Outline Package (TSOP) type that is configured to be suitable for a memory card.
이러한 패키지 제조 방법을 개략적으로 설명하면 다음과 같다.The manufacturing method of such a package is briefly described as follows.
먼저, 웨이퍼를 스크라이빙 라인을 따라 절단하는 소잉(sawing) 공정을 진행하여 개개의 반도체 칩으로 분리한 다음, 리드 프레임의 인너 리드를 각 반도체 칩에 부착하는 다이 어태치 공정을 진행한다.First, a sawing process of cutting a wafer along a scribing line is performed to separate the semiconductor chips into individual semiconductor chips, and then a die attach process of attaching the inner lead of the lead frame to each semiconductor chip is performed.
이후 일정 온도에서 일정시간 동안 큐어링(curing)을 실시한 후, 반도체 칩의 패드와 리드 프레임의 인너 리드를 금속 와이어로 상호 연결시켜 전기적으로 연결시키는 와이어 본딩 공정을 수행한다.After curing at a predetermined temperature for a predetermined time, a wire bonding process is performed in which the pads of the semiconductor chip and the inner lead of the lead frame are interconnected with metal wires to be electrically connected to each other.
와이어 본딩이 끝나면, 봉지제를 사용하여 반도체 칩을 몰딩하는 몰딩 공정을 수행한다. 이와 같이 반도체 칩을 몰딩해야만, 외부의 열적, 기계적 충격으로 부터 반도체 칩을 보호할 수가 있는 것이다.After the wire bonding is finished, a molding process of molding a semiconductor chip using an encapsulant is performed. Only by molding the semiconductor chip in this way, can the semiconductor chip be protected from external thermal and mechanical shocks.
상기와 같은 몰딩 공정이 완료된 후에는 아우터 리드을 도금하는 플래팅 공정, 아우터 리드를 지지하고 있는 댐바를 절단하는 트림 공정, 및 기판에 실장이 용이하도록 아우터 리드를 소정 형태로 절곡 형성하는 포밍 공정을 진행하여, 패키지를 제조한다.After the molding process is completed, a plating process for plating the outer lead, a trimming process for cutting the dam bar supporting the outer lead, and a forming process for bending the outer lead into a predetermined shape to facilitate mounting on the substrate are performed. To prepare the package.
이러한 공정으로 제작되는 일반적인 패키지에 대해, 패키지의 경박화를 위해 제시된 볼 그리드 어레이 패키지는 기판에 실장되는 수 개의 솔더 볼이 어레이식으로 배열된 구조로 이루어져 있다.For a typical package manufactured by this process, the ball grid array package proposed for thinning the package has a structure in which several solder balls mounted on a substrate are arranged in an array form.
한편, 볼 그리드 어레이 패키지를 솔더 볼을 매개로 기판의 패드에 실장할 때, 구리 재질인 볼 랜드와 주석 재질인 솔더 볼이 접촉하는 계면에서, 구리 원자가 솔더 볼로 확산되어, 계면에서 경도가 높고 강도가 취약한 구리/주석 재질의 금속간 화합물이 소정 두께로 성장하게 된다. 금속간 화합물은 솔더 볼의 조직과 결정 구조가 다르기 때문에, 계면을 불안정하게 만들고, 따라서 외부에서 응력이 작용하게 되면 파단되는 경우가 많았다.On the other hand, when the ball grid array package is mounted on the pad of the substrate via the solder ball, copper atoms diffuse into the solder ball at the interface where the ball land made of copper and the solder ball made of tin contact, resulting in high hardness and strength at the interface. Vulnerable copper / tin intermetallic compounds are grown to a predetermined thickness. Since the intermetallic compound is different in the structure of the solder ball and the crystal structure, the intermetallic compound is unstable at the interface, and therefore, it often breaks when an external stress is applied.
이를 방지하기 위해, 볼 랜드와 패드 전체면에 구리 원자가 솔더 볼로 확산되는 현상을 방지하는 니켈 재질의 확산 방지층(Under Bump Metallurgy:UMP)을 형성하도록 되어 있다.To prevent this, an under bump metallurgy (UMP) layer of nickel is formed on the ball land and the entire surface of the pad to prevent the diffusion of copper atoms into the solder balls.
한편, 패키지를 기판에 실장한 후, 접합력을 강화시키기 위해서, 종래에는 다음과 같은 4가지 방법이 사용되었다.On the other hand, after mounting a package on a board | substrate, the following four methods were conventionally used in order to strengthen the bonding force.
먼저, 에폭시 수지를 각 솔더 볼 사이에 채우는 첫 번째 방법, 솔더 볼이 마운트되는 볼 랜드의 오목한 부분을 에폭시 수지로 보강하는 두 번째 방법, 실장용 솔더볼보다 크기가 큰 4개의 희생용 솔더 볼을 패키지의 각 모서리에 형성하여, 이 희생용 솔더 볼들이 먼저 파단되면서 응력을 완화시키는 세 번째 방법, 마지막으로 볼 랜드와 기판 패드간의 접촉 면적비를 적절하게 변화시키는 방법 등이 사용되었다.First, the first method of filling the epoxy resin between each solder ball, the second method of reinforcing the concave part of the ball land on which the solder ball is mounted with epoxy resin, and the packaging of four sacrificial solder balls larger than the mounting solder balls. Formed at each corner of, the third method of relieving stress as these sacrificial solder balls were broken first, and finally the method of appropriately changing the contact area ratio between the ball land and the substrate pad was used.
그러나, 상기된 종래의 4가지 방법은 다음과 같은 문제점을 안고 있다.However, the above four conventional methods suffer from the following problems.
먼저, 첫 번째 방법은 에폭시 수지를 도포하는 시간과 아울러 에폭시 수지를 경화시키는 시간이 추가로 소요된다. 또한, 모듈로 제작하여 판매하고 있는 메모리 칩의 경우, 모듈 중 일부의 반도체 칩이 불량이 나게 되면, 에폭시 수지 제거가 불가능하기 때문에, 모듈 전체를 폐기처분해야 하는 문제점이 있다.First, the first method requires additional time to cure the epoxy resin as well as time to apply the epoxy resin. In addition, in the case of a memory chip manufactured and sold as a module, when a part of the semiconductor chip of the module is defective, the epoxy resin cannot be removed, and thus the entire module must be disposed of.
두 번째 방법은, 볼 랜드의 오목한 부분에 에폭시 수지를 일일이 도포해야 하므로, 매우 번거로운 작업이 요구된다.In the second method, since the epoxy resin must be applied to the concave portion of the ball land, a very troublesome work is required.
세 번째 방법은, 희생용 솔더 볼이 실장용 솔더 볼보다 크기 때문에, 의해서 패키지를 기판에 실장하기 위해서는 두 번의 공정을 거쳐야만 했다.In the third method, since the sacrificial solder ball is larger than the mounting solder ball, two steps were required to mount the package on the substrate.
네 번째 방법은, 기판 패드를 크게 하면, 솔더 볼 실장시에는 여유도가 확보되나, 상대적으로 패드간의 피치 간격이 줄어들게 되므로써 인접하는 솔더 볼간에 쇼트가 발생될 소지가 매우 높다. 반대로, 기판 패드를 줄이면, 솔더 볼 실장 여유도가 확보되지 않는다.In the fourth method, when the substrate pad is enlarged, a margin is secured when solder ball is mounted, but the pitch gap between pads is relatively reduced, so that shorting occurs between adjacent solder balls. Conversely, if the substrate pad is reduced, the solder ball mounting margin is not secured.
따라서, 본 발명은 종래의 실장 방법들이 안고 있는 제반 문제점들을 해소하기 위해 안출된 것으로서, 금속간 화합물이 경도가 매우 높다는 점을 착안하여, 금속간 화합물 성장 제어를 통해 균열 거리를 증가시키므로써, 솔더 볼이 파단되는 시간을 지연시켜, 접착력을 강화시킬 수 있는 반도체 패키지의 실장 방법을 제공하는데 목적이 있다.Accordingly, the present invention has been made to solve the problems associated with the conventional mounting methods, and focuses on the fact that the intermetallic compound has a very high hardness, thereby increasing the crack distance through the intermetallic compound growth control, It is an object of the present invention to provide a method for mounting a semiconductor package that can retard the time at which a ball breaks, thereby enhancing adhesion.
도 1 내지 도 6은 본 발명에 따른 실장 방법을 순차적으로 나타낸 도면1 to 6 are views sequentially showing the mounting method according to the present invention
도 7은 본 발명에 의해 패키지가 기판에 실장된 상태를 나타낸 도면7 is a view showing a state in which a package is mounted on a substrate in accordance with the present invention
도 8 내지 도 10은 본 발명의 효과를 설명하기 위해 균열이 진행되는 상태를 순차적으로 나타낸 도면8 to 10 are views sequentially showing a state in which the crack progresses to explain the effect of the present invention
- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-
10 ; 볼 랜드 11,31 ; 확산 방지층10; Boland 11,31; Diffusion barrier
12 ; 금속층 20 ; 솔더 볼12; Metal layer 20; Solder ball
21,22 ; 금속간 화합물 30 ; 패드21,22; Intermetallic compound 30; pad
상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 실장 방법은 다음과 같다.In order to achieve the above object, the mounting method according to the present invention is as follows.
패키지의 볼 랜드와 기판의 패드 각각에 가장자리를 따라 확산 방지층을 도금한다. 볼 랜드와 패드 전체 표면에 납/주석 계열의 금속층을 도금하고, 볼 랜드의 금속층에 솔더 볼을 마운트한다. 솔더 볼을 패드의 금속층에 실장한 후, 전체를 열처리한다. 이때, 솔더 볼은 확산 방지층이 가장자리를 따라 도금되어 있으므로, 노출된 볼 랜드와 패드의 중앙 부위에 직접 접촉하게 되고, 따라서 열처리 공정을 통해서 접촉 계면에서부터 구리/주석 계열의 금속간 화합물이 성장하게 된다. 열처리 공정을 적절하게 제어하여, 금속간 화합물이 각 금속층보다 높게 성장하여 솔더 볼 내부로 침투하도록 한다. 그러면, 솔더 볼의 일측으로부터 균열이 발생되었을 때, 이 균열은 경도가 높은 금속간 화합물을 통과하지 못하고 우회하게 되므로써, 균열 길이가 길어지게 된다.Each of the ball lands of the package and the pad of the substrate are plated with a diffusion barrier along the edge. A lead / tin-based metal layer is plated on the entire surface of the ball lands and pads, and solder balls are mounted on the metal layers of the ball lands. After solder ball is mounted on the metal layer of the pad, the whole is heat-treated. In this case, since the diffusion barrier layer is plated along the edge, the solder ball is in direct contact with the exposed ball land and the center of the pad, and thus the copper / tin-based intermetallic compound grows from the contact interface through the heat treatment process. . By appropriately controlling the heat treatment process, the intermetallic compound grows higher than each metal layer and penetrates into the solder ball. Then, when a crack is generated from one side of the solder ball, the crack does not pass through the intermetallic compound having a high hardness and is thus bypassed, resulting in a long crack length.
상기된 본 발명의 구성에 의하면, 금속간 화합물의 성장 두께를 적절하게 제어하여, 균열이 경도가 높은 금속간 화합물을 통과하지 못하고 우회하게 되므로써, 균열 길이가 길어지게 되고, 따라서 솔더 볼이 완전히 파단되는 시간이 지연된다.According to the above-described configuration of the present invention, the growth thickness of the intermetallic compound is appropriately controlled so that the crack bypasses the high intermetallic compound with high hardness, so that the crack length becomes long, so that the solder ball is completely broken. Time is delayed.
이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.
도 1 내지 도 6은 본 발명에 따른 실장 방법을 순차적으로 나타낸 도면이고, 도 7은 본 발명에 의해 패키지가 기판에 실장된 상태를 나타낸 도면이며, 도 8 내지 도 10은 본 발명의 효과를 설명하기 위해 균열이 진행되는 상태를 순차적으로 나타낸 도면이다.1 to 6 are views sequentially showing the mounting method according to the invention, Figure 7 is a view showing a state in which the package is mounted on the substrate by the present invention, Figures 8 to 10 illustrate the effect of the present invention It is a figure which showed the state in which a crack progresses in order in order.
먼저, 도 1에 도시된 구리 재질의 볼 랜드(10)에 도 2와 같이, 종래와 같이 전체 표면이 아니라 가장자리를 따라 환상으로 니켈 재질의 확산 방지층(11)을 형성한다. 확산 방지층(11)을 상기된 바와 같이 환상으로 형성하기 위해서, 포토레지스트로 볼 랜드(10)의 중앙 부위를 차단하고 스퍼터링 방법으로 증착하거나, 또는 볼 랜드(10)의 중앙 부위만을 절연 물질로 차단하고 전해 도금법으로 도금하는 방법 등이 사용될 수 있다.First, as shown in FIG. 2, the diffusion barrier layer 11 made of nickel is formed in an annular shape along the edge of the copper ball land 10 shown in FIG. In order to form the diffusion barrier layer 11 as described above, the center portion of the ball land 10 is blocked with photoresist and deposited by sputtering, or only the center portion of the ball land 10 is blocked with an insulating material. And plating by electrolytic plating may be used.
따라서, 상기된 방법에 의해 확산 방지층(11)을 볼 랜드(10)의 가장자리를 따라 형성하게 되면, 볼 랜드(10)의 중앙 부위는 노출된다. 한편, 본 실시예에 첨부된 도면들은 패키지의 볼 랜드(10)만을 도시하였으나, 기판의 패드에도 확산 방지층을 동일한 형상으로 도금한다.Therefore, when the diffusion barrier layer 11 is formed along the edge of the ball land 10 by the method described above, the central portion of the ball land 10 is exposed. On the other hand, the drawings attached to the present embodiment shows only the ball land 10 of the package, but also plate the diffusion barrier layer in the same shape on the pad of the substrate.
이어서, 도 3와 같이, 볼 랜드(10)의 전체 상부에 납/주석 계열의 금속층(12)을 도금한다. 기판의 패드도 마찬가지로 금속층을 도금한다. 이어서, 솔더 볼(20)을 도 4와 같이 금속층(12)을 매개로 볼 랜드(10)에 마운트한 후, 도 7과 같이 솔더 볼(20)을 기판의 패드(30)에 실장한다.Subsequently, as shown in FIG. 3, the lead / tin-based metal layer 12 is plated on the entire upper portion of the ball land 10. The pad of the substrate similarly plated the metal layer. Subsequently, the solder balls 20 are mounted on the ball lands 10 through the metal layer 12 as shown in FIG. 4, and then the solder balls 20 are mounted on the pads 30 of the substrate as shown in FIG. 7.
그런 다음, 전체를 소정의 온도로 열처리한다. 그러면, 솔더 볼(20)은 노출된 볼 랜드(10)와 패드(30)의 중앙 부위에 직접 접촉된 상태이므로, 이 접촉된 계면에서 구리/주석 계열의 금속간 화합물(21,22)이 도 4 내지 도 6과 같이 성장하게 된다. 특히, 열처리 공정 조건을 적절하게 제어하여, 도 7과 같이 각 금속간 화합물(21,22)이 확산 방지층(11,31)보다 더 높게 성장하여 솔더 볼(20) 내부로 침투하도록 한다.Then, the whole is heat-treated to a predetermined temperature. Then, since the solder ball 20 is in direct contact with the exposed ball land 10 and the central portion of the pad 30, the copper / tin-based intermetallic compounds 21 and 22 are formed at the contacted interface. 4 to 6 will grow. In particular, the heat treatment process conditions are appropriately controlled so that the intermetallic compounds 21 and 22 grow higher than the diffusion barrier layers 11 and 31 to penetrate into the solder ball 20 as shown in FIG. 7.
상기된 바와 같이, 솔더 볼(20)의 상하로 금속간 화합물(21,22)이 성장하게 되면, 솔더 볼(20)에 균열이 발생되었을 때, 균열 길이가 금속간 화합물(21,22)에 의해 늘어나게 된다.As described above, when the intermetallic compounds 21 and 22 grow up and down of the solder balls 20, when the cracks are generated in the solder balls 20, the crack length is increased in the intermetallic compounds 21 and 22. Is increased by.
즉, 도 8와 같이 솔더 볼(20)의 좌측에서부터 균열이 발생되면, 이 균열은 도 9와 같이 경도가 매우 높은 금속간 화합물(21,22)을 통과하지 못하게 된다. 따라서, 도 10과 같이 균열은 금속간 화합물(21,22)을 우회하여 솔더 볼(20)의 우측으로 진행하게 된다. 따라서, 금속간 화합물(21,22)에 의해 균열 길이가 늘어나게 되고, 결과적으로 솔더 볼(20)이 완전히 파단되는 시간이 지연된다.That is, when a crack occurs from the left side of the solder ball 20 as shown in FIG. 8, the crack does not pass through the intermetallic compounds 21 and 22 having a very high hardness as shown in FIG. 9. Therefore, as shown in FIG. 10, the crack is directed to the right side of the solder ball 20 by bypassing the intermetallic compounds 21 and 22. Therefore, the crack length is increased by the intermetallic compounds 21 and 22, and as a result, the time for the solder ball 20 to completely break is delayed.
이상에서 설명한 바와 같이 본 발명에 의하면, 균열이 통과하지 못할 정도로 경도가 높은 금속간 화합물의 성장 두께를 적절히 제어하므로써, 비록 솔더 볼에 균열이 발생되어도, 균열 길이가 금속간 화합물에 의해 늘어나게 된다. 따라서, 균열이 솔더 볼을 횡단하여 솔더 볼을 완전히 파단시키기까지의 시간이 지연되므로써, 패키지와 기판의 접찹력이 강화된다.As described above, according to the present invention, the crack length is increased by the intermetallic compound even if a crack occurs in the solder ball by appropriately controlling the growth thickness of the intermetallic compound having a high hardness such that the crack cannot pass. Therefore, the time until the crack crosses the solder ball and completely breaks the solder ball is delayed, thereby enhancing the adhesive force between the package and the substrate.
이상에서는 본 발명에 의한 실장 방법을 실시하기 위한 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.In the above, although the preferred embodiment for carrying out the mounting method according to the present invention has been illustrated and described, the present invention is not limited to the above-described embodiment, and the present invention is not limited to the scope of the present invention as claimed in the following claims. Various modifications can be made by those skilled in the art to which the invention pertains.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980058920A KR20000042669A (en) | 1998-12-26 | 1998-12-26 | Mounting method of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980058920A KR20000042669A (en) | 1998-12-26 | 1998-12-26 | Mounting method of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000042669A true KR20000042669A (en) | 2000-07-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980058920A KR20000042669A (en) | 1998-12-26 | 1998-12-26 | Mounting method of semiconductor package |
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| KR (1) | KR20000042669A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100659527B1 (en) * | 2003-10-22 | 2006-12-20 | 삼성전자주식회사 | Semiconductor chip having three dimension type ubm for flip chip bonding and mounting structure thereof |
| KR100729050B1 (en) * | 2000-12-29 | 2007-06-14 | 앰코 테크놀로지 코리아 주식회사 | Land structure of semiconductor package and its manufacturing method |
-
1998
- 1998-12-26 KR KR1019980058920A patent/KR20000042669A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100729050B1 (en) * | 2000-12-29 | 2007-06-14 | 앰코 테크놀로지 코리아 주식회사 | Land structure of semiconductor package and its manufacturing method |
| KR100659527B1 (en) * | 2003-10-22 | 2006-12-20 | 삼성전자주식회사 | Semiconductor chip having three dimension type ubm for flip chip bonding and mounting structure thereof |
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