KR20050036623A - Driving method of plasma display panel - Google Patents

Abstract

In the driving method of the plasma display panel, a falling ramp voltage is applied to the scan electrode to initialize the wall charge state of the discharge cell in the reset period. At this time, while the falling ramp voltage is applied, the voltage of the scan electrode is fixed for a period of time when the voltage between the scan electrode and the address electrode becomes the discharge start voltage. Next, the falling ramp voltage is subsequently applied to the scan electrodes. In this way, strong discharge that can be caused by the discharge delay between the scan electrode and the address electrode can be prevented.

Description

Driving method of plasma display panel and plasma display device {DRIVING METHOD OF PLASMA DISPLAY PANEL}

The present invention relates to a method of driving a plasma display panel (PDP) and a plasma display device.

A plasma display panel is a flat display device that displays characters or images by using plasma generated by gas discharge, and tens to millions or more of pixels are arranged in a matrix form according to their size. First, the structure of the plasma display panel will be described with reference to FIGS. 1 and 2.

1 is a partial perspective view of a plasma display panel, and FIG. 2 shows an electrode arrangement diagram of the plasma display panel.

As shown in FIG. 1, the plasma display panel includes two glass substrates 1 and 6 facing each other apart. On the glass substrate 1, the scan electrode 4 and the sustain electrode 5 are formed in pairs and in parallel, and the scan electrode 4 and the sustain electrode 5 are covered with the dielectric layer 2 and the protective film 3. have. A plurality of address electrodes 8 are formed on the glass substrate 6, and the address electrodes 8 are covered with the insulator layer 7. The address electrode 8 and the partition 9 are formed on the insulator layer 7 between the address electrodes 8. In addition, the phosphor 10 is formed on the surface of the insulator layer 7 and on both sides of the partition wall 9. The glass substrates 1 and 6 are disposed to face each other with the discharge space 11 therebetween so that the scan electrode 4, the address electrode 8, the sustain electrode 5, and the address electrode 8 are orthogonal to each other. The discharge space 11 at the intersection of the address electrode 8 and the paired scan electrode 4 and the sustain electrode 5 forms a discharge cell 12.

As shown in FIG. 2, the electrode of the plasma display panel has a matrix structure of n × m. The plurality of address electrodes A ₁ -A _m are arranged in the vertical direction, and the plurality of scan electrodes Y ₁ -Y _n and the storage electrodes X ₁ -X _n are arranged in pairs in the horizontal direction.

In general, a plasma display panel is driven by dividing one frame into a plurality of subfields, and gray levels are expressed by a combination of subfields. In general, each subfield includes a reset period, an address period, and a sustain period. The reset period serves to erase the wall charges formed by the previous sustain discharge and to set up the wall charges in order to stably perform the next address discharge. The address period is a period in which a wall charge is accumulated in a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on in the panel. The sustain period is a period in which sustain discharge is performed to actually display an image in the addressed cells.

As shown in Fig. 3, the reset period consists of a rising ramp period and a falling ramp period. In the ramp-down period, a ramp voltage gradually dropping toward the voltage V _s at 0V in the sustain electrodes (X) to V _e voltage state to the scan electrode (Y). A weak discharge occurs between the scan electrode Y and the sustain electrode X while this ramp voltage is falling, and a weak discharge occurs between the scan electrode Y and the address electrode A afterwards. As a result, the negative wall charges of the scan electrode Y decrease and the positive wall charges of the sustain electrode X and the address electrode A decrease.

At this time, in the conventional waveform, the voltage between the scan electrode Y and the address electrode A exceeds the discharge start voltage while the weak discharge occurs between the scan electrode Y and the sustain electrode X in the falling ramp period. The weak discharge is started between the electrode Y and the address electrode A. FIG. However, as shown in FIG. 1, since the scan electrode Y and the address electrode A are formed to face each other with a large area, a discharge delay may occur between the scan electrode Y and the address electrode A. FIG.

Due to such a discharge delay, the weak discharge between the scan electrode Y and the address electrode A does not occur at the time when the discharge start voltage is reached, and the time point at which the voltage difference between the two electrodes Y and A becomes larger than the discharge start voltage. Happens in That is, when a discharge occurs between the scan electrode Y and the address electrode A, a strong discharge may occur between the two electrodes Y and A since the voltage difference between the two electrodes is greater than the discharge start voltage. When a strong discharge occurs between the two electrodes Y and A, a large amount of wall charges are erased, so that address discharge may not occur properly in the address period A. FIG.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of driving a plasma display panel that can easily cause an address discharge.

In order to solve this problem, the present invention fixes the voltage of the scan electrode for a period of time when the voltage between the scan electrode and the address electrode becomes the discharge start voltage in the falling ramp period.

According to one aspect of the invention, it comprises a plurality of first and second electrodes formed side by side on the first substrate, and a plurality of third electrodes formed on the second substrate and intersect the first and second electrodes, The present invention provides a method of driving a plasma display panel in which discharge cells are formed by adjacent first electrodes, second electrodes, and third electrodes. The driving method includes gradually lowering the voltage of the first electrode from the first voltage to the second voltage during the reset period, fixing the voltage of the first electrode to substantially the second voltage, and of the first electrode. Gradually lowering the voltage from the second voltage to the third voltage.

According to an embodiment of the present invention, the address discharge may occur due to the voltage difference between the first electrode and the third electrode during the address period.

According to another embodiment of the present invention, the second voltage may be a voltage having a magnitude that can substantially initiate a discharge between the first electrode and the third electrode during the reset period.

According to another embodiment of the present invention, the second voltage may be a voltage having substantially the same magnitude as the voltage applied to the third electrode during the reset period.

According to another embodiment of the present invention, the second voltage may be substantially 0V.

According to another embodiment of the present invention, while the first electrode is lowered from the first voltage to the third voltage, the second electrode and the third electrode may be maintained at a constant voltage, respectively.

According to another embodiment of the present invention, the voltage of the first electrode can be fixed to the second voltage by applying the second voltage to the first electrode.

According to another embodiment of the present invention, while the first electrode is lowered from the first voltage to the third voltage, the second electrode and the third electrode are maintained at a constant voltage, respectively, by floating the first electrode to The voltage can be fixed at substantially the second voltage.

According to another embodiment of the present invention, the voltage of the first electrode may be gently lowered with at least one slope from the first voltage to the second voltage and from the second voltage to the third voltage.

According to another embodiment of the present invention, the first electrode, the second electrode and the third electrode may be a scan electrode, a sustain electrode and an address electrode, respectively.

According to another feature of the present invention, a plasma including a plurality of first and second electrodes formed on the first substrate, and a plurality of address electrodes formed on the second substrate and crossing the first and second electrodes, respectively. A plasma display device including a display panel and a driving circuit for applying a driving signal to a first electrode, a second electrode, and a third electrode are provided. The driving circuit sets the voltage of the first electrode to the second voltage during the first period in order to set the wall charge state of the discharge cells formed by the first electrode, the second electrode, and the third electrode to an addressable state. The voltage is gradually lowered to a voltage, a second voltage is applied to the first electrode during the second period, and the voltage of the first electrode is gradually lowered from the second voltage to the third voltage during the third period.

According to another feature of the present invention, a plurality of first and second electrodes are formed on the first substrate side by side, and a plurality of address electrodes formed on the second substrate and cross the first and second electrodes A plasma display device including a plasma display panel and a driving circuit for applying a driving signal to a first electrode, a second electrode, and a third electrode are provided. The driving circuit sets the voltage of the first electrode to the second voltage during the first period in order to set the wall charge state of the discharge cells formed by the first electrode, the second electrode, and the third electrode to an addressable state. The voltage is gradually lowered to the voltage, the first electrode is floated for the second period, and the voltage of the first electrode is gradually lowered to the third voltage for the third period.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

4 is a driving waveform diagram of the plasma display panel according to the first exemplary embodiment of the present invention, and FIG. 5 is an enlarged view of the falling ramp period in the driving waveform of FIG. 4. 6 is an enlarged view of a falling ramp period in a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

4, each of the subfields in the driving waveform according to a first embodiment of the present invention includes a reset period (P _r), an address period (P _a), and a sustain period (P _s). The reset period P _r is made up of the rising ramp period P _r1 and the falling ramp period P _r2 .

The rising ramp period P _r1 of the reset period P _r is a period for forming wall charges in the scan electrode Y, the sustain electrode X, and the address electrode A, and the falling ramp period P _r2 rises. The wall charges formed in the lamp period P _r2 are partially erased to facilitate address discharge. An address period (P _a) is a period for selecting a discharge cell to cause sustain discharge in a sustain period of the plurality of discharge cells. Sustain period (P _s) is a period for maintaining discharge in the discharge cells selected by applying a sustain pulse in turn to the scan electrode (Y) and the sustain electrode (X) during the address period (P _a).

In the plasma display panel, a scan / hold driving circuit which applies a driving voltage to the scan electrode Y and the sustain electrode Y in each of the periods P _r , P _a , and P _s , and a driving voltage to the address electrode A, respectively. An address driving circuit for applying a is connected to form one display device.

First, in the rising ramp period P _r1 of FIG. 4, the V _set voltage higher than the discharge start voltage at the voltage V _s of the scan electrode Y while 0 V voltage is applied to the sustain electrode X and the address electrode A. FIG. Ramp waveform is applied until it rises slowly. Then, a weak discharge occurs between the scan electrode (Y) and the sustain electrode (X) in all the discharge cells while the ramp waveform rises, and then a weak discharge occurs between the scan electrode (Y) and the address electrode (A). As a result, negative wall charges are stored in the scan electrode Y, and positive wall charges are stored in the address electrode A and the sustain electrode X. As shown in FIG. In other words, wall charges are accumulated in the protective layer 3 covering the scan electrode Y and the sustain electrode X and the insulator layer 7 covering the address electrode A, but the scan electrode Y is described below for convenience. ), The wall charges are accumulated in the sustain electrode X and the address electrode A. FIG.

Next, Figure 4 and looking at Fig. 5, descent initially in a first period (T1) of the light period (P _r2) the ramp waveform gently lowered to V _p the voltage at V _s the voltage is applied to the scan electrode (Y) . The positive voltage _Ve is applied to the sustain electrode X, and 0 V is continuously applied to the address electrode A. FIG. Here, the voltage V _p is substantially the voltage applied to the scan electrode Y when the voltage between the scan electrode Y and the address electrode A becomes the discharge start voltage V _{f_AY} . The discharge start voltage V _{f_AY} is formed between the two electrodes Y and A together with the wall voltage caused by the wall charges formed on the two electrodes Y and A with the voltages applied to the scan electrode Y and the address electrode A. This is the voltage that can cause a discharge at. Similarly, the discharge start voltage V _{f_XY} described below includes two electrodes ( _W ) with the wall voltage due to the wall charges formed on the two electrodes Y and X by the voltages applied to the scan electrode Y and the sustain electrode A. It is a voltage that can cause a discharge between Y and X).

If the voltage between the scan electrode Y and the sustain electrode X exceeds the discharge start voltage V _{f_XY} during the voltage applied to the scan electrode Y in the first period T1, the scan electrode Y About discharge continues between the sustain electrode X and the sustain electrode X, and wall charges accumulated on the scan electrode Y and the sustain electrode X are erased. In the first period T1, since the voltage between the scan electrode Y and the address electrode A does not exceed the discharge start voltage V _{f_AY} , no discharge occurs between the scan electrode Y and the address electrode A. .

In the second period T2 of the falling ramp period P _r3 , the voltage V _p is continuously applied to the scan electrode Y. Then, since the voltage of the scan electrode Y no longer drops, no discharge occurs between the scan electrode Y and the sustain electrode X. When the voltage of the scan electrode Y is V _{p, the} voltage between the scan electrode Y and the address electrode A is the discharge start voltage V _{f_AY} , and thus, between the scan electrode Y and the address electrode A. Weak discharge occurs. However, as described above, since there is a discharge delay between the scan electrode Y and the address electrode A, no discharge occurs at the beginning of the second period T2, and the discharge is discharged in the middle of the second period T2 due to the discharge delay. This happens. In this manner, even when the discharge is generated between the scan electrode Y and the address electrode A due to the discharge delay, the voltage between the two electrodes Y and A is maintained at the discharge start voltage V _{f_AY} . A strong discharge does not occur between Y and A), but a weak discharge occurs.

Next, in the third period T3 of the falling ramp period P _r2 , a ramp waveform falling from the voltage V _{p to the} voltage V _n is applied to the scan electrode Y. Then, the weak discharge is started again between the scan electrode Y and the sustain electrode X. Further, in the second period T2, the particles generated by the weak discharge between the scan electrode Y and the address electrode A are primed, so that the weak discharge smoothly occurs between the scan electrode Y and the address electrode A. FIG. Happens. Through such weak discharges, wall charges of the scan electrode Y, the sustain electrode X, and the address electrode A are erased to a state suitable for causing an address discharge in the address period.

Next, in the address period _Pa , while the other scan electrode Y is maintained at the V _sc voltage, the scan electrode Y is sequentially selected by applying the voltage V _n to the scan electrode Y. And it is applied to the address voltage (V _a) to the address electrode (A) to form a discharge cell to be selected among the discharge cells formed by the scan electrode (Y) is applied to the voltage V _n. Then, the voltage applied to the address electrodes (A) (V _a) and the wall voltage due to the wall charges formed on the difference and the address electrode (A) and scan electrodes (Y) of the voltage (V _n) applied to the scan electrode (Y) This causes address discharge.

In the sustain period P _s , a sustain pulse is sequentially applied to the scan electrode Y and the sustain electrode X. A sustain pulse is a pulse to the scan electrode (Y) and the sustain electrode (X) to a voltage difference shift voltage V _s and -V _s to the voltage. The voltage V _{s is a} voltage lower than the discharge start voltage between the scan electrode Y and the sustain electrode X. If the address period (P _a), the wall voltage between the scan electrode (Y) and the sustain electrode (X) by the address discharge are formed on the scan electrode by the wall voltage and V _s the voltage (Y) and the sustain electrode (X) Discharge occurs at.

In the first embodiment of the present invention, since the voltage V _p is the voltage at the time when the discharge is started between the scan electrode Y and the address electrode A, it can be measured through an experiment. According to the principle of the weak discharge, at the end of the rising ramp period P _r1 , the wall voltage formed on the address electrode A and the scan electrode Y starts the discharge between the address electrode A and the scan electrode Y. It is substantially the same as the voltage V _{f_AY} . Since the positive wall voltage is formed on the address electrode A and the negative wall voltage is formed on the scan electrode Y, the voltage of the scan electrode Y decreases and the scan electrode Y and the address electrode are externally. When the difference between the voltages applied to (A) becomes 0 V, the voltage between the two electrodes Y and A becomes the discharge start voltage V _{f_AY} again. Therefore, the V _p voltage may be a voltage at a time point at which the voltage applied to the scan electrode Y is substantially the same as the voltage applied to the address electrode A. FIG. In the waveform of FIG. 4, the voltage V _p becomes a voltage close to 0V.

In the first embodiment of the present invention, the voltage V _p is applied to the scan electrode Y in the second period T2 of the falling ramp period P _r2 , but unlike FIG. 6, the voltage V _p is applied during the second period T2. The scan electrode Y can be floated. Referring to FIG. 6, in the driving waveform according to the second embodiment of the present invention, the voltage is cut off from the scan electrode Y during the second period T2 of the falling ramp period P _r2 . At this time, since a constant voltage is continuously applied to the sustain electrode X and the address electrode A, the voltage applied to the scan electrode Y does not change even when the scan electrode Y is floated. Therefore, the driving waveform of FIG. 6 also has the same effect as the driving waveform of FIG. 5.

In the first and second embodiments of the present invention, although 0 V is applied to the address electrode A in the reset period P _r , a voltage other than 0 V is applied to the address electrode A depending on the voltage range used. May be authorized.

In the first and second embodiments of the present invention, the waveform of applying the falling ramp waveform after applying the rising ramp waveform in the reset period has been described. Alternatively, the rising ramp only in the reset period of at least one subfield in one frame. The waveform and the falling ramp waveform may be applied, and only the falling ramp waveform may be applied in the reset period of another subfield.

In addition, in the first and second embodiments of the present invention, the rising waveform and the falling waveform applied to the reset period P _r are ramp waveforms. Alternatively, a round waveform such as a log waveform or an RC waveform may be used. In addition, the slope may change while the ramp waveform rises or falls. In addition, the floating may be repeatedly applied to the scan electrode Y in the reset period P _r , which will be described below in detail with reference to FIG. 7.

7 is an enlarged view of a falling ramp period in a driving waveform diagram of a plasma display panel according to a third exemplary embodiment of the present invention.

As shown in FIG. 7, in the driving waveform according to the third embodiment of the present invention, the falling ramp waveform applied to the scan electrode Y in the reset period P _r is reduced after the voltage is lowered by a predetermined voltage. ) Is repeated for a certain period of time. In other words, the voltage applied to the scan electrode Y is lowered by a predetermined voltage and the operation of floating the scan electrode Y by cutting off the voltage supplied to the scan electrode Y is repeated.

If the discharge occurs in the discharge cell by the voltage applied to the scan electrode Y while this operation is repeated, the wall charges formed in the discharge cell are erased. When the scan electrode Y is floated after the discharge is started, even when a small amount of wall charges are lost in the discharge cell, the voltage in the discharge cell is rapidly decreased to eliminate the discharge. When the voltage of the scan electrode Y drops by a predetermined voltage, the discharge starts. When the scan electrode Y floats after the discharge starts, the voltage inside the discharge cell decreases rapidly and the discharge disappears. The charge is erased. In other words, it is possible to precisely control the amount of wall charges erased.

By repeating the floating operation after applying the falling voltage to the scan electrode Y as described above, it is possible to control the desired state while erasing the wall charge inside the discharge cell little by little. That is, the wall charge can be precisely erased by repeating the operation of erasing a small amount of the wall charge at a time.

In the following, strong discharge dissipation due to floating will be described in detail with reference to FIGS. 8A to 8D. Since the discharge occurs between the sustain electrode X and the scan electrode Y, the discharge cell will be described based on the sustain electrode X and the scan electrode Y.

FIG. 8A is a diagram illustrating a discharge cell formed by the sustain electrode and the scan electrode, and FIG. 8B is an equivalent circuit diagram of FIG. 8A. FIG. 8C is a diagram illustrating a state in which an external voltage is applied to the discharge cell of FIG. 8A. FIG. 8D is a diagram illustrating a floating state when discharge occurs in the discharge cell of FIG. 8A. In FIG. 8A, the scan electrode 4 and the sustain electrode 5 are initially provided for convenience of explanation. And + It is assumed that a charge of is formed. The charge is formed on the dielectric layer of the electrode, but will be described below as being formed on the electrode for convenience of description.

As shown in FIG. 8A, the scan electrode 4 is electrically connected to the externally applied voltage V _in through the switch SW, and the sustain electrode 5 is electrically connected to the V _h voltage. A dielectric layer 2 is formed inside the scan electrode 4 and the sustain electrode 5, respectively. Discharge gas (not shown) is injected between the dielectric layers 2, and a region between the dielectric layers 2 forms a discharge space 11.

In this case, since the scan and sustain electrodes 4 and 5, the dielectric layer 2, and the discharge space 11 form a capacitive load, they can be equivalently represented by the panel capacitor C _p as shown in FIG. 8B. And the dielectric constant of the two dielectric layers 2 The voltage across the discharge space 11 is referred to as V _g . The thickness of the two dielectric layers 2 is equal (d ₁ ), and the distance (distance of the discharge space) between the two dielectric layers 2 is d ₂ .

First, referring to FIG. 8C, the voltage V _g1 inside the discharge space at the time when the switch SW is turned on and the external voltage V _in is applied to the scan electrode 4 (that is, when the discharge is not started) is performed. Calculate At this time, the scan electrode 4 and the sustain electrode 5 are respectively- And + Assume that as much charge is applied. Applying the Gaussian law of the internal dielectric layer 2, the electric field (E ₁₎ and the electric field in the discharge space (11) (E ₂₎ is given by the respective expressions (1) and (2).

here, Is the dielectric constant inside the discharge space.

The voltage V _e -V _in applied to the outside is represented by Equation 3 by the relationship between the electric field and the distance, and from Equations 1 to 3, the voltage inside the discharge space is expressed by Equation 4.

Where V _w is the wall charge in the discharge space 11 ( With voltage formed by Where α is to be.

Next, discharge occurs between the scan electrode 4 and the sustain electrode 5 by the voltage V _in applied to the scan electrode 4 from the outside. As shown in Fig. 8D, the wall charges formed on the scan electrode 4 and the sustain electrode 5 by discharge are The switch SW is turned off and then the scan electrode 4 is floated.

Then, since no charge flows from the outside in the floating state, the amount of charge applied to the scan electrode 4 and the sustain electrode 5 is also- And + Is maintained. At this time, by applying the Gaussian law of the dielectric layer (2) of the internal electric field (E ₁₎ and the electric field in the discharge space (11) (E ₂₎ it is given by the respective expressions (1) and 5.

When the voltage V _{g2 in the} discharge space is calculated from Equations 5 and 4, Equation 6 is obtained.

As can be seen from Equation 6, it can be seen that there is a voltage drop due to the wall charge that disappears when the switch SW is turned off (floating state). As a result, in the floating state, even if the wall charges are slightly dissipated, the voltage in the discharge space 11 decreases abruptly, so that the voltage between the electrodes becomes less than or equal to the discharge start voltage.

As described above, in the third embodiment of the present invention, the falling ramp waveform in the form of repeating voltage application and floating in the reset period is applied to the scan electrode Y to precisely control the wall charge. In this way, since the discharge is extinguished by eliminating the wall charge much less than before, fine control of the wall charge is possible. In addition, the reset by the ramp waveform which is continuously falling gently controlled the wall charge by preventing the strong discharge by gently lowering the voltage applied to the discharge space through a constant voltage change amount. In the case of such a lamp voltage, since the intensity of the discharge is controlled by the slope of the lamp, the lamp voltage slope constraint for the wall charge control is very strong, so that the time required for reset is lengthened. On the contrary, in the case of the reset using floating as in the third embodiment, the time required for the reset can be shortened because the intensity of discharge is used as the voltage drop principle according to the erasure of the wall charge.

And the first and second embodiments and similarly continue V _p the voltage to the scan electrode (Y) during the time the voltage of the scan electrode (Y) that is the voltage V _p a period of time (T2) in the third embodiment of the present invention May be applied or the scan electrode Y may be floated.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, according to the present invention, strong discharge that can occur between the address electrode and the scan electrode in the reset period can be prevented. As a result, address discharge can occur smoothly.

1 is a schematic partial perspective view of a plasma display panel.

2 is an electrode array diagram of a plasma display panel.

3 is a driving waveform diagram of a plasma display panel according to the related art.

4 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

FIG. 5 is an enlarged view of a falling ramp period in the driving waveform of FIG. 4.

6 and 7 are enlarged views of the falling ramp periods in the driving waveform diagrams of the plasma display panel according to the second and third embodiments of the present invention, respectively.

8A is a diagram illustrating a discharge cell formed by a sustain electrode and a scan electrode.

8B is an equivalent circuit diagram of FIG. 8A.

FIG. 8C is a diagram illustrating a state in which an external voltage is applied to the discharge cell of FIG. 8A.

FIG. 8D is a diagram illustrating a floating state when discharge occurs in the discharge cell of FIG. 8A.

Claims (16)

A plurality of first electrodes and second electrodes formed on the first substrate, and a plurality of third electrodes formed on the second substrate and crossing the first and second electrodes, respectively; A method of driving a plasma display panel in which discharge cells are formed by second and third electrodes, During the reset period, Gradually lowering the voltage of the first electrode from the first voltage to the second voltage, Fixing the voltage of the first electrode to the second voltage substantially, and Gradually lowering the voltage of the first electrode from the second voltage to a third voltage Method of driving a plasma display panel comprising a. The method of claim 1, A method of driving a plasma display panel in which an address discharge occurs due to a voltage difference between the first electrode and the third electrode during an address period. The method of claim 1, And the second voltage is a voltage having a magnitude that can substantially initiate discharge between the first electrode and the third electrode during the reset period. The method of claim 1, And the second voltage is a voltage having substantially the same magnitude as a voltage applied to the third electrode during the reset period. The method of claim 1, And the second voltage is substantially 0V. The method according to any one of claims 1 to 5, While the first electrode falls from the first voltage to the third voltage, And the second electrode and the third electrode are respectively maintained at a constant voltage. The method according to any one of claims 1 to 5, And applying the second voltage to the first electrode to fix the voltage of the first electrode substantially to the second voltage. The method according to any one of claims 1 to 5, While the first electrode is lowered from the first voltage to the third voltage, the second electrode and the third electrode are respectively maintained at a constant voltage, And floating the first electrode to fix the voltage of the first electrode substantially to the second voltage. The method according to any one of claims 1 to 5, And a voltage of the first electrode is gently lowered with at least one slope from the first voltage to the second voltage and from the second voltage to the third voltage. The method according to any one of claims 1 to 4, And the first electrode, the second electrode, and the third electrode are a scan electrode, a sustain electrode, and an address electrode, respectively. A plasma display panel including a plurality of first and second electrodes formed on the first substrate, and a plurality of address electrodes formed on the second substrate and crossing the first and second electrodes, respectively; A driving circuit for applying a driving signal to the first electrode, the second electrode, and the third electrode; The driving circuit is configured to set the wall charge state of the discharge cells formed by the first electrode, the second electrode, and the third electrode to an addressable state, Gradually lowering the voltage of the first electrode from the first voltage to the second voltage during the first period, Applying the second voltage to the first electrode for a second period of time, And drop the voltage of the first electrode gradually from the second voltage to the third voltage during a third period. A plasma display panel including a plurality of first and second electrodes formed on the first substrate, and a plurality of address electrodes formed on the second substrate and crossing the first and second electrodes, respectively; A driving circuit for applying a driving signal to the first electrode, the second electrode, and the third electrode; The driving circuit is configured to set the wall charge state of the discharge cells formed by the first electrode, the second electrode, and the third electrode to an addressable state, Gradually lowering the voltage of the first electrode from the first voltage to the second voltage during the first period, Float the first electrode for a second period of time, And gradually lowering the voltage of the first electrode to the third voltage during a third period of time. The method according to claim 11 or 12, wherein And the second voltage is a voltage having a magnitude that can substantially initiate discharge between the first electrode and the address electrode. The method according to claim 11 or 12, wherein And the second voltage is a voltage having substantially the same magnitude as a voltage applied to the address electrode during the second period. The method according to claim 11 or 12, wherein And the second voltage is substantially 0V. The method according to claim 11 or 12, wherein During the first, second and third periods of time, And the second electrode and the address electrode are each maintained at a constant voltage.