KR20040110695A - Apparatus and method for driving gate lines of liquid crystal display panel - Google Patents

Abstract

PURPOSE: An apparatus and a method for driving a gate of a liquid crystal panel are provided to reduce size of the liquid crystal panel by using a decoder to drive gate lines sequentially. CONSTITUTION: A gate drive IC(Integrated Circuit)(32) generates a plurality of gate driving signals and a multiplicity of control signals. Decoders(D1,D2,...,Dj) divide gate lines into plural blocks and provide the gate driving signals to the gate lines of corresponding blocks by being selected by each of the control signals at a different period. The number of the gate driving signals is k (a positive integer) and the number of the control signals is j (a positive integer). A sum of the number of the gate driving signals and the control signals is less than the number of the gate lines. The k x j gate lines are driven by using the k gate driving signals and the j control signals.

Description

Gate driving device and method of liquid crystal panel {APPARATUS AND METHOD FOR DRIVING GATE LINES OF LIQUID CRYSTAL DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a gate driving device and a method of a liquid crystal panel capable of compacting by reducing the number of output channels while ensuring device reliability due to stress of a driving circuit embedded in the liquid crystal panel.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel having a pixel matrix and a driving circuit for driving the liquid crystal panel.

Specifically, the liquid crystal display includes a liquid crystal panel 2 having a pixel matrix as shown in FIG. 1, a gate driver 4 for driving gate lines GL1 to GLn of the liquid crystal panel 2, A data driver 6 for driving the data lines DL1 to DLm of the liquid crystal panel 2, and a timing controller 8 for controlling the driving timing of the gate driver 4 and the data driver 6. do.

The liquid crystal panel 2 includes a pixel matrix composed of pixels 12 formed at regions defined by intersections of the gate lines GL and the data lines DL. Each of the pixels 12 includes a liquid crystal cell Clc for adjusting light transmittance according to a pixel signal, and thin film transistors TFT for driving the liquid crystal cell Clc.

The thin film transistor TFT is turned on when the gate driving signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell Clc. . The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell Clc.

The liquid crystal cell Clc is equivalently represented by a capacitor and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to the thin film transistor TFT. In addition, the liquid crystal cell Clc further includes a storage capacitor (not shown) so that the charged pixel signal is stably maintained until the next pixel signal is charged. In the liquid crystal cell Clc, an array state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, thereby adjusting grayscale.

The gate driver 4 shifts the gate start pulse GSP from the timing controller 8 according to the gate shift clock GSC to sequentially gate the gate lines GL1 to GLm. Supply a scan pulse of high voltage (VGH). The gate driver 14 supplies the gate low voltage VGL to the gate lines GL in the remaining periods during which the scan pulse of the gate high voltage VGH is not supplied. The gate driver 4 includes a plurality of gate driving integrated circuits (ICs) to divide and drive the gate lines GL1 to DLn.

The data driver 6 shifts the source start pulse SSP from the timing controller 8 in accordance with the source shift clock SSC to generate a sampling signal. In addition, the data driver 6 latches the pixel data RGB input according to the source shift clock SSC according to the sampling signal, and then relies on a line unit in response to a source output enable (SOE) signal. To supply. The data driver 6 converts pixel data RGB, which is supplied in units of lines, into analog pixel signals by using different gamma voltages, and supplies them to the analog pixel signals. Here, the data driver 6 determines the polarity of the pixel signal in response to the polarity control signal POL from the timing controller 8 when converting the pixel data into the pixel signal. The data driver 6 includes a plurality of data driving ICs for dividing and driving the data lines DL1 to DLm.

The timing controller 8 generates a gate start pulse GSP and a gate shift clock GSC for controlling the gate driver 4, and a source start pulse SSP and a source shift clock for controlling the data driver 6. (SSC), source output enable signal SOE, polarity control signal POL, and the like. In this case, the timing controller 8 transmits a data enable (DE) signal, a horizontal sync signal (Hsync), a vertical sync signal (Vsync), and pixel data (RGB) indicating a valid data section input from the outside. Control signals such as the GSP, GSC, GOE, SSP, SSC, SOE, and POL are generated by using a dot clock (DCLK) that determines timing.

The liquid crystal display is mainly used as a monitor of a computer, a display of a TV, a mobile phone and the like. In the liquid crystal display device applied to the mobile phone, the drive ICs 14, 16, and 18 are directly mounted on the liquid crystal panel 20 as shown in FIG. 2.

2 illustrates a conventional driving circuit-mounted liquid crystal panel. The driving circuit-integrated liquid crystal panel 20 shown in FIG. 2 includes an image display unit 15 having a pixel matrix and first and second gate drive ICs 14 and 18 formed in a non-display area except for the image display unit 15. ) And a data drive IC 16.

The first gate drive IC 14 drives odd gate lines GL1, GL3,..., GLn-1 of the gate lines GL1 to DLn formed in the image display unit 15.

The second gate drive IC 18 drives the even gate lines GL2, GL4,... GLn among the gate lines GL1 to GLn formed in the image display unit 15.

The data drive IC 16 drives the data lines DL1 to DLm formed in the image display unit 15.

The drive ICs 14, 16, and 18 are typically mounted in a non-display area on the screen display unit 15 in a chip on glass (COG) or chip on film (COF) method. Here, the first and second gate drive ICs 14 and 18 are symmetrically disposed about the data drive IC 16. Accordingly, the non-display area in which the gate lines GL1 to GLn between the gate drive ICs 14 and 18 and the image display unit 15 are disposed can be reduced more than when only one gate drive IC is mounted. . However, two gate drive ICs are required, resulting in a problem of increased manufacturing costs.

Furthermore, as the resolution of the screen display unit 20 increases, the number of gate lines GL1 to GLn increases, and the number of output channels of the first and second gate drive ICs 14 and 18, that is, the gate lines ( The number of GL1 to GLn) is increased. In order to arrange the increased gate lines GL1 to GLn, the left and right non-display areas between the first and second gate drive ICs 14 and 18 and the image display unit 15 are increased. have. For example, the resolution of a 2-inch liquid crystal display for a mobile phone is progressing to a high resolution product of 240 * 3 * 320 (n = 320) pixel number from 176 * 3 * 220 pixel number. In this case, since 160 gate lines should be disposed in each of the left and right non-display areas between each of the first and second gate drive ICs 14 and 18 and the image display unit 15, the left and right non-display areas. This will greatly increase. As a result, there is a problem that the compactness of the mobile phone is hindered by the increase in the size of the mobile phone liquid crystal display.

In order to solve this problem, as shown in FIG. 3, a method of integrating the entire gate driver and directly forming the liquid crystal panel has been proposed. However, due to reliability problems of the drive ICs 14 and 18, a circuit life is shortened. there is a problem.

In general, the gate driver formed directly on the liquid crystal panel includes a shift register 22 having a plurality of stages ST1 to STn, an output line and gate lines of each of the stages ST1 to STn, as shown in FIG. An output buffer array 24 composed of output buffers 26 connected between each of GL1 to GLn.

The first stage ST1 of the shift register 24 receives the gate start pulse SP, and the second to n / 2 stages ST2 to ST (n / 2) output the output signal of the previous stage. Enter it. In addition, the stages ST1 to ST (n / 2) commonly input the first and second clock signals C and C /. Each of the stages ST1 to ST (n / 2) sequentially shifts the gate start pulse SP using the first and second clock signals C and C / to output a gate driving signal.

Each of the output buffers 26 included in the output buffer array 24 receives the gate driving signal output from each of the stages ST1 to ST (n / 2) and the first and second driving voltages VDD and VSS. The signal buffer is used to output to each of the gate lines GL1 to GLn.

The shift register 22 and the output buffer array 24 constituting the gate driver are implemented by a combination of a plurality of thin film transistors. However, when the thin film transistors for the gate driver are formed of amorphous silicon in the same manner as the thin film transistors of the image display unit 15, a circuit life problem occurs due to reliability problems. This is because a large change in the threshold voltage of a driver thin film transistor requiring high reliability occurs due to the current generated by hydrogen included in the amorphous silicon thin film transistor. As a result, it is difficult to integrate the gate driver and form it directly on the liquid crystal panel.

Accordingly, an object of the present invention is to provide a gate driving apparatus and method for a liquid crystal panel which can simplify the gate driver and ensure reliability.

1 is a view schematically showing a conventional liquid crystal display device.

2 is a diagram schematically showing a configuration of a conventional drive circuit mounted liquid crystal panel.

3 is a diagram illustrating an internal configuration of a conventional integrated gate driver.

4 is a diagram schematically illustrating a configuration of a liquid crystal panel including a gate driver according to an exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating a detailed configuration of the gate driver shown in FIG. 4. FIG.

FIG. 6 is a driving waveform diagram of the gate driver shown in FIG. 5; FIG.

7 is a view showing a detailed configuration of a gate driver according to another embodiment of the present invention.

8 is a view showing a detailed configuration of a gate driver according to another embodiment of the present invention.

9 is a control signal waveform diagram supplied to a gate driver shown in FIG. 8; FIG.

<Description of Symbols for Main Parts of Drawings>

2, 20, 30: liquid crystal panel 4: gate driver

6: data driver 12: pixel

14, 18, 32, 42, 52: gate drive IC

16, 34: data drive IC 22: shift register

24: buffer array 26: buffer

36: image display unit D1 to Dj, DD1 to DDj: decoder

ST1 to STn: stage

In order to achieve the above object, the gate driving device of the liquid crystal panel according to the present invention is a device for driving the gate lines of the liquid crystal panel, the gate drive integrated circuit for generating a plurality of gate driving signals and a plurality of control signals; ; And dividing the gate lines into a plurality of blocks, and having a plurality of decoders selected at different periods by each of the plurality of control signals to supply the plurality of gate driving signals to the gate lines of the corresponding block. It is done.

The sum of the number of gate driving signals and the number of control signals is smaller than the number of gate lines.

The k × j gate lines are driven using k (k is a positive integer) gate driving signals and j (j is a positive integer) control signals.

The number of the gate driving signals is set smaller than the number of the control signals.

The plurality of control signals may cause the plurality of decoders to be driven sequentially.

The plurality of gate driving signals may sequentially drive gate lines of a corresponding block selected by the decoder.

Each of the decoders is connected to each of the gate lines of the corresponding block, and each of the plurality of gate driving signals is respectively connected to each of the gate lines of the corresponding block in response to a control signal of any one of the plurality of control signals. It is characterized by comprising a plurality of switching elements for supplying.

And a plurality of off voltage applying transistors for supplying an off voltage to each of the gate lines during a period in which each of the gate lines maintains a gate low voltage among the gate driving signals.

The plurality of off voltage applying transistors may be connected in parallel with each of the gate lines.

The plurality of off voltage applying transistors may be divided in the same block unit as the gate lines, and driven in the block unit according to any one of the plurality of control signals.

The control signal supplied to the plurality of off voltage applying transistors in the unit of block is different from the control signal supplied to the decoder driving the gate lines of the corresponding block.

The gate driving integrated circuit may further supply a plurality of second control signals for driving the plurality of off voltage applying transistors in the block unit.

Each of the plurality of second control signals has an antiphase with a control signal supplied to a decoder connected to gate lines of a corresponding block among the control signals.

Each of the plurality of second control signals has a phase which is partially different from a plurality of control signals supplied to the decoder connected to gate lines of a corresponding block among the control signals.

The plurality of off voltage applying transistors may be built in each of the plurality of decoders in block units.

The gate driving integrated circuit is mounted in a non-display area of the liquid crystal panel, and the plurality of decoders are formed in the non-display area.

According to an aspect of the present invention, there is provided a method of driving a gate line of a liquid crystal panel, comprising: generating a plurality of gate driving signals and a plurality of control signals; Selecting the gate lines in units of blocks in different periods by each of the plurality of control signals; And supplying the plurality of gate driving signals to the selected gate lines block.

The plurality of control signals may cause the gate lines to be sequentially driven in block units.

The plurality of gate driving signals may drive the gate lines of the selected block sequentially.

Each of the plurality of gate driving signals is connected to each of the gate lines of the corresponding block, and the gate of the corresponding block passes through each of the plurality of switching elements that commonly respond to any one of the plurality of control signals. It is characterized by being supplied to each of the lines.

And supplying an off voltage to each of the gate lines while each of the gate lines maintains a gate low voltage among the gate driving signals.

The off voltage may be supplied to the gate lines in units of blocks of the gate lines through each of the off voltage applying transistors connected in parallel with each of the gate lines.

The off voltage applying transistors connected to any one of the gate lines supply the off voltage to the gate lines of the corresponding block in response to one of the plurality of control signals in common. do.

The control signal supplied to the off voltage applying transistors in block units has a phase different from that of the control signal used to supply the gate driving signal to the gate lines of the corresponding block.

And generating a plurality of second control signals for driving the plurality of off voltage applying transistors in the block unit.

Each of the plurality of second control signals has an inverse phase with a control signal used to supply the gate driving signal to gate lines of a corresponding block among the control signals.

Each of the plurality of second control signals has a phase that is partially different from a control signal used to supply the gate driving signal to gate lines of a corresponding block among the control signals.

Other objects and advantages of the present invention in addition to the above objects will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 9.

4 schematically illustrates a liquid crystal panel including a gate driving apparatus according to an exemplary embodiment of the present invention.

The liquid crystal panel shown in FIG. 4 has an image display section 36 having a pixel matrix, a gate drive IC 32 and a plurality of decoders D1 to Dj for driving the gate lines of the image display section 36. A gate driver and a data driver IC 32 for driving the data lines of the image display unit 36.

The image display unit 36 has a pixel matrix composed of pixels formed for each region defined by the intersection of the gate lines and the data lines. Each of the pixels includes a liquid crystal cell for adjusting the amount of light transmission according to the pixel signal, and a thin film transistor for driving the liquid crystal cell. The thin film transistor supplies a liquid crystal cell with a pixel signal from the data line in response to a gate driving signal from the gate line. Accordingly, the liquid crystal cell is driven according to the pixel signal supplied through the thin film transistor to adjust grayscale by adjusting the light transmittance.

The data drive IC 34 converts digital pixel data input from the outside into an analog pixel signal and supplies the same to the data lines. This data drive IC 34 is mounted in the non-display area above the image display unit 36.

The gate driver selects the gate drive ICs 32 for generating a plurality of gate driving signals S1 to Sk and a plurality of control signals C1 to Cj, and selects the gate driving signals S1 to Sk according to the control signals C1 to Cj to gate lines. And a plurality of decoders D1 to Dj that feed into the channels. The gate drive IC 32 is mounted in the non-display area above the image display unit 36 adjacent to the data drive IC 34. The decoders D1 to Dj are formed in the non-display area on the left or right side of the image display unit 36. Here, the gate drive IC 32 is mounted in the non-display area of the liquid crystal panel 30 together with the data drive IC 34 in the form of a separate IC, and the decoders D1 to Dj are together with the thin film transistors of the image display unit 36. It is formed in the non-display area.

The gate drive IC 32 generates gate drive signals S1 to Sk and supplies them to the decoders D1 to Dj in common through k output channels. In addition, the gate drive IC 32 generates the control signals C1 to Cj and supplies them to the decoders D1 to Dj through the j output channels, respectively.

The plurality of decoders D1 to Dj divide and drive the gate lines into blocks. For example, the plurality of decoders D1 to Dj divide and drive the gate lines GL11 to GLjk into j blocks by k as shown in FIG. 5. Each of the decoders D1 to Dj includes k switch elements for driving k gate lines. Specifically, decoder D1 is a switch SW11 to SW1k for driving the gate lines GL11 to GL1k of the first block, decoder D2 is a switch SW21 to SW2k for driving the gate lines GL21 to GL2k of the second block, and The decoder Dj has switches SWj1 to SWjk for driving the gate lines GLj1 to GLjk of the jth block.

Each of these decoders D1 to Dj commonly inputs the gate driving signals S1 to Sk output from the gate drive IC 32. Each of the decoders D1 to Dj is supplied to the corresponding gate lines by selecting the gate driving signals S1 to Sk in response to each of the control signals C1 to Cj output from the gate drive IC 32. In this case, the decoders D1 to Dj each input only one control signal of the control signals C1 to Cj. In other words, the switches SW11 to SW1k constituting the decoder D1 are controlled by the control signal C1, the switches SW21 to SW2k constituting the decoder D2 are controlled by the control signal C2, and the switches SWj1 to SWjk constituting the decoder Dj are the control signals Cj. Controlled by Here, each of the control signals C1 to Cj has a form in which the high state is sequentially shifted as shown in FIG. 6, for example, and has one frame 1F period. Accordingly, since the decoders D1 to Dj are each driven by the control signals C1 to Cj sequentially, they are driven only during the period when the corresponding control signal of one frame 1F is in the high state. In other words, the switches SW11 to SWjk constituting the decoders D1 to Dj are driven only during a period when the corresponding control signal becomes high, thereby reducing driving stress. As shown in FIG. 6, the gate driving signals S1 to Sk having the form in which the high states are sequentially shifted are repeatedly supplied for each of the high state periods of the control signals C1 to Ck.

Accordingly, as shown in FIG. 6, when the control signal C1 becomes high, the switches SW11 to SW1k of the decoder D1 are simultaneously turned on, and the gate driving signals S1 to Sk are supplied to the gate lines GL11 to GL1k of the first block, respectively. Subsequently, when the control signal C2 becomes high, the switches SW21 to SW2k of the decoder D2 are simultaneously turned on to supply the gate driving signals S1 to Sk to the gate lines GL21 to GL2k of the second block, respectively. When the control signal Cj becomes high, the switches SWj1 to SWjk of the decoder Dj are simultaneously turned on to supply the gate driving signals S1 to Sk to the gate lines GLj1 to GLjk of the j-th block, respectively. Here, the high state of the gate driving signals S1 to Sk is a gate high voltage for turning on the thin film transistor of the image display unit 36, and a low state for the gate driving signals S1 to Sk for turning off the thin film transistor. Is set.

Here, in order for the decoder switches SW11 to SWjk to sufficiently charge the gate driving signals S1 to Sk to the gate lines GL11 to GLjk, respectively, the turn-on voltage of the control signals C1 to Cj (that is, the high state voltage) is The threshold voltage must be at least higher than the high state of the gate driving signals S1 to Sk.

As described above, in the gate driver according to the present invention, the gate drive IC 32 includes (k + j) output channels for outputting the gate drive signals S1 to Sk and the control signals C1 to Cj. Each of the decoders D1 to Dj sequentially selects the gate line block according to the control signals C1 to Cj, and supplies the gate driving signals S1 to Sk to the gate lines of the selected block. In other words, the gate bent part according to the present invention can sequentially drive the jk gate lines GL11 to GLjk with (k + j) output channels of the gate drive IC 32 using the decoders D1 to Dj. . Accordingly, the number of output channels of the gate drive IC 32 can be reduced, thereby reducing the non-display area occupied by the output channel. For example, when the number k of the gate driving signals S1 to Sk is set to about 3 to 4, the number of output channels of the gate drive IC 32 can be reduced to about 1/3 compared to the conventional (n).

Here, as the number k of the gate driving signals S1 to Skj increases, there is a possibility that a signal delay occurs due to an increase in the capacitor connected to the supply lines of the gate driving signals S1 to Sk, so that the number of the gate driving signals S1 to Sk is increased. (k) is set smaller than the number j of the control signals C1 to Cj (j> k). Accordingly, the number k of gate lines included in each of the decoders D1 to Dj is also set smaller than the number j of decoders D1 to Dj for dividing the gate lines GL11 to GLjk in units of blocks (j> k).

7 illustrates a gate driver of a liquid crystal panel according to a second exemplary embodiment of the present invention. 7, transistors T11 to T1k, T21 to T2k, ..., Tj1 to Tjk for applying an off voltage Voff are added to each of the decoders DD1 to DDj in comparison with FIG. 5. 42 has the same components except that it additionally outputs an off voltage Voff. Therefore, detailed description of the components overlapping with FIG. 5 will be omitted.

The gate drive IC 42 supplies the off voltage Voff to the decoders DD1 to DDj together with the gate driving signals S1 to Sk and the control signals C1 to Cj.

After each of the decoders DD1 to DDj is selected by each of the control signals C1 to Cj, the gate lines GL11 to GL1k, GL21 to GL2k, ..., GLj1 to GLjk connected to each of the decoders DD1 to DDj are in a floating state. In addition, since a signal is not applied until the corresponding decoder is selected in the next frame, a problem may occur in which the gate low voltages of the gate lines GL11 to GLjk are changed by the leakage current. In order to prevent this, each of the decoders DD1 to DDj includes transistors T11 to T1k, T21 to T2k, ..., Tj1 to Tjk for applying an off voltage Voff connected in parallel with the gate line. The off-voltage applying transistors T11 to T1k, T21 to T2k, ..., Tj1 to Tjk are arranged inside the decoders DD1 to DDj as shown in FIG. 7, or are arranged outside, although not shown.

In detail, the decoder DD1 performs transistors T11 through T1k connected in parallel with each of the gate lines GL11 through GL1k of the first block, and the decoder DD2 uses transistors T21 through T2k for driving the gate lines GL21 through GL2k of the second block. And the decoder DDj further includes transistors Tj1 to Tjk for driving the gate lines GLj1 to GLjk of the jth block. The off-voltage applying transistors T11 to T1k, T21 to T2k, ..., Tj1 to Tjk are turned on by a different control signal at an appropriate time until the decoder is selected in the corresponding control signal and then selected in the next frame on a block basis. On to supply an off voltage Voff to the gate lines of the block. In this case, as a control signal for controlling the transistors T11 to T1k, T21 to T2k, ..., Tj1 to Tjk for the off-voltage Voff application in block units, the decoder switches SW11 to SW1k, SW21 to SW2k, ... , One of the control signals C1 to Cj used to select SWj1 to SWjk on a block basis. However, the control signal of the transistor for applying off voltage Voff and the control signal of the switch for decoder are not overlapped with each other.

For example, the switches SW11 to SW1k of the decoder DD1 are selected by the control signal C1 to supply the gate driving signals S1 to Sk to the gate lines GL11 to GL1k of the first block. The transistors T11 to T1k for applying the off voltage of the decoder DD1 are selected by the control signal Ci (here, i <j), which becomes high at an arbitrary point, for example, an intermediate point of the frame, so that the gate line of the first block is selected. By supplying the off voltage Voff to the GL11 to GL1k, the gate low voltage charged to the gate lines GL11 to GL1k can be stabilized. Here, the control signal Ci is also used to select switches SWi1 to SWik (not shown) of other decoders DDi (not shown).

As described above, the gate driver according to the present invention can reduce the number of output channels of the gate drive IC 42 and can stabilize the gate low voltages of the gate lines GL11 to GL1k by the transistor for applying the off voltage Voff. .

8 illustrates a gate driver of a liquid crystal panel according to a third exemplary embodiment of the present invention. In contrast to FIG. 7, the gate driver illustrated in FIG. 8 controls the control signal C for controlling the transistor for applying the off voltage Voff to the gate signals IC 1 to Cj for controlling the switch for the decoder. The same components are provided except for the additional supply of j + 1) to C2j. Therefore, detailed descriptions of the components overlapping with FIGS. 5 and 7 will be omitted.

The gate drive IC 52 stores the gate drive signals S1 to Sk, the off voltage Voff, the switch control signals C1 to Cj for the decoder, and the transistor control signals C (j + 1) to C2j for applying the off voltage Voff. Supply to decoders DD1 to DDj. Here, each of the transistor control signals C (j + 1) to C2j has an inverse phase with each of the switch control signals C1 to Cj as shown in FIG. 9. Or each of the transistor control signals C (j + 1) to C2j has a high state that partially overlaps the low state of each of the switch control signals C1 to Cj.

For example, the high state of the control signal C (j + 1) for selecting the transistors T11 to T1k of the decoder DD1 is set so as not to overlap with the high state of the control signal C1 supplied to the switches SW11 to SW1k of the decoder DD1. In other words, the control signal C (j + 1) is set to have a high state which overlaps or partially overlaps with the period during which the control signal Ci is low. Accordingly, the switches SW11 to SW1k of the decoder DD1 are selected by the high state of the control signal C1 to supply the gate driving signals S1 to Sk to the gate lines GL11 to GL1k of the first block. Subsequently, the transistors T11 to T1k of the decoder DD1 are selected by the high state of the control signal C (j + 1) to stabilize the gate low voltage by supplying the off voltage Voff to the gate lines GL11 to GL1k of the first block. It becomes possible.

As described above, the gate driver according to the present invention can reduce the number of output channels of the gate drive IC 52 and can stabilize the gate low voltages of the gate lines GL11 to GL1k by the transistor for applying the off voltage Voff. .

As described above, the gate driving apparatus and method of the liquid crystal panel according to the present invention can sequentially drive k × j gate lines to k + j output channels of the gate drive IC using a decoder. Accordingly, the number of output channels of the gate drive IC can be reduced to reduce the non-display area occupied by the output channel, thereby making it possible to compact the liquid crystal panel.

In addition, the gate driving apparatus and method of the liquid crystal panel according to the present invention can be stabilized by connecting the off voltage applying transistor to the gate line in parallel to prevent the gate low voltage on the gate line from being changed by the leakage current through the decoder. Will be.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (30)

An apparatus for driving gate lines of a liquid crystal panel, A gate drive integrated circuit for generating a plurality of gate drive signals and a plurality of control signals; And dividing the gate lines into a plurality of blocks, and having a plurality of decoders selected at different periods by each of the plurality of control signals to supply the plurality of gate driving signals to the gate lines of the corresponding block. The gate drive device of the liquid crystal panel. The method of claim 1, The sum of the number of the gate driving signals and the number of the control signals is smaller than the number of the gate lines. The method of claim 1, and k (j is a positive integer) gate driving signals and j (j is a positive integer) control signals to drive k x j gate lines. The method of claim 1, And the gate driving signals are set smaller than the number of the control signals. The method of claim 1, And the plurality of control signals cause the plurality of decoders to be sequentially driven. The method of claim 1, And the plurality of gate driving signals sequentially drive gate lines of a corresponding block selected by the decoder. The method of claim 1, Each of the decoders A plurality of gates connected to each of the gate lines of the corresponding block and configured to supply each of the plurality of gate driving signals to each of the gate lines of the corresponding block in response to a control signal of any one of the plurality of control signals in common; And a switching element of the gate driving device of the liquid crystal panel. The method of claim 1, And a plurality of off voltage applying transistors for supplying an off voltage to each of the gate lines while the gate lines each maintain a gate low voltage among the gate driving signals. Gate drive. The method of claim 8, And the plurality of off voltage applying transistors are connected in parallel with each of the gate lines. The method of claim 8, The plurality of off voltage applying transistors are divided in the same block unit as the gate lines, and are driven in the block unit according to any one of the plurality of control signals. Device. The method of claim 10, And a control signal supplied to the plurality of off voltage applying transistors in units of blocks is different from a control signal supplied to a decoder for driving gate lines of a corresponding block. The method of claim 10, And the gate driving integrated circuit further supplies a plurality of second control signals for driving the plurality of off voltage application transistors in the block unit. The method of claim 12, And each of the plurality of second control signals has an inverse phase with a control signal supplied to a decoder connected to gate lines of a corresponding block among the control signals. The method of claim 12, Each of the plurality of second control signals has a phase which is partially different from a plurality of control signals supplied to the decoder connected to gate lines of a corresponding block among the control signals. . The method of claim 10, And the plurality of off voltage applying transistors are embedded in each of the plurality of decoders in block units. The method of claim 1, The gate driving integrated circuit is mounted in the non-display area of the liquid crystal panel, And the plurality of decoders are formed in the non-display area. In the method of driving the gate lines of the liquid crystal panel, Generating a plurality of gate drive signals and a plurality of control signals; Selecting the gate lines in units of blocks in different periods by each of the plurality of control signals; And supplying the plurality of gate driving signals to a selected block of gate lines. The method of claim 17, And the sum of the number of the gate driving signals and the number of the control signals is smaller than the number of the gate lines. The method of claim 17, and k (j is positive integer) gate driving signals and j (j is positive integer) control signals to drive k x j gate lines. The method of claim 17, And setting the number of the gate driving signals to be smaller than the number of the control signals. The method of claim 17, And the plurality of control signals cause the gate lines to be sequentially driven in units of blocks. The method of claim 17, And the gate driving signals sequentially drive the gate lines of the selected block. The method of claim 17, Each of the plurality of gate driving signals Connected to each of the gate lines of the corresponding block, and supplied to each of the gate lines of the corresponding block through each of a plurality of switching elements that commonly respond to any one of the plurality of control signals. The gate drive method of the liquid crystal panel. The method of claim 17, And supplying an off voltage to each of the gate lines during a period in which each of the gate lines maintains a gate low voltage among the gate driving signals. The method of claim 24, The off voltage is And a plurality of off voltage applying transistors connected in parallel with each of the gate lines to be supplied to the gate lines in units of blocks of the gate lines. The method of claim 26, The off voltage applying transistors connected to any one of the gate lines supply the off voltage to the gate lines of the corresponding block in response to one of the plurality of control signals in common. The gate drive method of the liquid crystal panel. The method of claim 26, The control signal supplied to the off voltage applying transistors in block units is And a phase different from a control signal used to supply the gate driving signal to the gate lines of the block. The method of claim 25, And generating a plurality of second control signals for driving the plurality of off voltage applying transistors in the block unit. The method of claim 28, And each of the plurality of second control signals has an inverse phase with a control signal used to supply the gate driving signal to gate lines of a corresponding block among the control signals. The method of claim 28, Each of the plurality of second control signals has a phase that is partially different from a control signal used to supply the gate driving signal to gate lines of a corresponding block among the control signals. Way.