KR20040098108A - poly silicon layer, mask for forming the poly silicon layer, panel for a display device including the poly silicon layer, and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: A polycrystalline silicon layer and a mask for polycrystalline silicon, and a display panel for a display device with the polycrystalline silicon layer and a manufacturing method thereof are provided to form uniformly the polycrystalline silicon layer by crystallizing an amorphous silicon layer using the mask of a desired structure. CONSTITUTION: A mask for polycrystalline silicon includes slits for defining a light transmitting region. Both ends of each slit are formed like a sawtooth. The first group of slits is arrayed to a Y-axis direction on the mask. The second group of slits is arrayed parallel with the first group of slits on the mask. The first and the second groups are cornerwise arrayed with each other. The first and the second groups include small groups, respectively. The small groups are cornerwise arrayed with each other. Each small group includes three slits.

Description

Polysilicon layer, mask for forming the poly silicon layer, panel for a display device including the poly silicon layer, and method for manufacturing kind}

The present invention relates to a polycrystalline silicon layer, a polycrystalline mask for forming the same, a display panel for a display device including the polycrystalline silicon layer, and a manufacturing method thereof.

Generally, silicon may be divided into amorphous silicon and crystalline silicon according to the crystal state. Amorphous silicon can be deposited at a low temperature to form a thin film, and is mainly used for switching elements of liquid crystal panels using glass having a low melting point as a substrate.

However, the amorphous silicon thin film has difficulty in large area of the display device due to problems such as low field effect mobility. Therefore, there is a need for the application of polycrystalline silicon having high field effect mobility, high frequency operating characteristics, and low leakage current electrical characteristics.

The electrical properties of thin films using polycrystalline silicon are greatly influenced by the size and uniformity of the grains. That is, as the size and uniformity of the particles increase, the field effect mobility also increases. Therefore, there is increasing interest in a method of forming uniform polycrystalline silicon while increasing the particle size.

Methods of forming polycrystalline silicon include ELA (eximer laser anneal) and furnace annealing (chamber annal). Recently, a sequential lateral solidification (SLS) technique has been proposed for producing polycrystalline silicon by inducing lateral growth of silicon crystals with a laser. .

The SLS technology takes advantage of the fact that silicon particles grow at the interface between liquid silicon and solid silicon in a direction perpendicular to the interface, and shift the size of the laser beam energy and the range of irradiation of the laser beam to the optical system and the mask. In this case, the amorphous silicon is crystallized by lateral growth of the silicon particles by a predetermined length.

That is, the laser beam passes through the transmission region (slit) of the mask to completely dissolve the amorphous silicon to form a slit-shaped liquid region. Subsequently, the liquid amorphous silicon is crystallized while cooling, and the crystal grows from the interface between the solid region and the liquid region where the laser is not irradiated, and grows in a direction perpendicular to the interface. The particles grow in different directions and stop when they meet at the center of the liquid region.

Here, the mask has two rows of slits in which a plurality of rectangular slits are arranged at regular intervals, and the slits of each row are arranged to be staggered with each other. In order to form polycrystalline silicon on the entire substrate using such a mask pattern, a plurality of processes of irradiating a laser pattern and then irradiating the mask pattern are performed a plurality of times. In this case, the crystallization process is performed by irradiating a laser beam while continuously moving the mask by a predetermined distance in the X-axis direction of the substrate, and this process is repeatedly performed in the Y-axis direction of the substrate to crystallize amorphous silicon into polycrystalline silicon on the entire surface. .

When moving the mask, however, the edge of the slit overlaps the previously irradiated portion to irradiate the laser, where the overlapping portion of the slit irradiates the laser, unlike most other regions, where the direction of crystal growth is not perpendicular to the interface and is tilted. It grows unevenly in form.

When the channel portion of the thin film transistor is located at a portion where the crystal grows unevenly, the characteristics of the thin film transistor are deteriorated, and thus, the image quality of the display device is uneven, and so is the case in the organic light emitting display device. The organic light emitting diode display is a display device using an organic material that emits light due to a flowing current, and the flow of the current is sensitively reacted according to the uniformity of the polycrystal.

The present invention has been made to solve the above problems and to provide a polycrystalline silicon layer having a uniform crystal and a polycrystalline mask capable of forming the same.

Another object of the present invention is to provide a thin film transistor array panel for a display device including a polycrystalline silicon layer having a uniform crystal and a method of manufacturing the same.

1 is a view showing the grain shape of the polycrystalline silicon layer and the alignment of the slits in the crystallization process according to an embodiment of the present invention,

2A to 2C are views illustrating masks for polycrystals according to first to third embodiments of the present invention.

Figure 3a is a SEM photograph of the crystal grains of the polycrystalline silicon layer according to the prior art,

Figure 3b is a SEM photograph of the grains of the polysilicon layer in accordance with an embodiment of the present invention,

4A to 4G are diagrams sequentially illustrating a process of crystallizing a polycrystalline silicon layer using a mask according to an embodiment of the present invention.

5 is a layout view of a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

6 is a cross-sectional view taken along the line VI-VI 'of FIG. 5,

FIG. 7 is a cross-sectional view taken along the line VII-VII ′ of FIG. 5;

8A, 9A, 10A, 11A, and 12A are layout views of display panels at each stage of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention.

8B and 8C are cross-sectional views taken along lines VIIIb-VIIIb 'and VIIIc-VIIIc' of FIG. 8A, respectively.

9B and 9C are cross-sectional views taken along the lines IXb-IXb 'and IXb-IXb' of FIG. 9A, respectively.

10B and 10C are cross-sectional views taken along the lines Xb-Xb 'and Xc-Xc' of FIG. 10A, respectively.

11B and 11C are cross-sectional views taken along lines XIb-XIb ′ and XIc-XIc ′ of FIG. 11A, and

12B and 12C are cross-sectional views taken along lines XIIb-XIIb 'and XIIc-XIIc' of FIG. 12A.

<Description of the symbols for the main parts of the drawings>

70 organic light emitting layer 121, 123a, 123b: gate line

133: sustain electrode 150a, 150b: polycrystalline silicon layer

171a, 171b, 173a, 173b, 175a, 175b: data line

181, 182, 183, 184, 185, 186: contact hole

190: pixel electrode

Polycrystalline silicon layer according to an embodiment of the present invention for achieving the above object has a sawtooth-shaped crystal grains, a slit pattern having a side-side sawtooth shape is formed in the polycrystalline mask to crystallize it.

In more detail, at least a portion of the polycrystalline silicon layer according to the present invention for achieving the above-mentioned object is formed by repeating the partially constant sawtooth crystal grains.

Here, the polycrystalline silicon layer is formed by alternating crystal grains inclined with respect to the Y axis and inclined with respect to the Y axis, and a plurality of crystal grains are preferably formed in a predetermined region.

Polycrystalline mask according to the present invention for achieving the above another object is a polycrystalline mask having a slit defining a transmission region for transmitting a laser beam or light, the side edges of the slit is narrowed at both ends in a diagonal form Serrated

Here, the polycrystalline mask may have a first group in which two or more slits are arranged in the Y-axis direction at intervals equal to the Y-axis length of the slits.

In addition, the polycrystalline mask may further include a second group having the same pattern as the first group and arranged to be shifted by 1/2 of the length of the Y axis of the slit.

In this case, the first and second groups each include a small group in which three slits are arranged at intervals equal to the Y-axis length of the slit, and in the first and second groups, the small groups are arranged to be offset from each other at regular intervals. Do.

According to another aspect of the present invention, a display panel for a display device includes an insulating substrate, a polycrystalline silicon layer formed on a substrate, and having a constantly repeating sawtooth crystal grain, a gate insulating film formed on the polycrystalline silicon layer, On the gate line formed on the gate insulating film, the first interlayer insulating film formed on the gate line, the data line and drain electrode formed on the first interlayer insulating film, the second interlayer insulating film formed on the data line, and the second interlayer insulating film. The polycrystalline silicon layer including the formed pixel electrode is formed by alternating a crystal grown in the Y axis along a crystal growth direction and a crystal inclined at a predetermined angle with respect to the Y axis.

The organic light emitting layer may further include an organic emission layer formed in a predetermined region on the pixel electrode, a partition wall surrounding the organic emission layer and defining an area of the organic emission layer, and a common electrode formed on the organic emission layer and the partition wall.

The polysilicon layer has a storage electrode portion connected to the first and second transistor portions and the second transistor portion, and the gate lines and the storage electrode portions overlap the first and second transistor portions, respectively. And a sustain electrode overlapping the sustain electrode portion, wherein the data line includes a first source electrode connected to a source region of the first and second data lines, the first data line, and the first transistor portion, and a drain region of the first transistor portion. And a first drain electrode connected to the second gate electrode, a second data line and a second source electrode connected to the source region of the second transistor portion, and a second drain electrode connected to the drain region of the second transistor portion. The pixel electrode is preferably connected to the second drain electrode.

In this case, it is preferable to further include a buffer layer formed between the organic light emitting layer and the reference electrode, and may further include grains grown in the Y-axis direction between the sawtooth crystal grains and the neighboring sawtooth crystal grains.

According to another aspect of the present invention, there is provided a method of manufacturing a display panel for a display device, the method including: forming a polycrystalline silicon film having a sawtooth-shaped crystal grain repeatedly on an insulating substrate, and patterning the polycrystalline silicon film to form a polycrystalline silicon layer. Forming a source region, a drain region, and a channel region that is not doped with impurities by doping conductive regions in a predetermined region of the polycrystalline silicon layer, forming a gate insulating layer on the polysilicon layer, and a gate on the gate insulating layer Forming a line, forming a first interlayer insulating film on the gate line, forming a data line having a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the first interlayer insulating film, Forming a second interlayer insulating film, the drain electrode on the second interlayer insulating film And forming a pixel electrode connected.

The method may further include forming a partition on the pixel electrode, forming an organic emission layer in a predetermined region on the pixel electrode partitioned by the partition, and forming a common electrode on the organic emission layer.

In this case, the forming of the polycrystalline silicon layer may include forming an amorphous silicon layer on an insulating substrate, aligning a polycrystalline mask having slits having serrated slits at both ends of the side edges on the amorphous silicon layer. Irradiating the amorphous silicon layer through the mask for mask, it is preferable to include the step of moving the mask so that the teeth of the slit is arranged to engage, the step of repeating the irradiation and moving. The method may further include forming an auxiliary electrode in contact with the common electrode. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. In contrast, when a part is just above another part, it means that there is no other part in between.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[First to third embodiments]

1 is a view showing a grain shape of the polycrystalline silicon layer according to an embodiment of the present invention and the alignment shape of the slits in the manufacturing process.

As shown in FIG. 1, the slit S for forming the polycrystalline silicon layer has a hexagonal shape in which the slit S is elongated to one side, and both ends thereof become narrower, and the sides have a sawtooth shape. The ends are aligned with the neighboring slit (S). In this case, the slit S may be arranged in various shapes in the polycrystalline mask used in the crystallization process, which will be described in detail later with reference to the drawings.

The polycrystalline silicon layer according to the embodiment of the present invention crystallized through the side solid crystallization process using a mask having such a slit has a predetermined crystal pattern according to the growth shape of the crystal.

This is due to the property of crystal growth in the direction perpendicular to the interface between the solid phase and the liquid phase during the crystallization process. The grains of the polycrystalline silicon layer grow in a direction perpendicular to the boundary line of the slit (S). Therefore, the crystal grain pattern of the polycrystalline silicon layer is formed in such a manner that the first crystal grains C1 formed on the Y axis and the second crystal grains C2 formed to have an inclination angle with respect to the Y axis alternately. The grains of j are jagged. In this case, a plurality of first grains C1 and second crystal grains C2 are formed in a predetermined region, and the first and second groups C1 and P2 are arranged in an alternating manner.

The polycrystalline silicon layer having such a grain pattern may be formed using a polycrystalline mask according to the present invention. Next, a polycrystalline mask structure according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. do.

2A to 2C illustrate a mask for polycrystal according to an embodiment of the present invention.

The polycrystalline mask MP according to the embodiment of the present invention includes a plurality of slits S arranged at regular intervals and through which a laser beam is transmitted, and the side edges of the slits S have a sawtooth shape. The slits S of the polycrystalline mask MP may be arranged in various forms as shown in FIGS. 2A to 2C (first to third embodiments, respectively). Hereinafter, the up and down direction of the figure is referred to as the Y-axis direction and the left and right directions are referred to as the X-axis direction.

That is, the slits S can be arranged at regular intervals with respect to the Y axis, as shown in 2a. After the initial irradiation, the slit S is half the length of the Y axis of the slit S as the Y axis. The first irradiation step of moving and irradiating by X-axis length of the slit S (the length excluding the length of the teeth formed at both ends of the slit) on the X-axis, and the slit (S) on the Y-axis. 2nd irradiation process which irradiates without moving to the X axis and irradiates by the length of Y-axis of), and which irradiates by moving to the position which is separated by the X-axis length of the slit S on the X axis without moving to the Y axis Three irradiation processes can be combined suitably, and a polycrystalline silicon layer can be formed.

As shown in FIG. 2B, the first column arranged at a constant interval with respect to the Y axis and the length of the Y axis are shifted by 1/2, and the slit S is spaced apart by the X axis length to have a constant interval with respect to the Y axis. And a second column arranged. Such an arrangement can reduce the time for irradiating the entire substrate by half than when using the polycrystalline mask shown in Fig. 2A. In this case, after the first irradiation, the first irradiation process of irradiating the first column at the time of the first irradiation to the position of the second column by irradiating by moving the mask by 1/2 of the polycrystalline mask on the X axis without moving the Y axis, The polysilicon layer can be formed by combining suitably the 2nd irradiation process which moves by 1/2 of the length of the Y-axis of the slit S, and does not move on a Y-axis, but combines suitably.

In addition, slits may be arranged as shown in FIG. 2C, which is divided into first and second groups 1G and 2G, and the first and second groups 1G and 2G are first to third small groups. (1SG, 2SG, 3SG).

The slits of the first and second groups 1G and 2G are arranged in the same shape, but the second group 2G is positioned to be shifted by the Y-axis length W of the slit S than the first group 1G. The first to third small groups 1SG to 3SG are alternately arranged with neighboring small groups. Each of the small groups 1SG to 3SG has three slits S through which the laser beam is transmitted, and is arranged at regular intervals so that the X-axis length L of the slits S is parallel. Both ends of the slit (S) has a sawtooth shape in a narrower form toward the end, the end need not be pointed. A process of forming the polycrystalline silicon layer using the polycrystalline mask shown in FIG. 2C will be described with reference to FIGS. 4A to 4G.

As described above, the polycrystalline silicon layer finally formed using various types of polycrystalline masks MP is formed to have the crystal pattern shown in FIG.

That is, when the polysilicon layer is formed by using the polycrystalline mask MP having the slit according to the present invention, the slit has a serrated side of the slits, and is perpendicular to the side at the portion corresponding to the edge of the slit S. Even if the polysilicon layer is established, the growth direction of the grains is almost similar to the growth direction of the grains growing at the portion corresponding to the center of the slit (S). Therefore, the crystal grown at the portion corresponding to the edge of the slit S hardly affects the crystal growing at the portion corresponding to the center of the slit S, so that the crystal of the polycrystalline silicon layer is formed uniformly.

That is, in the prior art, the crystal grains formed in the Y-axis at the portion corresponding to the center of the slit S and the crystals grown in the X-axis at the edges of the slits collide with each other to form non-uniform crystals, but this phenomenon occurs in the embodiment of the present invention. It is not possible to obtain a uniform polycrystalline silicon layer.

3A and 3B are SEM images showing the crystal structure of a polysilicon layer crystallized using a mask having a rectangular slit of the prior art and a mask having a sawtooth-shaped side edge as in the embodiment of the present invention.

In FIG. 3A, it can be seen that the crystal grains of the polycrystalline silicon layer are partially formed unevenly. However, as shown in FIG. 3B, when the polycrystalline silicon layer is crystallized using a mask having a slit according to an embodiment of the present invention, the polycrystalline silicon is crystallized. It can be seen that the crystals of the layer are formed more uniformly. By using the polycrystalline silicon layer having a uniform crystal structure as the semiconductor layer of the thin film transistor, the characteristics of the thin film transistor can be improved to ensure uniformity. The thin film transistor is used as a driving element for driving pixels of the display device. By using it, the display characteristic of a display apparatus can be improved.

Next, a method of forming the polycrystalline silicon layer according to the embodiment of the present invention using the polycrystalline mask according to the third embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4A to 4G are layout views illustrating a process of crystallizing amorphous silicon using a polycrystalline mask according to a third exemplary embodiment of the present invention according to a process sequence.

As shown in Fig. 4A, an amorphous silicon film 100 is formed on a substrate (not shown) for forming polycrystalline silicon. Thereafter, after aligning the mask in a predetermined region of the amorphous silicon film 100, the laser beam is first irradiated through the slit S of the mask.

At this time, the amorphous silicon of the irradiated portion is melted to become a liquid phase, and crystallization starts at the interface between the molten amorphous silicon and the solid amorphous silicon of the unirradiated portion. Crystals grow in the vertical direction of the interface.

The mask MP is arranged at regular intervals and includes a plurality of slits defining the area through which the laser beam is transmitted. In more detail, the mask MP is divided into first and second groups 1G and 2G, and the first and second groups 1G and 2G are first to third small groups 1SG, 2SG, and 3SG. Is done.

The slits S of the first and second groups 1G and 2G are arranged in the same shape, but the second group 2G is shifted by the Y-axis length W of the slit S than the first group 1G. Is located. The first to third small groups 1SG to 3SG are alternately arranged with neighboring small groups.

Each of the small groups 1SG to 3SG has three slits S through which the laser beam is transmitted, and is arranged at regular intervals so that the X-axis length L of the slits S is parallel. The slit (S) is formed long in one direction and both ends are sawtooth in a narrower shape toward the end, the end does not need to be pointed.

Subsequently, as shown in FIG. 4B, after the first irradiation, the mask MP is moved up and down by a predetermined distance, and then the second irradiation is performed.

The moving distance is moved by the width of the first group 1G in the X-axis direction, and when the first irradiation is performed, the portion where the laser beam is shot through the second group 2G (hereafter A: A region) and the second irradiation can be performed. In this case, the portion (B: region B below) to shoot the laser beam is positioned on the same Y axis through the first group 1G. In the Y-axis direction, the A region A and the B region B irradiated downward by the short width W of the slit and irradiated by one slit are alternately arranged on the same Y axis.

Thereafter, as shown in FIG. 4C, the first scan is completed by repeating the second irradiation and the movement many times. At this time, it is said that the scan and movement of the substrate from one end to the other end of the substrate are scanned once.

Then, as shown in FIG. 4D, the secondary scan is performed in the direction opposite to the primary scan at the point where the primary scan is finished. This scanning operation is performed on the entire substrate in a zigzag form that descends from the upper left of the substrate to the lower right of the substrate.

Next, as illustrated in FIGS. 4E to 4G, the scan operation is continuously performed on the entire substrate in a zigzag pattern of rising from the lower right portion to the upper left portion. At this time, the slit S of the mask MP is disposed so as to correspond to the amorphous silicon of the portion where crystallization has not been performed, but it is preferable to carry out while moving at the same width and interval as the primary and secondary irradiation.

The thin film transistor array panel for an organic light emitting display device including the polycrystalline silicon layer and the polycrystalline mask polycrystalline silicon layer according to the embodiment of the present invention and a method of manufacturing the same may be applied to the same. It will be described in detail.

[Example 4]

5 is a layout view illustrating a structure of a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention, FIG. 6 is a cross-sectional view taken along the line VI-VI ′ of FIG. 5, and FIG. 7 is a VII-VII line of FIG. 5. 'Is a cross section of the line.

5 to 7, a blocking layer 111 made of silicon oxide or the like is formed on the insulating substrate 110, and the polycrystalline silicon layers 153a 154a, 155a, 153b, and 154b are formed on the blocking layer 111. 155b and 157 are formed.

The polysilicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157 may include the first transistor portions 153a, 154a, 155a, the second transistor portions 153b, 154b, 155b, and the storage electrode portion 157. Include. The source region (first source region 153a) and the drain region (first drain region, 155a) of the first transistor portions 153a, 154a, and 155a are doped with n-type impurities, and the second transistor portions 153b and 154b. The source region (second source region 153b) and the drain region (second drain region 155b) of 155b are doped with p-type impurities. In this case, depending on the driving conditions, the first source region 153a and the drain region 155a may be doped with p-type impurities, and the second source region 153b and the drain region 155b may be doped with n-type impurities. .

At this time, the polycrystalline silicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157 are formed so that the crystals have a predetermined pattern, and some have a sawtooth shape as shown in FIG. 1.

A gate insulating layer 140 made of silicon oxide or silicon nitride is formed on the polycrystalline silicon layers 153a, 154a, 155a, 153b, 154b, 155b, and 157. On the gate insulating layer 140, a gate line 121 made of a metal such as aluminum, chromium, molybdenum, or an alloy thereof, first and second gate electrodes 123a and 123b, and a storage electrode 133 are formed.

The first gate electrode 123a is formed in the shape of a branch of the gate line 121, and overlaps the channel region (first channel region 154a) of the first transistor, and the second gate electrode 123b is a gate line ( 121 and overlap with the channel region (second channel region 154b) of the second transistor. The storage electrode 133 is connected to the second gate electrode 123b and overlaps the storage electrode portion 157 of the polysilicon layer. One end of the gate line 121 may be formed wider than the width of the gate line 121 to receive a signal transmitted from an external driving circuit (not shown).

An interlayer insulating layer 801 is formed on the gate line 121, the first and second gate electrodes 123a and 123b, and the storage electrode 133, and the first and second data lines 171a and 171b, first and second source electrodes 173a and 173b, and first and second drain electrodes 175a and 175b are formed.

The first source electrode 173a is connected to the first source region 153a as a branch of the first data line 171a through a contact hole 181 penetrating through the interlayer insulating film 801 and the gate insulating film 140. The second source electrode 173b is a branch of the second data line 171b and a second source region 153b through a contact hole 184 penetrating through the interlayer insulating film 801 and the gate insulating film 140. It is connected. The first drain electrode 175a is in contact with the first drain region 155a and the second gate electrode 123b through the contact holes 182 and 183 penetrating the interlayer insulating layer 801 and the gate insulating layer 140. The second drain electrode 175b is connected to the second drain region 155b through a contact hole 185 penetrating through the gate insulating layer 140 and the interlayer insulating layer 801. On the other hand, the second data line 171b overlaps the sustain electrode 133.

An interlayer insulating film 802 having a contact hole 186 exposing the second drain electrode 175 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b.

The pixel electrode 190 connected to the second drain electrode 175b is formed on the interlayer insulating layer 802 through the contact hole 186. The pixel electrode 190 is preferably formed of a material having excellent reflectivity such as aluminum. However, if necessary, the pixel electrode 190 may be formed of a transparent insulating material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

A partition wall 803 made of an organic insulating material is formed on the pixel electrode 190. The partition 803 surrounds the pixel electrode 190 to define a region in which the organic emission layer 70 is to be filled.

The partition wall 803 is formed by exposing and developing a photosensitive agent including a black pigment to serve as a light shielding film, and at the same time, the forming process may be simplified. An organic emission layer 70 is formed in an area on the pixel electrode 190 surrounded by the partition 802. The organic light emitting layer 70 is formed of an organic material emitting one of red, green, and blue light, and the red, green, and blue organic light emitting layers 70 are repeatedly arranged in sequence.

The buffer layer 804 is formed on the organic light emitting layer 70 and the partition 803. The buffer layer 804 may be omitted as necessary.

The common electrode 270 is formed on the buffer layer 804. The common electrode 270 is made of a transparent conductive material such as ITO or IZO. If the pixel electrode 190 is made of a transparent conductive material such as ITO or IZO, the common electrode 270 is formed of a metal having good reflectivity such as aluminum.

Although not shown, an auxiliary electrode may be formed of a metal having low resistance to compensate for the conductivity of the common electrode 270. The auxiliary electrode may be formed between the common electrode 270 and the buffer layer 804 or on the common electrode 270. The auxiliary electrode may be formed in a matrix shape along the partition wall 803 so as not to overlap the organic light emitting layer 70. . Here, the second data line 171b is connected to a constant voltage power supply.

The driving of the thin film transistor array panel for the organic light emitting diode display will be briefly described.

When an on pulse is applied to the gate line 121, the first transistor is turned on, and an image signal voltage applied through the first data line 171a is transferred to the second gate electrode 123b. . When the image signal voltage is applied to the second gate electrode 123b, the second transistor is turned on, and a current transmitted through the second data line 171b is transferred to the common electrode 270 through the pixel electrode 190 and the organic emission layer 70. Will flow). The organic light emitting layer 70 emits light in a specific wavelength band when current flows. The amount of light emitted by the organic light emitting layer 70 varies according to the amount of current flowing, thereby changing the brightness. At this time, the amount of current that the second transistor can flow is determined by the magnitude of the image signal voltage transmitted through the first transistor.

A method of manufacturing the thin film transistor array panel for the organic light emitting diode display described above will be described in detail with reference to FIGS. 8A to 12C and FIGS. 5 to 7.

8A, 9A, 10A, 11A, and 12A are layout views of a thin film transistor array panel for an organic light emitting diode display in each step of manufacturing a thin film transistor array panel for an organic light emitting diode display according to an exemplary embodiment of the present invention. 8B to 12B show the VIIIb-VIIIb 'line of FIG. 8A, the IXb-IXb' line of FIG. 9A, the Xb-Xb 'line of FIG. 10A, the XIb-XIb' line of FIG. 11A, and the XIIb-XIIb 'line of FIG. 12A, respectively. 8C to 12C are lines VIII-VIII 'of FIG. 8A, lines IXb-IXb' of FIG. 9A, lines Xc-Xc 'of FIG. 10A, lines XIc-XIc' of FIG. 11A, and FIG. 12A, respectively. It is sectional drawing about the XIIc-XIIc 'line | wire.

First, as shown in FIGS. 8A to 8C, a silicon oxide or the like is deposited on the insulating substrate 110 to form a blocking layer 111, and an amorphous silicon film is deposited on the blocking layer 111. The deposition of the amorphous silicon film may be performed by low temperature chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVE), or sputtering. Next, the amorphous silicon film is crystallized by a crystallization method using a polycrystalline mask according to the first to third embodiments of the present invention to form a polycrystalline silicon film having sawtooth crystal grains (see FIGS. 3A to 3G).

Next, the polycrystalline silicon film is patterned by a photolithography process to form the first and second transistor parts and the sustain electrode part 157.

Next, as shown in FIGS. 9A to 9C, the gate insulating layer 140 is deposited on the polycrystalline silicon layers 150a, 150b, and 157. Subsequently, metal is deposited to form a gate metal film 120. Thereafter, a photoresist film is coated on the gate metal film 120, followed by exposure and development to form a first photoresist film pattern PR1.

Next, the gate metal film 120 is etched using the first photoresist film pattern PR1 as a mask to form the second gate electrode 123b and the sustain electrode 133, and the exposed second transistor unit 150b. The p-type impurity ions are implanted into the polysilicon layer to form the second source region 153b, the second drain region 155b, and the second channel region 154b which is not doped with impurities. In this case, the polycrystalline silicon layer of the first transistor unit 150a is covered and protected by the first photoresist film pattern PR1 and the gate metal film 120. At this time, since the sustain electrode part 157 overlaps with the data line 171b formed later, the sustain electrode part 157 is protected by the photosensitive film so that impurities are not doped.

Next, as shown in FIGS. 10A to 10C, the first photoresist pattern PR1 is removed, the photoresist is newly coated, exposed to light, and developed to form a second photoresist pattern PR2. The gate metal film 120 is etched using the second photoresist film pattern PR2 as a mask to form the first gate electrode 123a and the gate line 121, and the first transistor portion 150a of the polycrystalline silicon is exposed. The n-type impurity ions are implanted into the layer to form the first source region 153a, the first drain region 155a, and the first channel region 154a which is not doped with impurities. At this time, the second transistor units 153b, 154b, and 155b and the storage electrode unit 157 are covered and protected by the second photosensitive film pattern PR2.

Next, as illustrated in FIGS. 11A through 11C, the interlayer insulating layer 801 is stacked on the gate lines 121, 123a, 123b, and 133, and the interlayer insulating layer 801 and the gate insulating layer 140 are formed by a photolithography process. The interlayer and the contact holes 181, 182, 184, and 185 exposing the first source region 173a, the first drain region 175a, the second source region 173b, and the second drain region 175b, respectively, by etching. The insulating layer 801 is etched to form a contact hole 183 exposing one end of the second gate electrode 123b.

Next, the data metal film is stacked and the data lines 171a, 171b, 173a and 173b and the drain electrodes 175a and 175b are formed by a photolithography process.

12A to 12C, an interlayer insulating film 802 is formed on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b, and then the interlayer insulating film 802 is formed by a photolithography process. By etching, the contact hole 186 exposing the second drain electrode 175b is formed.

Subsequently, a metal having excellent reflectivity such as aluminum is deposited on the interlayer insulating layer 802 and patterned by a photolithography process to form a pixel electrode 190 connected to the second drain electrode 175b through the contact hole 186.

Next, as illustrated in FIGS. 5 to 7, an organic film including a black pigment is coated on the data lines 171a, 171b, 173a, and 173b and the drain electrodes 175a and 175b, and exposed and developed to partition the barrier rib 803. The organic light emitting layer 70 is formed in each pixel area. At this time, the organic light emitting layer 70 usually has a multilayer structure. The organic light emitting layer 70 is deposited after masking, or formed by inkjet printing or the like.

Next, a conductive organic material is coated on the organic emission layer 70 to form a buffer layer 804, and ITO or IZO is deposited on the buffer layer 804 to form a common electrode 270.

At this time, although not shown, the auxiliary electrode may be formed of a low resistance material such as aluminum before or after the common electrode 270 is formed. In addition, when the pixel electrode 190 is formed of a transparent conductive material, the common electrode 270 is formed using a metal having excellent reflectivity.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary and can be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. There will be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

As such, when the amorphous silicon layer is crystallized using the mask pattern according to the present invention, a uniform polycrystalline silicon layer can be obtained. Therefore, when the display panel including the polycrystalline silicon layer is formed, the current characteristics of the polycrystalline silicon layer are improved, thereby obtaining a high quality display panel.

Claims (15)

At least a portion of the polycrystalline silicon layer in which the sawtooth crystal grains are formed at a constant repeat. In claim 1, The polycrystalline silicon layer is formed of alternating crystal grains inclined with respect to the Y axis and inclined with respect to the Y axis, and a plurality of crystal grains are formed in a predetermined region. In the mask for polycrystal having a slit defining a transmission region for transmitting a laser beam or light, The side surface of the slit is a mask for polycrystalline with both ends narrowed in the form of a diagonal line. In claim 3, The polycrystalline mask has a first group of two or more slits arranged in the Y-axis direction at intervals equal to the Y-axis length of the slit. In claim 4, The polycrystalline mask further includes a second group having the same pattern as the first group and arranged to be shifted by 1/2 of the Y-axis length of the slit. In claim 5, The first and second groups each include a small group in which the three slits are arranged at intervals equal to the Y-axis length of the slit, and the small groups in the first and second groups are alternately arranged at regular intervals. Polycrystalline mask. Insulation board, A polycrystalline silicon layer formed on the substrate and having serrated crystal grains that repeat regularly; A gate insulating film formed on the polycrystalline silicon layer, A gate line formed on the gate insulating film, A first interlayer insulating film formed over the gate line, A data line and a drain electrode formed on the first interlayer insulating film; A second interlayer insulating film formed on the data line, A pixel electrode formed on the second interlayer insulating film, The polysilicon layer is a display panel for a display device wherein crystals grown in the Y-axis in accordance with the crystal growth direction and crystals inclined at a predetermined angle with respect to the Y-axis are alternately formed. In claim 7, An organic light emitting layer formed on a predetermined region on the pixel electrode, A partition wall surrounding the organic light emitting layer and defining an area of the organic light emitting layer, And a common electrode formed on the organic light emitting layer and the partition wall. In claim 8, The polycrystalline silicon layer has first and second transistor portions and sustain electrode portions connected to the second transistor portions, The gate line and the storage electrode part include first and second gate electrodes overlapping the first and second transistor parts, and a storage electrode overlapping the storage electrode part, respectively, The data line is connected to first and second data lines, a first source electrode connected to the first data line and a source region of the first transistor unit, a drain region of the first transistor unit, and the second gate electrode. A first drain electrode, a second source electrode connected to the second data line and a source region of the second transistor portion, and a second drain electrode connected to the drain region of the second transistor portion, The pixel electrode is connected to the second drain electrode. The method according to any one of claims 7 to 9, The display panel of claim 1, further comprising a buffer layer formed between the organic emission layer and the reference electrode. In claim 7, And a crystal grain grown in the Y-axis direction between the sawtooth crystal grain and the neighboring sawtooth crystal grain. Forming a polycrystalline silicon film having a sawtooth crystal grain repeatedly repeated on the insulating substrate, Patterning the polycrystalline silicon film to form a polycrystalline silicon layer, Doping a predetermined region of the polysilicon layer to form a source region, a drain region, and a channel region which is not doped with impurities, Forming a gate insulating film on the polycrystalline silicon layer, Forming a gate line on the gate insulating layer; Forming a first interlayer insulating film on the gate line; Forming a data line having a source electrode and a drain electrode connected to the source region and the drain region, respectively, on the first interlayer insulating layer; Forming a second interlayer insulating film on the data line; And forming a pixel electrode connected to the drain electrode on the second interlayer insulating layer. In claim 12, Forming a partition on the pixel electrode; Forming an organic emission layer on a predetermined region on the pixel electrode partitioned by the partition wall, And forming a common electrode on the organic light emitting layer. The method of claim 12 or 13, The forming of the polycrystalline silicon layer may include forming an amorphous silicon layer on the insulating substrate, Aligning the polycrystalline mask having the sawtooth-shaped slits with both ends of the side edges narrowed diagonally on the amorphous silicon layer, Irradiating the amorphous silicon layer through the polycrystalline mask; Moving the mask so that the teeth of the slit are arranged to engage, A method of manufacturing a display panel for a display device comprising repeating the irradiation and moving. The method of claim 14, And forming an auxiliary electrode in contact with the common electrode.