KR20040096340A - Method for forming contact plug of semicondutor device - Google Patents

Abstract

PURPOSE: A method for forming a contact plug of a semiconductor device is provided to reduce contact resistance and thermal budget by growing a silicon epi-layer between an amorphous silicon layer and a substrate. CONSTITUTION: An interlayer dielectric(5) is formed on a silicon substrate(1) with a desired lower structure. A contact hole is formed by selectively etching the interlayer dielectric. The exposed substrate is cleaned and baked. An amorphous silicon layer is deposited on the contact hole. A polysilicon layer(8) is then entirely filled in the contact hole. At this time, a silicon epi-layer(9) is grown at the interface between the substrate and the amorphous silicon layer. The remaining amorphous silicon layer is crystallized.

Description

Method for forming contact plug of semicondutor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact plug of a semiconductor device, and more particularly, to a method for forming a contact plug capable of improving interface characteristics with a substrate while having a low thermal budget.

As the integration of semiconductor devices increases, the size of circuit patterns is gradually decreasing, and various process technologies are being applied and developed to obtain excellent device characteristics in accordance with this trend. In particular, new process technologies for the contact process are being developed to increase the operation efficiency of the device.

The demand for a new technology for the contact process is that even if the size of the pattern is achieved, if the contact between the upper and lower patterns is unstable or the contact resistance is increased, the reliability of the device is not secured and the high speed operation is difficult.

On the other hand, in the device of 0.15㎛ or less, the gate length becomes smaller and inevitably requires excessive implantation of the ion implant for adjusting the threshold voltage (Vt). However, such ion implantation is generally known to deteriorate the refresh characteristics to a certain extent. In addition, as the miniaturization of the device is becoming increasingly difficult to secure the capacitance that greatly affects the refresh characteristics, the refresh margin is gradually decreasing.

Here, there are many factors affecting the refresh characteristics. For example, when polysilicon is used as the plug material, it is common to perform phosphorus (P) doping of approximately ˜1E20 orders in order to obtain an appropriate contact resistance. The phosphorus (P) is adversely affected by the refresh characteristics as it is diffused into the junction region or the cell transistor by a subsequent thermal process.

Further, in order to improve the refresh characteristics, additional ion implantation such as plug ion implantation may be performed, but this also adversely affects the refresh characteristic due to outward diffusion of the phosphorus (P) implanted with the plug ion.

On the other hand, when forming a contact plug, if the doping concentration of phosphorus (P) is unconditionally lowered, the contact resistance increases and the current driving capability is greatly reduced. Therefore, ensuring proper process conditions is essential.

On the other hand, in forming the contact plug, when there is a defect at the interface between the substrate surface and the contact plug, device reliability is lowered.

Accordingly, in order to solve this problem, a method of using a silicon epilayer using a selective epitaxial growth as a plug material has been proposed. When the silicon epi layer is used as the plug material, even if the doping concentration of phosphorus (P) is low, the interface property may be improved, thereby reducing contact resistance.

However, in the growth process of the silicon epilayer according to the prior art, since the process temperature is relatively high, such as 800 ° C. or more, phosphorus (P) diffuses into the substrate bonding region even though it has a low doping concentration. Rather, it has the potential to worsen the refresh characteristics.

As a result, the new technology for the contact process requires a plug structure having a low thermal budget and excellent interface with the substrate in order to improve refresh characteristics and increase current driving capability.

Accordingly, an object of the present invention is to provide a method for forming a contact plug of a semiconductor device capable of improving an interface property with a substrate while having a low thermal budget.

1A to 1E are cross-sectional views of processes for explaining a method for forming a contact plug according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1: silicon substrate 2: device isolation film

3: gate 4: junction area

5 interlayer insulating film 6 contact hole

7: amorphous silicon layer 8: polycrystalline silicon layer

9: silicon epi layer 10: contact plug

In order to achieve the above object, the present invention comprises the steps of providing a silicon substrate having an interlayer insulating film formed on the front surface to form a predetermined lower structure and cover it; Etching the interlayer insulating film to form a contact hole exposing a substrate; Performing a dry and wet cleaning of the substrate surface exposed by the contact hole, followed by hydrogen baking; Depositing an amorphous silicon layer on the contact hole and the interlayer dielectric layer to a predetermined thickness; A silicon epitaxial layer is formed at an interface between the amorphous silicon layer and the substrate through the application of heat during deposition of the polycrystalline silicon layer, and the deposition of the polycrystalline silicon layer to a thickness filling the contact hole on the amorphous silicon layer, and the amorphous silicon layer Making an upper layer of the polycrystalline silicon layer; And removing the polycrystalline silicon layer on the interlayer insulating film.

Here, the amorphous silicon layer is deposited to a thickness of 100 ~ 1000Å by using DCS (Diclorosilane: SiCl 2 H 2), H 2 and PH 3 gas at a temperature of 480 ~ 580 ℃, the PH3 gas flow rate is adjusted to 0 to 100 sccm . The polycrystalline silicon layer is deposited to a thickness of 1000 to 2000 kPa using DCS, H2 and PH3 gas at a temperature of 580 to 650 ° C, wherein the PH3 gas flow rate is adjusted to 50 to 500 sccm.

In addition, the method of the present invention further comprises the step of heat-treating in-situ after the step of depositing the polycrystalline silicon layer to make the remaining amorphous silicon layer completely polycrystalline silicon layer, wherein , The heat treatment is carried out in a temperature of 580 ~ 650 ℃ and H2, H2 + N2, He or Ar gas atmosphere.

According to the present invention, after depositing an amorphous silicon layer, a polycrystalline silicon layer is deposited thereon, and the contact resistance is lowered by allowing the silicon epitaxial layer to be grown on the interface with the substrate through the solid phase crystallization of the amorphous silicon layer by heat at this time. In addition, refresh characteristics may be improved by preventing diffusion of phosphorus (P) doped into the polycrystalline silicon layer by the amorphous silicon layer.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A through 1E are cross-sectional views illustrating processes for forming a contact plug according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a silicon substrate 1 having an isolation layer 2, a gate 3, and a junction region 4 defining an active region, and an interlayer insulating layer 5 formed on the entire surface thereof to cover the active region. ). Then, a predetermined portion of the interlayer insulating film 5 is selectively etched to form contact holes 6 for forming bit line contacts and storage node contacts.

Referring to FIG. 1B, dry and wet cleaning are sequentially performed on the substrate resultant to remove residual oxides or etching residues on the surface of the substrate exposed by the contact hole 6, thereby obtaining a clean contact hole bottom. . Subsequently, hydrogen bake (H2 bake) is performed at a temperature of 800 ° C. or higher and a pressure of several mTorr to several tens of Torr while the substrate product is charged in a reactor, thereby allowing interface residues and natural oxide films, etc., on the exposed substrate surface. Remove it.

Referring to FIG. 1C, a low concentration of amorphous silicon layer 7 is deposited on the contact hole 6 and the interlayer insulating film 5 in the reactor. Here, the low-density amorphous silicon layer 7 is deposited with a thickness of 200-1000 Pa at a temperature of 480-580 ° C. using DCS (dichlorosilane: SiCl 2 H 2), H 2, and PH 3 gas, wherein the flow rate of the PH 3 gas is It is set to 0-100 sccm. Although the amorphous silicon layer 7 has a relatively low deposition rate, the step coverage is excellent, which is very advantageous for forming contact plugs.

Referring to FIG. 1D, the doped polycrystalline silicon layer is formed on the amorphous silicon layer again using a DCS, H2, and PH3 gas at a thickness of 580 to 650 ° C., for example, a thickness of 1000 to 2000 kPa. 8) is deposited. At this time, the flow rate of the PH3 gas is about 50 to 500 sccm so that the doping concentration of phosphorus (P) can be appropriately adjusted.

Here, during the deposition of the doped polycrystalline silicon layer 8, a silicon epilayer 9 is formed at the interface between the amorphous silicon layer and the substrate due to the solid phase crystallization by heat applied to the substrate, and the amorphous silicon layer The upper layer is crystallized with a polycrystalline silicon layer.

On the other hand, during deposition of the doped polycrystalline silicon layer 8, the amorphous silicon layer may not all crystallize into the polycrystalline silicon layer due to the lack of heat applied to the substrate. Therefore, in order to crystallize the amorphous silicon layer into a complete polycrystalline silicon layer, an additional heat treatment is performed at a temperature of 580 to 650 ° C in-situ as necessary.

Referring to FIG. 1E, the polycrystalline silicon layer 8 is etched back or chemical mechanical polishing (CMP) until the interlayer insulating film 5 is exposed, thereby forming the contact plug 10. do.

According to the method of the present invention as described above, since the double layer of the amorphous silicon layer and the polycrystalline silicon layer is used as the plug material, the contact resistance between the contact plug and the substrate can be lowered and the refresh characteristics can be improved.

In detail, in general, when silicon is deposited at a temperature of 580 ° C. or lower after hydrogen baking, an amorphous silicon layer is deposited, and subsequently, when the temperature is increased to 580 ° C. or higher in-situ, a polycrystalline silicon layer is deposited. In the process, the silicon epitaxial layer, that is, single crystal silicon, is grown at the interface between the silicon substrate and the amorphous silicon layer by heat, and the contact resistance is improved as the silicon epitaxial layer is present at the contact interface. Here, the silicon epi layer can also be grown by subsequent heat treatment after polycrystalline silicon layer deposition.

In addition, as a low concentration of amorphous silicon layer exists between the substrate surface and the doped polycrystalline silicon layer, diffusion of dopant from the polycrystalline silicon layer to the substrate, i.e., diffusion of phosphorus (P), must pass through the amorphous silicon layer. The amorphous silicon layer functions as a buffer layer that suppresses the diffusion of phosphorus (P), so that the influence of diffusion of phosphorus (P) on the substrate can be minimized. It is possible to improve the refresh characteristics.

As a result, the method of the present invention can greatly improve contact resistance and refresh characteristics by providing a structure capable of lowering the thermal budget while maintaining epitaxial characteristics at the interface.

As described above, the present invention provides a contact by depositing an amorphous silicon layer, then depositing a polycrystalline silicon layer thereon, and allowing the silicon epilayer to be grown on the interface with the substrate through the solid phase crystallization of the amorphous silicon layer by heat at this time. The resistance can be lowered, and the refresh characteristics can also be improved by minimizing the diffusion of phosphorus (P) doped into the polycrystalline silicon layer by the amorphous silicon layer to the substrate.

Therefore, the present invention can lower the contact resistance and at the same time improve the refresh characteristics, and thus can be very advantageously applied to the production of high integration and high speed devices.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (7)

Providing a silicon substrate having an interlayer insulating film formed on a front surface thereof so as to form and cover a predetermined lower structure; Etching the interlayer insulating film to form a contact hole exposing a substrate; Performing a dry and wet cleaning of the substrate surface exposed by the contact hole, followed by hydrogen bake; Depositing an amorphous silicon layer on the contact hole and the interlayer dielectric layer to a predetermined thickness; While depositing a polycrystalline silicon layer with a thickness to fill a contact hole on the amorphous silicon layer, a silicon epitaxial layer is formed at the interface between the amorphous silicon layer and the substrate through heat application during deposition of the polycrystalline silicon layer, and the amorphous silicon Making the upper portion of the layer a polycrystalline silicon layer; And Removing the polycrystalline silicon layer on the interlayer insulating film. The method of claim 1, wherein the amorphous silicon layer A method of forming a contact plug in a semiconductor device, comprising depositing at a thickness of 100 to 1000 Pa using DCS (Diclorosilane: SiCl 2 H 2), H 2 and PH 3 gas at a temperature of 480 to 580 ° C. 3. The method of claim 2, wherein the PH3 gas flow rate is adjusted to 0 to 100 sccm. The method of claim 1, wherein the polycrystalline silicon layer A method of forming a contact plug in a semiconductor device, comprising depositing at a thickness of 1000 to 2000 kPa using DCS (Diclorosilane: SiCl 2 H 2), H 2 and PH 3 gas at a temperature of 580 to 650 ° C. 5. The method of claim 4, wherein the flow rate of the PH3 gas is adjusted to 50 to 500 sccm. The semiconductor device of claim 1, further comprising, after depositing the polycrystalline silicon layer, performing heat treatment on the substrate result in-situ so that the remaining amorphous silicon layer becomes a completely polycrystalline silicon layer. Method of forming a contact plug. The method of claim 4, wherein the heat treatment is performed at a temperature of 580 ° C. to 650 ° C. and at any one gas atmosphere selected from the group consisting of H 2, H 2 + N 2, He, and Ar. .