JP2013105770A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can reduce variation in a depth direction of an upper diffusion layer of a vertical transistor.SOLUTION: A semiconductor device manufacturing method of forming an upper diffusion layer 11 composed of a silicon layer having a flat surface, comprises: selectively and excessively growing a silicon layer having a facet; and subsequently, planarizing a surface of the silicon layer by removing an excess of the silicon layer formed on the surface of an interlayer insulation film 7 by CMP. The silicon layer is grown by selectively epitaxial growing the silicon layer by a single crystal silicon. In this case, because a facet is generated, the silicon layer is excessively grown until the slowest growing facet reaches above the surface of the interlayer insulation film.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Patent Document 1 proposes a technique for forming a semiconductor layer having a uniform concentration profile in the depth direction using an epitaxial growth method as an improved technique for a planar transistor.

  However, in semiconductor devices where progress in miniaturization is remarkable, the planar type that constitutes a transistor on the main surface of a semiconductor substrate is shifted to a vertical type that constitutes a transistor by forming a plurality of pillars (silicon pillars) on the semiconductor substrate. I am doing. The vertical transistor includes an upper diffusion layer provided on the upper side of the silicon pillar, a lower diffusion layer provided on the bottom side of a groove between adjacent silicon pillars, and a silicon substrate sandwiched between the upper diffusion layer and the lower diffusion layer. A channel region, a gate insulating film that covers the peripheral side surface of the channel region, and a gate electrode that covers the surface of the gate insulating film are configured (Patent Document 2). In the vertical transistor, the lower diffusion layer serves as a source or a drain.

FIG. 1 shows a structure of a 4F ^2- cell transistor as an example of a vertical transistor. The manufacturing process until the upper diffusion layer is formed in such a structure will be described with reference to FIGS.

  First, referring to FIG. 2, a plurality of grooves (holes) are formed by etching silicon substrate 1 using pad oxide film 101 and mask nitride film 6 formed as a pattern by lithography and etching, and between adjacent grooves. The silicon pillar 1a is formed. After the impurity implantation for forming the lower diffusion layer 2 is performed below the bottom of the trench, the bottom of the trench and the side surface of the silicon pillar 1a are oxidized to form gate oxide films (gate insulating films) 3 and 4. . After the formation of the gate oxide films 3 and 4, a gate electrode material is deposited, and a gate electrode 5 is formed so as to cover the gate oxide film 4 on the side surface of the silicon pillar 1a by etch back.

  Next, in FIG. 3, a groove between adjacent silicon pillars 1a is filled with an oxide film (interlayer insulating film) 7, and is planarized by CMP (Chemical Mechanical Polishing) to the same height as the upper surface of the mask nitride film 6.

  Next, referring to FIG. 4, mask nitride film 6 and pad oxide film 101 are removed to expose the silicon on silicon pillar 1a. In this state, impurities are implanted to form an LDD (Lightly Doped Drain) 8 of the upper diffusion layer. Subsequently, an insulating film such as a nitride film is deposited and etched back to prevent a short circuit with the gate electrode 5 on the side surface, so that the side of the hole (groove) after the removal of the nitride mask film 6 and the pad oxide film 101 is removed. A wall 9 is formed.

  Next, moving to FIG. 5, the exposed pillar silicon surface is selectively epitaxially grown as a seed layer, thereby forming a low-resistance silicon layer 10 to be an upper diffusion layer.

  Subsequently, in FIG. 6, the upper diffusion layer 11 is formed by implanting impurities into the epitaxially grown silicon layer (hereinafter sometimes referred to as an epi-Si layer) 10.

  Returning to FIG. 1, 14 is a contact bottom metal silicide layer, 15 is a capacitor cylinder contact plug, 16 is an interlayer oxide film, 17 is a cylinder stopper made of a nitride film, 18 is a capacitor dielectric film, 19 is a capacitor lower electrode, and 20 is a capacitor. A cylinder interlayer insulating film 21 is a capacitor upper electrode.

JP 2001-196573 A JP 2008-311641 A

  Incidentally, in the selective epitaxial growth of FIG. 5, the growth rate on the surface of the insulating film is delayed from the growth rate on the silicon surface, so that an inclined surface called a facet as shown in FIG. 5 is generated on the surface of the insulating film. As a result, unevenness occurs on the surface of the epi-Si layer 10. As a result, the upper diffusion layer 11 formed by ion implantation in FIG. 6 also varies in depth (height) due to the unevenness of the surface of the epi-Si layer 10. Moreover, not only does the depth vary within one upper diffusion layer 11, but the depth also varies between the upper diffusion layers 11 formed at different positions. Such variation in depth causes the channel length of the vertical transistor to change locally, making it difficult to obtain desired transistor characteristics.

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of reducing variations in the depth direction of an upper diffusion layer in a vertical transistor.

A method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of semiconductor pillars on a semiconductor substrate using a mask film formed in a pattern,
Forming a lower diffusion layer on the semiconductor substrate on the bottom side of the groove sandwiched between adjacent semiconductor pillars;
A step of depositing an interlayer insulating film from the inside of the groove to the same height as the mask film after forming a gate electrode on the side surface of the groove via an oxide film;
Forming a sidewall on the side surface of the hole or groove formed by removing the mask film and then forming an upper diffusion layer on the upper side of the semiconductor pillar exposed at the bottom surface of the hole or groove; ,including.

  According to the first aspect of the present invention, in the step of forming the upper diffusion layer, the single crystal silicon is selectively formed on the semiconductor pillar exposed on the bottom surface of the hole or groove. Excessive epitaxial growth to the outside, a planarization step of rubbing excess single crystal silicon formed above the upper surface of the interlayer insulating film to the same height as the upper surface of the interlayer insulating film, and the above in the hole or groove Implanting impurities into the single crystal silicon.

  According to the second aspect of the present invention, in the step of forming the upper diffusion layer, the polysilicon is selectively formed on the semiconductor pillar exposed at the bottom surface of the hole or groove in the hole or groove. And epitaxially growing and implanting impurities into the polysilicon in the holes or trenches.

  According to the third aspect of the present invention, the step of forming the upper diffusion layer is performed on the semiconductor pillar exposed at the bottom of the hole or groove up to a height that does not protrude from the hole or groove. Selectively epitaxially growing crystalline silicon, burying the single crystal silicon in the hole or groove and growing polysilicon so as to cover the interlayer insulating film, and above the upper surface of the interlayer insulating film A flattening step of rubbing the formed excess polysilicon to the same height as the upper surface of the interlayer insulating film, and a step of implanting impurities into the single crystal silicon in the hole or groove.

  In any of the first to third aspects, since the silicon plug having a flat surface is obtained in the hole or groove formed by removing the mask film, the upper diffusion layer formed by impurity implantation is The variation in the depth direction can be reduced and the film can be formed stably. This eliminates variations in the characteristics of the vertical transistor due to the difference in channel length.

It is sectional drawing which showed the structural example of the 4F ² cell transistor as an example of the vertical transistor which can apply this invention. It is sectional drawing for demonstrating the manufacturing process until it forms the upper diffusion layer of the vertical transistor shown in FIG. 1 with the manufacturing method until now. FIG. 3 is a cross-sectional view for explaining a manufacturing process subsequent to FIG. 2. FIG. 4 is a cross-sectional view for explaining a manufacturing process subsequent to FIG. 3. FIG. 5 is a cross-sectional view for explaining a manufacturing process subsequent to FIG. 4. FIG. 6 is a cross-sectional view for explaining problems that occur in the manufacturing process subsequent to FIG. 5. It is a figure for demonstrating the manufacturing method by Example 1 of this invention, Comprising: It is sectional drawing for demonstrating the manufacturing process following FIG. FIG. 8 is a cross-sectional view for explaining a manufacturing process subsequent to FIG. 7. FIG. 9 is a cross-sectional view for illustrating the manufacturing process following FIG. 8. It is a figure for demonstrating the manufacturing method by Example 2 of this invention, Comprising: It is sectional drawing for demonstrating the manufacturing process following FIG. It is sectional drawing for demonstrating the manufacturing process following FIG. It is a figure for demonstrating the manufacturing method by Example 3 of this invention, Comprising: It is sectional drawing for demonstrating the manufacturing process following FIG. FIG. 13 is a cross-sectional view for illustrating a manufacturing process following FIG. 12. It is sectional drawing for demonstrating the manufacturing process following FIG. It is sectional drawing for demonstrating the manufacturing process following FIG.

  The present invention intends to form an upper diffusion layer composed of a silicon layer having a flat surface. Specifically, after selectively overgrowing a silicon layer having facets, the surface of the silicon layer is planarized by rubbing the silicon layer formed on the surface of the interlayer insulating film with CMP. Alternatively, a flat layer is obtained by growing a polysilicon layer that does not generate facets. In this case, any of the following methods can be used for the growth of the silicon layer.

  (1) A silicon layer is selectively epitaxially grown with single crystal Si (silicon). In this case, since facets are generated, the growth is sufficiently excessive until the slowest growing facet is located above the surface of the interlayer insulating film (Example 1).

  (2) A silicon layer is selectively grown with polysilicon. In this case, since the facet does not occur in the polysilicon, a silicon layer having a flat surface can be obtained (Example 2).

  (3) A silicon layer is formed by laminating single-crystal Si having facets and polysilicon not generating facets. In this case, the polysilicon may be formed by either selective growth or whole surface growth (Example 3).

  Examples 1 to 3 will be described below.

[Example 1]
Example 1 of the present invention will be described below. After removing the mask nitride film 6 and the pad oxide film 101 (hereinafter collectively referred to as mask film) described with reference to FIG. This process is as described above.

After the formation of the sidewalls 9 described with reference to FIG. 4, the process proceeds to FIG. 7 where single crystal Si 10a is selectively epitaxially grown using the surface of the silicon pillar 1a exposed by removing the mask film as a seed layer. Before setting the semiconductor substrate in the Si selective growth apparatus, the surface of the silicon pillar is washed with a hydrofluoric acid-containing solution to remove the natural oxide film. Next, the cleaned semiconductor substrate is set in a Si selective growth apparatus. After the semiconductor substrate is heated to 800 to 900 ° C., it is heat-treated in a hydrogen atmosphere for 1 to 3 minutes. The surface of the silicon pillar is further cleaned by this hydrogen heat treatment. Subsequently, while maintaining the hydrogen atmosphere, dichlorosilane (SiH ₂ Cl ₂ ) is introduced at, for example, 200 ml / min and hydrogen chloride (HCl) is introduced at, for example, 100 ml / min, and a pressure of 5 to 30 Torr (preferably 15 Torr). The single crystal Si10a is selectively epitaxially grown under the condition. In selective epitaxial growth, an overgrowth is made so that a hole (or groove) formed by removing the mask film is filled and the interlayer insulating film 7 is sufficiently covered until the slowest growth facet in the semiconductor substrate is located above the interlayer insulating film 7. Let

  Since the slowest facet among semiconductor substrates cannot be detected during the growth of single crystal Si 10a, the growth time is controlled empirically based on a preliminary growth test using another semiconductor substrate having the same configuration. (Or set).

  Next, moving to FIG. 8, the single crystal Si 10a that has grown excessively and is formed on the interlayer insulating film 7 is planarized by CMP, and is stopped when the surface of the interlayer insulating film 7 is exposed. By forming the upper diffusion layer 11 by impurity implantation in this state, a uniform upper diffusion layer is formed in the depth direction, and the channel length of the vertical transistor can be kept constant as shown in FIG.

[Example 2]
Next, a second embodiment of the present invention will be described.

  The steps from the removal of the mask film described with reference to FIG. 4 to the formation of the sidewalls 9 by the nitride film are as described above. After the formation of the sidewalls 9 described with reference to FIG. 4, referring to FIG. 10, when the epitaxial growth (epitaxial growth) is performed from above the silicon pillar 1a exposed by the removal of the mask film, the polysilicon 12 is selectively grown. Let Although illustration is omitted, when polysilicon is formed above the upper surface of the interlayer insulating film 7, the polysilicon is planarized by CMP and stopped when the surface of the interlayer insulating film 7 is exposed. . When single crystal silicon is epitaxially grown as in the first embodiment, facets depending on the plane orientation are formed, which causes variations in height (depth). Because there is no height variation, the height variation can be suppressed. If the impurity implantation for forming the upper diffusion layer 11 is performed in this state, as shown in FIG. 11, the uniform upper diffusion layer 11 is formed, so that there is no variation in the characteristics of the vertical transistor due to the difference in channel length. .

  Several methods can be selected for epitaxial growth of polysilicon as described below. The surface of the silicon pillar 1a on which the silicon layer is grown may be entirely or partially covered with a material different from silicon.

  (1) If the different material is a conductor, it may be covered entirely or partially. A metal, a metal silicide, or a metal compound can be used for this conductor. A metal is formed on the entire surface by CVD or sputtering, and then heat-treated at 650 ° C. to form metal silicide on the surface of the silicon pillar 1a. In this case, the surface of the silicon pillar 1a is entirely covered with metal silicide. Thereafter, the unreacted metal formed on the interlayer insulating film 7 is removed. In this state, by selectively growing polysilicon under the conditions described in the first embodiment, it is possible to form polysilicon having a flat surface only on the metal silicide. As the metal, titanium, tungsten, nickel, cobalt, or the like can be used. In this case, the thickness of the metal silicide is preferably 1 to 10 nm.

(2) On the other hand, when the different material is an insulating film, it is necessary to partially cover the surface of the silicon pillar 1a. This is because there is a problem that the contact resistance increases if the entire surface is covered. In other words, the exposed surface of the silicon pillar 1a may be dispersed. The insulating film is preferably an oxide such as silicon oxide. For example, the surface of the silicon pillar 1a can be partially covered with silicon oxide as follows. As described in the first embodiment, before setting the semiconductor substrate in the Si selective growth apparatus, the surface of the silicon pillar is washed with a hydrofluoric acid-containing solution to remove the natural oxide film. Thereafter, the substrate is left in air at room temperature or in an oxygen atmosphere for 1 to 3 minutes to form a new naturally grown silicon oxide film on the surface of the silicon pillar. The thickness of the silicon oxide film formed in this state is about 0.2 nm, and about 50% of the surface is covered with silicon oxide. Next, the semiconductor substrate is set in a Si selective growth apparatus. After heating to 700 to 750 ° C. in a hydrogen atmosphere, dichlorosilane (SiH ₂ Cl ₂ ) is introduced at, for example, 200 ml / min and hydrogen chloride (HCl) is introduced at, for example, 100 ml / min, and 5 to 30 Torr (preferably 15 Torr). The silicon is selectively grown while maintaining the pressure condition. In this case, the growth temperature is 700 to 750 ° C., which is a low temperature as the selective growth condition. Since silicon oxide is hardly reduced even in a hydrogen atmosphere, it remains on the silicon pillar surface as it is. In this state, the epitaxial growth starts independently from the exposed surface of about 50% of the surface of the silicon pillar, and each of the grown Si contacts with the growth and forms an interface. As a whole, it is not single crystal but polycrystalline silicon. Therefore, it can be grown as a polysilicon layer having a flat surface without forming facets.

  In addition to the naturally grown oxide film made of silicon oxide, an oxide film dispersed as described below can be formed. An insulating film having a relatively high dielectric constant such as hafnium oxide or zirconium oxide can be formed by using an atomic layer deposition (ALD) method. For example, in the case of zirconium oxide, the basic steps consist of introduction of tetrakisethylmethylaminozirconium (TEMAZ) as a source gas, source gas purge, ozone introduction, and ozone purge while maintaining the temperature of the semiconductor substrate at 250 ° C. Is repeated for a plurality of cycles to form a desired film thickness. At this time, the film thickness of zirconium oxide formed in one cycle is about 0.1 nm. This corresponds to a state in which about 30% of the surface is coated with zirconium oxide. Therefore, the silicon pillar surface can be partially covered with such an oxide formed by the ALD method, and can be selectively grown as a polysilicon layer having a flat surface.

[Example 3]
Next, Embodiment 3 of the present invention will be described.

  The steps from the removal of the mask film described with reference to FIG. 4 to the formation of the sidewalls 9 by the nitride film are as described above. After the formation of the sidewall 9 described with reference to FIG. 4, referring to FIG. 12, the single crystal Si 10 'is epitaxially grown to such a height that the head does not protrude from the hole (or groove) after removal of the mask film.

  Subsequently, referring to FIG. 13, single crystal Si 10 ′ is buried in polysilicon 13, and the upper diffusion layer is made to have the same height by CMP to the same height as the upper surface of interlayer insulating film 7. Yes (Figure 14). When the upper diffusion layer is formed by impurity implantation in this state, the high concentration implanted layer 11 'is formed of single crystal silicon (FIG. 15). For this reason, even if abnormal growth occurs along the grain boundary of polysilicon when siliciding the upper contact bottom, it is possible to prevent a defect from occurring in the high concentration implantation layer 11 ′. Polysilicon may be formed by either selective growth or overall growth.

[Effect of Example]
According to the first to third embodiments, since the silicon layer having a flat surface can be formed, the height (depth) of the silicon layer serving as the upper diffusion layer is made constant, and the characteristic variation of the vertical transistor is suppressed. I can do it.

  Although the present invention has been described with reference to a plurality of embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the spirit and scope of the present invention described in the claims.

The present invention is suitable for application to, for example, a 4F ^2- cell transistor, but is not limited to this, and can be applied to all vertical transistors including a lower diffusion layer and an upper diffusion layer.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Lower diffused layer 3, 4 Gate oxide film 5 Gate electrode 6 Mask nitride film 7 Interlayer insulating film 8 LDD
9 Side wall 10 Epitaxial growth silicon layer (epi-Si layer)
10 ', 10a Single crystal silicon 11 Upper diffusion layer 11' High concentration injection layer 12, 13 Polysilicon

Claims (11)

Forming a plurality of semiconductor pillars on a semiconductor substrate using a mask film formed in a pattern;
Forming a lower diffusion layer on the semiconductor substrate on the bottom side of the groove sandwiched between adjacent semiconductor pillars;
A step of depositing an interlayer insulating film from the inside of the groove to the same height as the mask film after forming a gate electrode on the side surface of the groove via an oxide film;
Forming a sidewall on the side surface of the hole or groove formed by removing the mask film and then forming an upper diffusion layer on the upper side of the semiconductor pillar exposed at the bottom surface of the hole or groove; Including,
The step of forming the upper diffusion layer includes a step of selectively epitaxially growing single-crystal silicon to the outside of the hole or groove on the semiconductor pillar exposed at the bottom of the hole or groove;
A planarization step of rubbing excess single crystal silicon formed above the upper surface of the interlayer insulating film to the same height as the upper surface of the interlayer insulating film;
And a step of injecting an impurity into the single crystal silicon in the hole or groove.   The method of claim 1, wherein in the step of overgrowing the single crystal silicon to the outside of the hole or groove, the single crystal silicon is excessively epitaxially grown until a facet is formed outside the hole or groove. Semiconductor device manufacturing method.   3. The semiconductor device according to claim 1, wherein a growth time for the overgrowth of the single crystal silicon is set based on a preliminary growth test using another semiconductor substrate having the same configuration. Production method. Forming a plurality of semiconductor pillars on a semiconductor substrate using a mask film formed in a pattern;
Forming a lower diffusion layer on the semiconductor substrate on the bottom side of the groove sandwiched between adjacent semiconductor pillars;
A step of depositing an interlayer insulating film from the inside of the groove to the same height as the mask film after forming a gate electrode on the side surface of the groove via an oxide film;
Forming a sidewall on the side surface of the hole or groove formed by removing the mask film and then forming an upper diffusion layer on the upper side of the semiconductor pillar exposed at the bottom surface of the hole or groove; Including,
The step of forming the upper diffusion layer includes the step of selectively epitaxially growing polysilicon on the semiconductor pillar exposed at the bottom surface of the hole or groove in the hole or groove;
And a step of injecting impurities into the polysilicon in the hole or groove.   In the step of selectively epitaxially growing the polysilicon in the hole or groove, at least a part of the upper surface of the semiconductor pillar exposed at the bottom surface of the hole or groove is covered with a film made of a material different from silicon. The method of manufacturing a semiconductor device according to claim 4, further comprising a step.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the material different from silicon is a conductor material made of any one of metal, metal silicide, and metal compound.   The method of manufacturing a semiconductor device according to claim 6, wherein the metal is titanium, tungsten, nickel, or cobalt.   The method of manufacturing a semiconductor device according to claim 6, wherein a film thickness of the metal silicide is in a range of 1 to 10 nm.   6. The film made of a material different from silicon is an insulating film, and a part of the upper surface of the semiconductor pillar exposed at the bottom surface of the hole or groove is covered with the insulating film. Semiconductor device manufacturing method.   The method for manufacturing a semiconductor device according to claim 9, wherein the insulating film is any one of silicon oxide, hafnium oxide, and zirconium oxide. Forming a plurality of semiconductor pillars on a semiconductor substrate using a mask film formed in a pattern;
Forming a lower diffusion layer on the semiconductor substrate on the bottom side of the groove sandwiched between adjacent semiconductor pillars;
A step of depositing an interlayer insulating film from the inside of the groove to the same height as the mask film after forming a gate electrode on the side surface of the groove via an oxide film;
Forming a sidewall on the side surface of the hole or groove formed by removing the mask film and then forming an upper diffusion layer on the upper side of the semiconductor pillar exposed at the bottom surface of the hole or groove; Including,
The step of forming the upper diffusion layer is a step of selectively epitaxially growing single crystal silicon on the semiconductor pillar exposed at the bottom of the hole or groove to a height that does not come out of the hole or groove;
Burying the single crystal silicon in the hole or groove and growing polysilicon so as to cover the interlayer insulating film;
A planarization step of rubbing excess polysilicon formed above the upper surface of the interlayer insulating film to the same height as the upper surface of the interlayer insulating film;
And a step of injecting an impurity into the single crystal silicon in the hole or groove.

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