KR20010066393A - Method for Manufacturing of Thin Film Trunsistor - Google Patents
Method for Manufacturing of Thin Film Trunsistor Download PDFInfo
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- KR20010066393A KR20010066393A KR1019990068102A KR19990068102A KR20010066393A KR 20010066393 A KR20010066393 A KR 20010066393A KR 1019990068102 A KR1019990068102 A KR 1019990068102A KR 19990068102 A KR19990068102 A KR 19990068102A KR 20010066393 A KR20010066393 A KR 20010066393A
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- 239000010409 thin film Substances 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 24
- 229920005591 polysilicon Polymers 0.000 claims abstract description 24
- 239000012535 impurity Substances 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010408 film Substances 0.000 claims description 93
- 239000007789 gas Substances 0.000 claims description 21
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 239000012159 carrier gas Substances 0.000 claims description 2
- 238000009279 wet oxidation reaction Methods 0.000 claims description 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 abstract 1
- 229910007264 Si2H6 Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 238000005984 hydrogenation reaction Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000003949 trap density measurement Methods 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- General Physics & Mathematics (AREA)
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- Thin Film Transistor (AREA)
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Abstract
Description
본 발명은 반도체 메모리 장치의 제조방법에 관한 것으로서, 특히 스태틱 랜덤 억세스 메모리(Static Random Access Memory: 이하 "SRAM"이라 칭함)의 부하 소자로 사용되는 박막 트랜지스터의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a thin film transistor used as a load element of a static random access memory (hereinafter, referred to as "SRAM").
일반적으로, SRAM은 DRAM(Dynamic Random Access Memory)에 비해 집적도는 떨어지지만, 고속으로 동작하기 때문에 중형 또는 소형 컴퓨터 분야에서 널리 사용되고 있다. 이 SRAM은 통상 두 개의 전송 트랜지스터(access transistor)와 두 개의 구동 트랜지스터(drive transistor), 그리고 두 개의 부하 소자로 이루어지는 플립 플롭(flip flop) 회로로 구성된다. 특히 SRAM 중에서도 부하 소자로 박막 트랜지스터(TFT: Thin Film Transistor)를 채용한 SRAM은 낮은 대기 전류(standby current)를 유지할 수 있으며, 높은 집적도를 갖는다는 장점이 있다.In general, SRAM is less integrated than DRAM (Dynamic Random Access Memory), but is widely used in the medium or small computer field because it operates at a high speed. This SRAM typically consists of a flip flop circuit consisting of two access transistors, two drive transistors, and two load elements. In particular, SRAMs employing thin film transistors (TFTs) as load elements can maintain low standby current and have high integration.
이와 같은 부하소자로 TFT를 채용한 TFT SRAM 소자에서 풀 업(pull-up) 소자로서 PMOS TFT가 사용된다. 이 PMOS TFT의 게이트전극은 구동 트랜지스터와 PMOS TFT를 연결시키는 역할을 하면서 데이터가 저장되는 노드 역할을 수행한다. 이와 같은 PMOS TFT의 게이트전극을 형성하기 위하여 종래에는 주로 다음의 두 가지 방법을 사용하였다.PMOS TFTs are used as pull-up devices in TFT SRAM devices employing TFTs as such load devices. The gate electrode of the PMOS TFT serves to connect the driving transistor and the PMOS TFT and serves as a node for storing data. In order to form the gate electrode of such a PMOS TFT, the following two methods are mainly used in the related art.
첫째, PMOS TFT의 게이트전극으로 도핑되지 않은 폴리실리콘 박막을 형성한후에 불순물 이온을 주입하는 방법이다. 이는, 도핑된 폴리실리콘 박막을 형성하게 되면, 박막 내부의 불순물 입자들이 후속 열공정에 의해 실리콘 기판으로 유입되고, 이로 인해 소자분리된 트랜지스터에서 펀치 쓰루(punch-through) 현상 등이 유발되기 때문에, 이를 방지하기 위하여 사용하는 방법이다. 이 때, 주로 사용하는 불순물 이온으로는 비소(As) 이온이 있다.First, impurity ions are implanted after the undoped polysilicon thin film is formed as the gate electrode of the PMOS TFT. This is because when the doped polysilicon thin film is formed, impurity particles in the thin film are introduced into the silicon substrate by a subsequent thermal process, which causes a punch-through phenomenon in the device-separated transistor. This method is used to prevent this. At this time, arsenic (As) ions are mainly used as impurity ions.
둘째, PMOS TFT의 게이트전극으로 도핑된 폴리실리콘 박막을 직접 형성하는 방법이다. 이는 앞서 설명한 바와 같이, 폴리실리콘 박막 내의 불순물 입자가 실리콘 기판으로 유입되는 문제가 발생할 수 있지만, 공정수의 감소로 인한 생산성 향상을 위하여 최근에 다시 시도되고 있는 방법으로서, 주로 대략 570℃ 이상의 도핑된 폴리실리콘 박막을 증착하여 사용한다.Second, a method of directly forming the polysilicon thin film doped with the gate electrode of the PMOS TFT. As described above, impurity particles in the polysilicon thin film may be introduced into the silicon substrate. However, this method has been recently attempted to improve productivity due to the reduction of the number of processes. A polysilicon thin film is deposited and used.
그런데, 상기 방법들은 TFT의 게이트절연막을 벌크(bulk) 트랜지스터와 같이 열산화막으로 형성할 수 없다는 문제가 있다. 즉, 열산화막 형성 공정 중에, 하부의 폴리실리콘 박막의 그레인 바운더리(grain boundary) 등의 결정 입계 부분과 폴리실리콘 벌크 부분에서의 산화막 성장속도의 차이로 인해 균일한 산화막이 형성되지 않는다. 그리고, 균일하지 않은 산화막의 불규칙한 계면으로 인해 산화막 상부에서 채널을 형성시키기 위한 폴리실리콘막을 형성할 때 핵 생성에 영향을 주어 계면의 트랩 밀도(trap density)를 증가시키는 문제가 있다.However, the above methods have a problem in that the gate insulating film of the TFT cannot be formed of a thermal oxide film like a bulk transistor. That is, during the thermal oxide film forming process, a uniform oxide film is not formed due to the difference in the oxide film growth rate in the grain boundary portion such as the grain boundary of the lower polysilicon thin film and the polysilicon bulk portion. In addition, when the polysilicon film for forming a channel is formed on the oxide film due to the irregular interface of the oxide film, the nucleation is affected, thereby increasing the trap density of the interface.
따라서, 본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 박막 트랜지스터의 게이트절연막으로서 균일한 열산화막을 형성할 수 있도록 하는 SRAM 소자의 부하 소자로 사용되는 박막 트랜지스터를 제조하는 방법을 제공하는 것이다.Accordingly, an object of the present invention is to provide a method for manufacturing a thin film transistor that is used as a load element of an SRAM device capable of forming a uniform thermal oxide film as a gate insulating film of a thin film transistor in order to solve the above problems of the prior art. It is.
도 1은 본 발명에 있어서 게이트 도전막을 형성하는 단계를 도시한 단면도,1 is a cross-sectional view showing a step of forming a gate conductive film in the present invention;
도 2는 본 발명에 있어서 게이트절연막을 형성하는 단계를 도시한 단면도,2 is a cross-sectional view showing a step of forming a gate insulating film in the present invention;
도 3은 본 발명에 있어서 게이트절연막을 형성하는 다른 방법을 설명하기 위한 단면도,3 is a cross-sectional view for explaining another method of forming a gate insulating film in the present invention;
도 4는 본 발명에 있어서 채널 폴리실리콘막을 형성하는 단계를 도시한 단면도,4 is a cross-sectional view showing a step of forming a channel polysilicon film in the present invention;
도 5는 본 발명에 있어서 소오스/드레인 영역을 형성하는 단계를 도시한 단면도이다.5 is a cross-sectional view showing a step of forming a source / drain region in the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100: 절연막 111: 도핑된 비정질실리콘 박막100: insulating film 111: doped amorphous silicon thin film
112: 도핑되지 않은 비정질실리콘 박막112: undoped amorphous silicon thin film
120: 게이트절연막 130: 채널 폴리실리콘막120: gate insulating film 130: channel polysilicon film
140: 산화막 150: 소오스/드레인 영역140: oxide film 150: source / drain region
상기 목적을 달성하기 위하여 본 발명에 따른 박막 트랜지스터의 제조방법은, 반도체기판 상에 형성된 절연막 위에, 도핑된 비정질실리콘 박막 및 도핑되지 않은 비정질실리콘 박막으로 차례로 적층되어 이루어진 게이트 도전막을 형성하는 단계와, 이 게이트 도전막 위에 게이트절연막을 형성하는 단계와, 이 게이트절연막 위에 채널을 형성시키기 위한 채널 폴리실리콘막을 형성하는 단계, 및 채널 폴리실리콘막에 불순물 이온들을 선택적으로 주입시켜 소오스/드레인을 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention includes: forming a gate conductive film formed by sequentially stacking a doped amorphous silicon thin film and an undoped amorphous silicon thin film on an insulating film formed on a semiconductor substrate; Forming a gate insulating film over the gate conductive film, forming a channel polysilicon film for forming a channel on the gate insulating film, and selectively implanting impurity ions into the channel polysilicon film to form a source / drain Characterized in that it comprises a.
본 발명에 있어서, 상기 게이트절연막을 형성한 후에, 상기 게이트절연막과 도핑되지 않은 비정질실리콘 박막 사이에 고온 산화막을 형성하는 단계를 더 포함할 수 있으며, 이 경우 고온 산화막은 대략 800 ∼ 840℃ 정도의 온도와 대략 0.2 ∼ 3torr의 압력에서 SiH2Cl2가스 및 N2O 가스를 소스가스로 사용하여 형성할 수 있다.In the present invention, after the gate insulating film is formed, the method may further include forming a high temperature oxide film between the gate insulating film and the undoped amorphous silicon thin film, in which case the high temperature oxide film is approximately 800 to 840 ° C. It can be formed using SiH 2 Cl 2 gas and N 2 O gas as the source gas at a temperature and pressure of approximately 0.2 to 3 torr.
이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명에 따른 박막 트랜지스터의 제조방법을 설명하기위한 공정 순서도이다.1 to 5 are process flowcharts illustrating a method of manufacturing a thin film transistor according to the present invention.
먼저, 도 1은 게이트 도전막을 형성하는 단계를 나타낸 단면도로서, 이를 참조하여 본 발명의 게이트 도전막 형성 공정을 설명한다.First, Figure 1 is a cross-sectional view showing the step of forming a gate conductive film, with reference to this will be described the gate conductive film forming process of the present invention.
반도체기판(도시되지 않음) 상에, 구동 트랜지스터와 같은 트랜지스터 구조가 배치되어 형성된 반도체 메모리 소자(도시되지 않음)를 절연시키기 위하여 형성된 절연막(100) 위에, 실리콘막(110)을 형성하여 게이트 도전막을 형성한다. 이 실리콘막(110)은 도핑된 비정질실리콘 박막(111)과 도핑되지 않은 비정질실리콘 박막(112)이 순차적으로 적층된 구조를 갖는다.On the semiconductor substrate (not shown), a silicon film 110 is formed on the insulating film 100 formed to insulate a semiconductor memory element (not shown) formed by arranging a transistor structure such as a driving transistor, thereby forming a gate conductive film. Form. The silicon film 110 has a structure in which a doped amorphous silicon thin film 111 and an undoped amorphous silicon thin film 112 are sequentially stacked.
상기 도핑된 비정질실리콘 박막(111)은 저압 화학 기상 증착(LP-CVD) 방법으로 형성할 수 있다. 이 때, 소스 가스로서는 실란(SiH4) 혹은 디실란(Si2H6)과 같은 실리콘(Si) 소스가스와 인산(PH3) 소스가스를 사용하며, PH3소스가스의 캐리어 가스로서는 SiH4, He 혹은 N2가스를 사용한다. 그리고, 증착 압력은 0.2 ∼ 1torr가 되도록 하고, 증착온도는 530℃ 이하의 비교적 낮은 온도를 유지하여 후속 공정에 의한 결정립의 조대화로 인해 게이트절연막과의 계면특성을 향상시키고, 이와 동시에 노드 역할을 수행할 때 비저항이 감소되도록 한다.The doped amorphous silicon thin film 111 may be formed by low pressure chemical vapor deposition (LP-CVD). At this time, a silicon (Si) source gas such as silane (SiH 4 ) or disilane (Si 2 H 6 ) and phosphoric acid (PH 3 ) source gas are used as the source gas, and SiH 4 is used as a carrier gas of the PH 3 source gas. Use He or N 2 gas. In addition, the deposition pressure is 0.2 to 1 torr, and the deposition temperature is maintained at a relatively low temperature of 530 ° C. or lower to improve the interfacial characteristics with the gate insulating film due to coarsening of crystal grains by a subsequent process, and at the same time, serve as a node. The resistivity is reduced when performing.
상기 도핑된 비정질실리콘 박막을 형성한 후에는, 인 시튜(in-situ)로 공정을 진행하되, PH3소스가스의 공급을 중단하여 도핑되지 않은 비정질실리콘 박막(112)을 형성한다. 이 때, 도핑되지 않은 비정질실리콘 박막(112)은 도핑된 비정질실리콘 박막(111)의 대략 10 ∼ 20%의 비율이 되도록 하는 것이 적당하다. 도핑된 비정질실리콘 박막(111)에 대한 도핑되지 않은 비정질실리콘 박막(112)의 비율이 지나치게 낮은 경우에는, 후속 공정인 게이트절연막을 형성하기 위한 열산화막 성장공정과 폴리실리콘막 그레인 성장공정을 동시에 진행시킬 경우에 충분한 도핑되지 않은 층을 공급해 줄 수 없으며, 따라서 이 경우에 열산화막은 도핑되지 않은 층만 이용하여 형성해야 한다. 그리고, 도핑된 비정질실리콘 박막(111)에 대한 도핑되지 않은 비정질실리콘 박막(112)의 비율이 지나치게 높은 경우에는 노드로 작용할 때 캐리어 전자가 부족하게 되어 비저항이 증가할 수 있다.After the doped amorphous silicon thin film is formed, the process is performed in-situ, but the supply of the PH 3 source gas is stopped to form the undoped amorphous silicon thin film 112. At this time, it is appropriate that the undoped amorphous silicon thin film 112 has a ratio of approximately 10 to 20% of the doped amorphous silicon thin film 111. If the ratio of the undoped amorphous silicon thin film 112 to the doped amorphous silicon thin film 111 is too low, the thermal oxide growth process and the polysilicon film grain growth process for forming a gate insulating film, which are subsequent processes, are simultaneously performed. In this case, a sufficient undoped layer cannot be supplied, and in this case, the thermal oxide film should be formed using only the undoped layer. In addition, when the ratio of the undoped amorphous silicon thin film 112 to the doped amorphous silicon thin film 111 is too high, the carrier electrons may be insufficient when acting as a node, thereby increasing the resistivity.
도 2는 게이트절연막을 형성하는 단계를 나타낸 단면도로서, 이를 참조하여 본 발명의 게이트절연막 제조 공정을 설명한다.2 is a cross-sectional view illustrating a step of forming a gate insulating film, and a process of manufacturing the gate insulating film according to the present invention will be described with reference to the drawing.
이에 도핑되지 않은 비정질실리콘 박막(111)을 이용하여 열산화막을 성장시켜 게이트절연막(120)을 형성한다. 이 때, 게이트 도전막인 실리콘막(110)의 하부에 있는 절연막(100) 위에는 열산화막이 형성되지 않도록 상기 열산화막을 선택적으로 형성한다. 그리고, 상기 도핑되지 않은 비정질실리콘 박막(111)의 일부는 남아 있도록 함으로써, 계속된 열공정에 의한 결정화로 생기는 실리콘막(110) 계면에서의 결정립계를 최소화하고, 이로 인해 게이트절연막(120)의 균일도를 향상시키며, 또한 상기 실리콘막(110)의 저항을 감소시킬 수 있다.The thermal oxide film is grown using the undoped amorphous silicon thin film 111 to form the gate insulating film 120. In this case, the thermal oxide film is selectively formed on the insulating film 100 under the silicon film 110 as the gate conductive film so that the thermal oxide film is not formed. In addition, a portion of the undoped amorphous silicon thin film 111 remains, thereby minimizing the grain boundary at the interface of the silicon film 110 caused by the crystallization by the continuous thermal process, thereby uniformity of the gate insulating film 120 In addition, the resistance of the silicon layer 110 may be reduced.
그리고, 상기 게이트절연막(120)은 H2및 O2를 이용한 습식산화 또는 O2를 이용하는 건식산화 방식을 이용하여 형성할 수 있으나, 반드시 이에 한정되는 것은 아니다. 그리고, 상기 게이트절연막(120) 형성을 위한 산화공정은 대략 830℃ 이하의 온도 분위기에서 수행하여, 반도체 메모리 소자의 벌크 구동 트랜지스터(도시되지 않음)가 고온에 의해 열화되는 것을 억제한다.The gate insulating layer 120 may be formed using a wet oxidation method using H 2 and O 2 or a dry oxidation method using O 2 , but is not limited thereto. In addition, the oxidation process for forming the gate insulating film 120 is performed in a temperature atmosphere of about 830 ° C. or less, thereby preventing the bulk driving transistor (not shown) of the semiconductor memory device from being degraded by high temperature.
한편, 상기 게이트절연막(120)을 형성하기 전에, 도핑되지 않은 비정질실리콘 박막(112)의 표면 상에 존재하는 자연산화막 또는 다른 오염 물질들을 제거하기 위하여 전처리 세정공정을 수행할 수 있다. 또한, 상기 게이트절연막(120)을 형성한 후에는, 대략 800 ∼ 830℃ 정도의 온도에서 N2가스를 사용한 어닐링 공정을 인 시츄(in-situ)로 진행하여, 게이트절연막(120)의 특성을 개선하는 동시에 실리콘막(110)의 결정화를 가속시키는 것이 바람직하다.Meanwhile, before forming the gate insulating layer 120, a pretreatment cleaning process may be performed to remove the natural oxide film or other contaminants present on the surface of the undoped amorphous silicon thin film 112. In addition, after the gate insulating film 120 is formed, an annealing process using N 2 gas is performed in-situ at a temperature of about 800 to 830 ° C. to improve the characteristics of the gate insulating film 120. It is desirable to improve the crystallization of the silicon film 110 while improving it.
도 3은 게이트절연막을 형성하는 다른 방법을 나타낸 단면도로서, 이를 참조하여 본 발명의 게이트절연막 제조 공정을 설명한다.3 is a cross-sectional view showing another method of forming a gate insulating film, with reference to this will be described the gate insulating film manufacturing process of the present invention.
앞서 설명한 바와 같이, 게이트도전막으로서의 실리콘(110)을 형성한 후, 도핑되지 않은 비정질실리콘 박막(112)의 상부에 50Å미만의 얇은 열산화막(121)을 형성한 후, SiH2Cl2가스와 N2O 가스를 소스가스로 이용하여 고온산화막(Hot temperature Oxide)(122)을 형성한다. 이때, 상기 열산화막(121)은 830℃이하의 온도분위기에서 형성되고, 고온산화막(122)의 증착 온도는 800 ∼ 840℃ 정도가 되도록 하며, 증착 압력은 0.2 ∼ 3torr의 비교적 낮은 압력이 되도록 한다.As described above, after forming the silicon 110 as the gate conductive film, after forming a thin thermal oxide film 121 of less than 50 Å on top of the undoped amorphous silicon thin film 112, the SiH 2 Cl 2 gas and Hot temperature oxide 122 is formed using N 2 O gas as the source gas. At this time, the thermal oxide film 121 is formed in a temperature atmosphere of 830 ℃ or less, the deposition temperature of the high temperature oxide film 122 is about 800 ~ 840 ℃, the deposition pressure is to be a relatively low pressure of 0.2 ~ 3torr. .
도 4는 채널 폴리실리콘막을 형성하는 단계를 나타낸 단면도로서, 이를 참조하여 본 발명의 채널 폴리실리콘막 제조 공정을 설명한다.4 is a cross-sectional view illustrating a step of forming a channel polysilicon film, and a process of manufacturing the channel polysilicon film of the present invention will be described with reference to this.
도 2 또는 도 3의 결과물의 전면에 도핑되지 않은 채널 폴리실리콘막(130)을 형성한다. 상기 채널 폴리실리콘막(130)은 480℃ 정도의 낮은 온도에서 Si2H6소스가스를 이용한 저압 화학 기상 증착(LP-CVD) 방법을 사용하여 형성할 수 있다. 다음에, 약 620℃ 이상의 열공정으로 고상성장(Solid Phase Growth; SPG) 어닐링을 수행하여 그레인의 조대화를 실현한다. 이 때, 열산화막(120)과의 계면에서 발생하는 트랩 밀도(trap density)를 최소화하기 위하여, Si 댕글링(dangling) 결합에 H를 결합시키는 수소화 패시베이션(passivation) 공정을 수행한다. 즉, 금속층 증착 후에 수행하는 N2어닐링시에 대략 420℃ 정도의 온도에서 N2와 H2를 동시에 공급함으로써, 수소화 패시베이션 공정을 수행할 수 있다.An undoped channel polysilicon film 130 is formed on the entire surface of the resultant of FIG. 2 or FIG. 3. The channel polysilicon layer 130 may be formed using a low pressure chemical vapor deposition (LP-CVD) method using a Si 2 H 6 source gas at a temperature as low as 480 ° C. Next, solid phase growth (SPG) annealing is performed in a thermal process of about 620 ° C. or more to realize grain coarsening. At this time, in order to minimize the trap density generated at the interface with the thermal oxide film 120, a hydrogenation passivation process is performed in which H is bonded to the Si dangling bond. That is, the hydrogenation passivation process may be performed by simultaneously supplying N 2 and H 2 at a temperature of about 420 ° C. during N 2 annealing performed after metal layer deposition.
한편, 상기 채널 폴리실리콘막(130)을 형성하기 이전에, 게이트절연막의 표면의 오염을 제거하기 위한 전처리 세정 공정을 수행하는 것이 바람직하다. 이 경우에 사용하는 화학 약품으로서 50:1 또는 100:1의 혼합 비율을 갖는 불산(HF)을 사용할 수 있다.Meanwhile, before the channel polysilicon film 130 is formed, it is preferable to perform a pretreatment cleaning process for removing contamination of the surface of the gate insulating film. In this case, hydrofluoric acid (HF) having a mixing ratio of 50: 1 or 100: 1 can be used as the chemical used.
도 5는 소오스/드레인 영역을 형성하는 단계를 나타낸 단면도로서, 이를 참조하여 본 발명의 소오스/드레인 영역 제조 공정을 설명한다.5 is a cross-sectional view illustrating a step of forming a source / drain region, and a process of manufacturing the source / drain region of the present invention will be described with reference to the figure.
채널 폴리실리콘막(130)의 표면에 30Å 정도 두께의 산화막(140)을 형성한다. 이어서, 상기 산화막(140) 위에 통상의 사진공정에 의해 소오스/드레인 영역이 형성될 영역을 한정하는 포토레지스트 패턴(도시되지 않음)을 형성한다. 다음에, 이 포토레지스트 패턴을 이온주입 마스크로 사용하여 불순물 이온, 예를 들어 이불화붕소(BF2)를 이온주입하여 P+형의 소오스/드레인 영역(150)을 형성하며, 이에 따라 채널 폴리실리콘막(130) 내에는 채널 영역 및 옵셋(offset) 영역이 형성된다.An oxide film 140 having a thickness of about 30 μs is formed on the surface of the channel polysilicon film 130. Subsequently, a photoresist pattern (not shown) is formed on the oxide layer 140 to define a region in which the source / drain regions are to be formed by a normal photolithography process. Next, using this photoresist pattern as an ion implantation mask, impurity ions such as boron difluoride (BF 2 ) are ion implanted to form a P + type source / drain region 150, thereby channel poly Channel regions and offset regions are formed in the silicon film 130.
상술한 바와 같이, 본 발명에 따른 SRAM 소자의 부하소자로 사용되는 박막 트랜지스터의 제조방법에 의하면, 도핑된 비정질실리콘 박막과 도핑되지 않은 비정질실리콘 박막을 순차 적층하여 게이트전극을 형성함으로써, 후속 게이트절연막 형성공정에서 균일도가 높은 열산화막을 형성할 수 있으며, 실리콘막의 그레인을 조대화시켜 노드 역할시에 폴리실리콘막의 비저항을 감소시킬 수 있다. 또한, 열산화막을 상기 게이트전극용 실리콘막 위에만 선택적으로 형성시킴으로써, 불필요한 산화막 생성을 억제할 수 있다는 이점도 있다.As described above, according to the method of manufacturing a thin film transistor used as a load element of an SRAM device according to the present invention, a doped amorphous silicon thin film and an undoped amorphous silicon thin film are sequentially stacked to form a gate electrode, thereby forming a subsequent gate insulating film. In the forming process, a highly uniform thermal oxide film may be formed, and the grain resistance of the silicon film may be coarsened to reduce the resistivity of the polysilicon film in the role of a node. Further, by selectively forming a thermal oxide film only on the silicon film for gate electrodes, there is an advantage that unnecessary oxide film formation can be suppressed.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8513671B2 (en) | 2010-05-26 | 2013-08-20 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same |
| US8927991B2 (en) | 2010-10-27 | 2015-01-06 | Samsung Display Co., Ltd. | Organic light emitting diode display device and manufacturing method thereof |
| US9570534B2 (en) | 2010-06-30 | 2017-02-14 | Samsung Display Co., Ltd. | Organic light emitting diode display |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8513671B2 (en) | 2010-05-26 | 2013-08-20 | Samsung Display Co., Ltd. | Display device and method of manufacturing the same |
| US9570534B2 (en) | 2010-06-30 | 2017-02-14 | Samsung Display Co., Ltd. | Organic light emitting diode display |
| US8927991B2 (en) | 2010-10-27 | 2015-01-06 | Samsung Display Co., Ltd. | Organic light emitting diode display device and manufacturing method thereof |
| US9070904B2 (en) | 2010-10-27 | 2015-06-30 | Samsung Display Co., Ltd. | Method of manufacturing organic light emitting diode display |
| TWI563649B (en) * | 2010-10-27 | 2016-12-21 | Samsung Display Co Ltd | Organic light emitting diode display device and manufacturing method thereof |
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| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid |