CN114678325A - Method for filling polycrystalline silicon in contact hole - Google Patents

Method for filling polycrystalline silicon in contact hole Download PDF

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Publication number
CN114678325A
CN114678325A CN202011553806.5A CN202011553806A CN114678325A CN 114678325 A CN114678325 A CN 114678325A CN 202011553806 A CN202011553806 A CN 202011553806A CN 114678325 A CN114678325 A CN 114678325A
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Prior art keywords
contact hole
layer
polysilicon
polycrystalline silicon
filling
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CN202011553806.5A
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Inventor
崔锺武
金成基
刘金彪
杨涛
贺晓彬
项金娟
王垚
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Priority to CN202011553806.5A priority Critical patent/CN114678325A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1068—Formation and after-treatment of conductors

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

The invention relates to a method for filling polycrystalline silicon in a contact hole. The method for filling the contact hole with the polysilicon comprises the following steps: forming a contact hole on a semiconductor substrate; depositing a first layer of polycrystalline silicon on the bottom wall and the side wall of the contact hole, and then injecting ions into the first layer of polycrystalline silicon; and depositing a second layer of polysilicon on the surface of the first layer of polysilicon to fill the contact hole, and then carrying out annealing treatment. The invention fills the polycrystalline silicon as the conductive medium in two stages, can improve the density and the film uniformity of the medium, reduce the contact resistance, has controllable process conditions and few influencing factors, and obtains devices with high consistency among batches.

Description

Method for filling polycrystalline silicon in contact hole
Technical Field
The invention relates to the field of semiconductor production processes, in particular to a method for filling polycrystalline silicon in a contact hole.
Background
In the manufacturing process of a DRAM (Dynamic Random Access Memory) device, a polysilicon (poly) is deposited to form contact films such as a Bit line contact (Bit line contact) conductive structure and a Storage node contact (Storage node contact) conductive structure, which are generally called "plugs". As integrated circuits shrink in size, the demand for contact resistance of polysilicon plugs increases. If the polysilicon is not well buried during deposition, contact resistance may be increased or voids may be generated, resulting in a decrease in device yield and quality.
In the prior art, in order to improve the filling quality of polycrystalline silicon, after a contact hole is formed, all silicon is filled at one time, ion doping is completed simultaneously, and the filling quality is controlled by adjusting parameters such as deposition temperature, doping concentration, N junction doping concentration or annealing temperature after deposition, however, the method has many uncontrollable factors, and the quality uniformity of devices among batches is poor.
Therefore, the invention is especially provided.
Disclosure of Invention
The invention mainly aims to provide a method for filling polycrystalline silicon in a contact hole, which fills the polycrystalline silicon in two stages as a conductive medium, can improve the density and film uniformity of the medium and reduce the contact resistance, has controllable process conditions, few influencing factors and high consistency among batches of obtained devices.
In order to achieve the above object, the present invention provides the following technical solutions.
The method for filling the contact hole with the polysilicon comprises the following steps:
forming a contact hole on a semiconductor substrate;
depositing a first layer of polycrystalline silicon on the bottom wall and the side wall of the contact hole, and then injecting ions into the first layer of polycrystalline silicon;
and depositing a second layer of polysilicon on the surface of the first layer of polysilicon to fill the contact hole, and then carrying out annealing treatment.
Compared with the prior art, the method has the advantages that the filling of the polycrystalline silicon is divided into two stages, and the ions are injected into the polycrystalline silicon deposited in the first stage, so that the depth of the doped ions in the polycrystalline silicon filler can be increased, the concentration of the doped ions in the boundary of the polycrystalline silicon filler is improved, meanwhile, the density of the material can be improved by depositing the polycrystalline silicon in two stages, the resistance of the polycrystalline silicon in the contact hole is reduced from the two aspects, and a favorable basis is provided for improving the device point characteristic.
The contact holes in the present invention may be holes that function as conductive contacts in any semiconductor device (including but not limited to DRAMs, FLASH, logic devices, etc.), such as bit line contact holes or storage node contact holes in a typical DRAM.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
FIG. 1 is a schematic diagram of a partial structure of a DRAM according to the present invention;
FIG. 2 is an enlarged schematic view of the bit line contact of FIG. 1;
fig. 3 is a flow chart of a method for filling polysilicon according to the present invention.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
As shown in the DRAM structures of fig. 1 and 2, the bit line contact 105 and the storage node contact plug 104 are shown, and material characteristics such as resistance and uniformity of the two contacts are critical to the electrical performance of the device, for example, the resistance of the bit line contact 105 and the storage node contact plug 104 to the contact of the N-junction 106 on the bottom substrate (the contact is shown in the dashed box in fig. 1) is critical to the device performance. The process of the invention is mainly suitable for devices with polycrystalline silicon as the contact material. The invention improves the deposition method of the polysilicon in consideration of both the consistency of the device quality and the low resistance of the contact.
First, the manufacturing process of the bit line contact hole is performed.
A device isolation structure STI102 and a transistor including an active region and a buried gate 103 may be formed on a semiconductor substrate 101, and the active region is isolated by the isolation structure. The semiconductor substrate may be any substrate known to those skilled in the art for supporting components of a semiconductor integrated circuit, such as silicon-on-insulator (SOI), bulk silicon (bulk silicon), germanium, silicon germanium, gallium arsenide, or germanium-on-insulator (ge), etc. The method for forming the buried gate may include etching the substrate using a patterned photolithography method to form a buried gate trench; then forming a grid oxide layer; the partially filled metal layer then forms a word line. Next, an insulating layer is formed on the semiconductor substrate, and the insulating layer is etched by a patterning method until the active region is exposed, thereby forming a bit line contact hole 107 in the insulating layer. Then, the substrate having the bit line contact hole is cleaned. The substrate may then be placed in a deposition furnace in preparation for deposition of polysilicon.
The filling of the polysilicon in the bit line contact hole may then be performed.
Typically a dry or wet clean is performed prior to deposition, optionally followed by an inert gas (or nitrogen N)2Etc.) is then purged, followed by deposition of a first layer of polysilicon 108 on the bottom and sidewalls of the contact hole 107, at a reduced thickness, the first layer of polysilicon 108 remaining at a thickness that is maintained for typical DRAM structures
Figure BDA0002857930280000031
Preferably, a thin layer of polysilicon is deposited on the walls of the contact holes, as shown in figure 2. The polysilicon material may be amorphous silicon (amorphous silicon) or crystalline silicon, the first layer of polysilicon 108 may be deposited by Low Pressure Chemical Vapor Deposition (LPCVD) or Atomic Layer Deposition (ALD) or a composite method of atomic layer Seed (Seed) deposition and LPCVD or Plasma Enhanced Chemical Vapor Deposition (PECVD), and the silicon source may be silane, dichlorosilane, disilane, diisopropylaminosilane, bis (tert-butylamino) silane, bis (diethylamino) silane, hexachlorodisilane, tris (dimethylamino) silane, butylaminosilane, diethylaminosilane, dipropylaminosilane, hexaethylaminodisilane, or other typical silicon sources.
Then, ion implantation can be performed to improve material characteristics such As crystal defects, the ion type includes but is not limited to Ge and As, and the process conditions during ion implantation are preferably 1 KeV-10 KeV, 5E 14-1E 16ions/cm2. Because a small part of silicon is filled at the moment, doping ions are implanted to a deeper depth in the overall filler (polycrystalline silicon) of the contact hole and are close to contact interfaces with surrounding structures such as N junctions, source drains and the like, so that the contact resistance between the doping ions and the structures can be greatly reduced;
next, the second layer of polysilicon 109 may be filled, conventionally cleaned (dry or wet) prior to filling, and deposited on the surface of the first layer of polysilicon to a thickness sufficient to form contact plugs, as shown in fig. 3. The polysilicon deposition may be the same as or different from the first layer, such as a Low Pressure Chemical Vapor Deposition (LPCVD) process or an Atomic Layer Deposition (ALD) process or a combination of atomic layer Seed (Seed) deposition and LPCVD process or a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and the silicon source may be a typical silicon source such as monosilane, dichlorosilane, disilane, diisopropylaminosilane, bis (tert-butylamino) silane, bis (diethylamino) silane, hexachlorodisilane, tris (dimethylamino) silane, butylaminosilane, diethylaminosilane, dipropylaminosilane, hexaethylaminodisilane, etc.
And finally, annealing treatment can be carried out to refine grains and improve the crystal orientation, the common annealing mode is rapid thermal treatment (RTP), the treatment temperature is preferably 800-1000 ℃, and the atmosphere during the thermal treatment is preferably inert or vacuum.
After the annealing treatment is completed, the bit line main body can be formed continuously, for example, a lamination of the barrier layer, the metal layer and the insulating cap layer can be deposited, the lamination and the contact part are etched, a bit line main body structure is formed, and finally, side walls can be formed on two sides of the bit line main body structure.
In addition, in the above description, the filling of the polysilicon can be performed in two stages, and the buffering and repairing steps such as cleaning and the like are provided in the middle, so that the defects such as holes and the like can be reduced, and the density of the material can be improved.
After the bit lines are formed, a process method in which the embodiments of the present application are applied to the storage node contacts is described below.
After the bit line is manufactured, the isolation layer above the semiconductor substrate is etched by taking the bit line main body and the side wall as masks until the active region is exposed, and a groove is formed. A dielectric layer may be formed in the trench and then photolithography may be performed to form a storage node contact hole exposing the active region. The structure may then be fed into a deposition furnace ready to be filled with polysilicon; the manner of filling the polysilicon in this step is the same as that in the second step, and the same technical effect can be achieved. In another mode, polysilicon can be formed in the trench, then the polysilicon is patterned to form a plug, the polysilicon film can be patterned by dry etching until the active region is exposed, and the remaining polysilicon is used as a contact portion.
Fabrication of the contact pads and capacitors may then be further performed to complete the fabrication of the DRAM cell.
The present invention also provides a preferred embodiment for filling polysilicon in contact holes in a DRAM, the filling process is shown in fig. 3, and includes:
step s1 of forming a contact hole on the semiconductor substrate;
step s2, cleaning the surface of the contact hole;
step s3, first phase deposition: depositing a first layer of polysilicon on the bottom wall and the side wall of the contact hole, and keeping the deposition thickness at
Figure BDA0002857930280000051
Step s4, ion implantation;
step s5, cleaning;
step s6, second phase deposition: depositing the residual polysilicon;
step s7, annealing, wherein the annealing temperature is 800-1000 ℃;
step s8, follow-up procedure, as described above.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. The method for filling the polycrystalline silicon in the contact hole is characterized by comprising the following steps:
forming a contact hole on a semiconductor substrate;
depositing a first layer of polycrystalline silicon on the bottom wall and the side wall of the contact hole, and then injecting ions into the first layer of polycrystalline silicon;
and depositing a second layer of polysilicon on the surface of the first layer of polysilicon to fill the contact hole, and then carrying out annealing treatment.
2. The method of claim 1, wherein the first layer of polysilicon has a film thickness of
Figure FDA0002857930270000011
3. The method of claim 1, wherein the implanted ions are of a type including at least one of Ge and As.
4. The method according to claim 1 or 3, wherein the process conditions for implanting ions are as follows: 1KeV to 10KeV, 5E14 to 1E16ions/cm2。
5. The method of claim 1, wherein the annealing process is a rapid thermal process.
6. The method according to claim 5, wherein the temperature of the annealing treatment is 800 to 1000 ℃.
7. The method of claim 1 wherein the first layer of polysilicon is deposited by CVD, ALD or LPCVD.
8. The method of claim 1, wherein the second layer of polysilicon is deposited by CVD, ALD, or LPCVD.
9. The method of claim 1, wherein the contact hole is a bit line contact hole or a storage node contact hole.
10. The method of claim 1 or 9, wherein the contact hole is a contact hole in a DRAM.
CN202011553806.5A 2020-12-24 2020-12-24 Method for filling polycrystalline silicon in contact hole Pending CN114678325A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024000726A1 (en) * 2022-06-30 2024-01-04 长鑫存储技术有限公司 Method for manufacturing semiconductor structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024000726A1 (en) * 2022-06-30 2024-01-04 长鑫存储技术有限公司 Method for manufacturing semiconductor structure

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