CN115621116A - Method for manufacturing polycrystalline silicon film layer for split gate - Google Patents
Method for manufacturing polycrystalline silicon film layer for split gate Download PDFInfo
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- CN115621116A CN115621116A CN202211233767.XA CN202211233767A CN115621116A CN 115621116 A CN115621116 A CN 115621116A CN 202211233767 A CN202211233767 A CN 202211233767A CN 115621116 A CN115621116 A CN 115621116A
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- polycrystalline silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28229—Making the insulator by deposition of a layer, e.g. metal, metal compound or poysilicon, followed by transformation thereof into an insulating layer
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/24—Deposition of silicon only
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/52—Controlling or regulating the coating process
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/56—After-treatment
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B28/00—Production of homogeneous polycrystalline material with defined structure
- C30B28/12—Production of homogeneous polycrystalline material with defined structure directly from the gas state
- C30B28/14—Production of homogeneous polycrystalline material with defined structure directly from the gas state by chemical reaction of reactive gases
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
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- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
- C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
- C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
Abstract
The invention discloses a method for manufacturing a polycrystalline silicon film layer for split gate, which comprises the following steps: providing a semiconductor substrate to be deposited with polycrystalline silicon, wherein the semiconductor substrate is provided with a groove; placing the semiconductor substrate in a deposition furnace, and heating to T 1 Then keeping the temperature constant, and carrying out silicon deposition under the constant temperature condition to form a polycrystalline silicon film layer; then rise at a certain rateTemperature to T 2 Annealing treatment is carried out after temperature rise; wherein, T 2 ＞T 1 (ii) a And doping the polycrystalline silicon film layer. The invention effectively improves the uniformity and thickness of the polycrystalline silicon film layer and greatly improves the performance of the split gate.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a polycrystalline silicon film layer for split gate.
Background
In the manufacturing process of the existing Split Gate Power MOS (Split Gate Power field effect transistor), a polysilicon film layer is deposited and formed as an IPO (inter-Gate oxide layer), and then the polysilicon film layer is doped, so that the conductivity of the polysilicon film layer is adjusted. However, due to the doping method, the impurity distribution in the IPO (inter-gate oxide) is not uniform, and the thickness is not as thick as required. In order to improve the quality of the IPO, the reaction temperature and doping concentration need to be adjusted to improve the uniformity and thickness of the IPO.
In view of the above, the prior art should be improved to solve the above technical problems in the prior art.
Disclosure of Invention
In order to solve the technical problem in the prior art, the invention provides a method for manufacturing a polycrystalline silicon film for split gate, which can effectively improve the uniformity and thickness of the polycrystalline silicon film.
According to the invention, the method for manufacturing the polycrystalline silicon film layer for the split gate comprises the following steps: providing a semiconductor substrate to be deposited with polycrystalline silicon, wherein the semiconductor substrate is provided with a groove; placing the semiconductor substrate in a deposition furnace, and heating to T 1 Then keeping the temperature constant, and carrying out silicon deposition under the constant temperature condition to form a polycrystalline silicon film layer; then heating to T at a certain rate 2 Annealing treatment is carried out after temperature rise; wherein, T 2 ＞T 1 (ii) a And doping the polycrystalline silicon film layer.
According to one embodiment of the invention, said T 1 The temperature interval of (A) is 500-550 ℃.
According to one embodiment of the invention, said T 2 The temperature interval of (A) is 580-620 ℃.
According to one embodiment of the invention, the doping process comprises: and doping the polycrystalline silicon film layer by ion implantation of doping elements.
According to one embodiment of the present invention, the ion implantation is performed with PH as the raw material 3 。
According to one embodiment of the invention, PH is introduced into the apparatus 3 The flow rate of (2) is 70-100 ccm.
According to one embodiment of the invention, the polysilicon film layer is deposited by chemical vapor deposition.
According to one embodiment of the invention, the silicon deposition is performed under low pressure conditions.
According to one embodiment of the present invention, the thickness of the polysilicon film layer is in the range of
According to one embodiment of the invention, the temperature rise process is constant temperature rise.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages: compared with the traditional polycrystalline silicon film structure, the novel polycrystalline silicon film manufactured by the manufacturing method of the invention has the advantages that the oxidation rate is improved, the uniformity and the thickness of IPO are improved, crystal grains are reduced, the non-crystallization degree is better, and the problem that the polycrystalline silicon is in a V-shaped structure after etching is solved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some implementation examples of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 shows a schematic flow diagram of a method for fabricating a polysilicon film layer for split gate according to an exemplary embodiment of the present invention;
FIG. 2 shows an electron micrograph of a prior art synthesized IPO;
FIG. 3 is a graph illustrating the ratio of the thickness of a polysilicon oxide film to the thickness of bare silicon when the PH3 concentration is increased to 86ccm at various temperatures according to an exemplary embodiment of the invention;
FIG. 4 shows an electron microscope scanning photograph of amorphous silicon synthesized under different temperature conditions, according to an exemplary embodiment of the present invention;
FIG. 5 shows electron microscope scanning photographs of the content of polysilicon grains at different temperature conditions, according to an exemplary embodiment of the present invention;
fig. 6 shows an electron microscope scanning photograph of the shape of the polysilicon recess after etching under different reaction conditions, according to an exemplary embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are used merely for convenience of description and simplification of the description, but do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
As shown in fig. 1 to 6, the present invention provides a method for fabricating a polysilicon film layer for split gate, which includes: providing a semiconductor substrate to be deposited with polycrystalline silicon, wherein the semiconductor substrate is provided with a groove; placing the semiconductor substrate in a deposition furnace, and heating to T 1 Then keeping the temperature constant, and carrying out silicon deposition under the constant temperature condition to form a polycrystalline silicon film layer; then heating to T at a certain rate 2 Annealing treatment is carried out after temperature rise; wherein, T 2 ＞T 1 (ii) a And doping the polycrystalline silicon film layer.
According to the method for manufacturing the polycrystalline silicon film layer, only the reaction temperature and the doping concentration need to be adjusted, other steps do not need to be additionally added, and the uniformity and the thickness of the polycrystalline silicon film layer are improved on the premise of not increasing the cost.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing a polysilicon film layer for split gate according to an exemplary embodiment of the present invention, which may specifically include:
s1, providing a semiconductor substrate to be deposited with polycrystalline silicon, wherein the semiconductor substrate is provided with a groove;
s2, placing the semiconductor substrate in a deposition furnace, and heating to T 1 Then, keeping the constant temperature;
s3, carrying out silicon deposition under a constant temperature condition to form a polycrystalline silicon film layer;
s4, doping the polycrystalline silicon film layer;
s5, raising the temperature to T after etching 2 And annealing treatment is carried out after the temperature is raised.
The trench in step S1 is used to deposit polysilicon.
The deposition furnace in the step S2 is a chemical vapor deposition furnace, and T is 1 The temperature of (2) is in the range of 500 to 550 ℃, preferably 525 ℃. As can be seen from fig. 4 and 5, the thickness and uniformity of the amorphous silicon are more excellent when the temperature is raised to 525 ℃, and the grain size is significantly less than 550 ℃, which is also more excellent in the degree of amorphization.
In the step S3, the polysilicon film layer is deposited by a chemical vapor deposition method, which may be a Low Pressure Chemical Vapor Deposition (LPCVD) method or a Plasma Enhanced Chemical Vapor Deposition (PECVD) method, and is preferably low pressure chemical vapor deposition because of its characteristics of fast growth rate, compact and uniform film formation, large loading capacity, and the like, and the growth rate of the polysilicon film layer is 1 to 2nm/min.
The doping process in step S4 specifically includes ion doping, and the ion doping can meet the requirement of high-purity doping, thereby improving the performance of the semiconductor device. The doping is achieved by ion implantation, the preferred doping element being P (phosphorus),the ion implantation is performed with pH as a raw material 3 Introducing PH into the equipment 3 The flow rate of (2) is 70 to 100ccm, preferably 86ccm. As can be seen from FIG. 3, when the pH is adjusted 3 The flow rate of the silicon oxide film is increased to 86ccm, and when the deposition temperature is 550 ℃, the ratio of the thickness of the polysilicon oxide film layer at the deposition center to the thickness of the bare silicon can reach 5 times, and the thickness of the polysilicon oxide film layer at the edge can also reach 4.6 times; when the deposition temperature is 525 ℃, the ratio of the thicknesses of the polycrystalline silicon oxide film layer and the bare silicon at the center and the edge of the deposition can reach more than 4.8 times, and the requirement of high oxidation rate can be met.
In the step S5, the doped polysilicon film layer is etched to form a uniform polysilicon film layer, and as can be seen from fig. 6, after the polysilicon deposited by heating to 525 ℃ is etched, V-shaped depressions are generated. Thus raising the temperature to T 2 Said T is 2 The temperature range of (A) is 580 to 620 ℃, preferably 600 ℃. The temperature rise process is constant temperature rise with the speed of 5 ℃/min. Specifically, the problem can be effectively improved by continuously increasing the deposition amount of the polycrystalline silicon on the surface of the polycrystalline silicon film layer and carrying out annealing treatment at 600 ℃, so that the etched polycrystalline silicon forms a flat and horizontal rectangular surface. The thickness of the finally formed polysilicon film layer is within the range of
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for manufacturing a polycrystalline silicon film layer for split gate comprises the following steps:
providing a semiconductor substrate to be deposited with polycrystalline silicon, wherein the semiconductor substrate is provided with a groove; placing the semiconductor substrate in a deposition furnace, and heating to T 1 Then keeping the temperature constant, and carrying out silicon deposition under the constant temperature condition to form a polycrystalline silicon film layer; then heating to T at a certain rate 2 Annealing treatment is carried out after temperature rise;
wherein, T 2 ＞T 1 ；
And doping the polycrystalline silicon film layer.
2. The method of claim 1, wherein the T is selected from the group consisting of 1 The temperature interval of (A) is 500-550 ℃.
3. The method of claim 1, wherein the T is the same as the T 2 The temperature interval of (A) is 580-620 ℃.
4. The method of claim 1, wherein the doping comprises: and doping the polycrystalline silicon film layer by ion implantation of doping elements.
5. The method as claimed in claim 4, wherein the ion implantation is performed with pH 3 。
6. The method of claim 1, wherein PH is introduced into the apparatus 3 The flow rate of (2) is 70-100 ccm.
7. The method of claim 1, wherein the polysilicon film is deposited by chemical vapor deposition.
8. The method of claim 1, wherein the silicon deposition is performed at low pressure.
9. The method of claim 1, wherein the polysilicon film has a thickness in the range of about
10. The method for manufacturing a polycrystalline silicon film layer for Splitgate according to claim 1, wherein the temperature rise process is constant temperature rise.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211233767.XA CN115621116A (en) | 2022-10-10 | 2022-10-10 | Method for manufacturing polycrystalline silicon film layer for split gate |
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| CN202211233767.XA CN115621116A (en) | 2022-10-10 | 2022-10-10 | Method for manufacturing polycrystalline silicon film layer for split gate |
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| CN115621116A true CN115621116A (en) | 2023-01-17 |
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| CN202211233767.XA Pending CN115621116A (en) | 2022-10-10 | 2022-10-10 | Method for manufacturing polycrystalline silicon film layer for split gate |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5597754A (en) * | 1995-05-25 | 1997-01-28 | Industrial Technology Research Institute | Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process |
| JPH11251244A (en) * | 1992-04-30 | 1999-09-17 | Toshiba Corp | Semiconductor device and manufacture of the same |
| KR20040096340A (en) * | 2003-05-09 | 2004-11-16 | 주식회사 하이닉스반도체 | Method for forming contact plug of semicondutor device |
| JP2005191480A (en) * | 2003-12-26 | 2005-07-14 | Fuji Photo Film Co Ltd | Manufacturing method of solid-state imaging device |
| US20050191800A1 (en) * | 2004-03-01 | 2005-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for integrated manufacturing of split gate flash memory with high voltage MOSFETS |
| US20160141176A1 (en) * | 2014-07-18 | 2016-05-19 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
| CN115084242A (en) * | 2022-05-23 | 2022-09-20 | 安徽瑞迪微电子有限公司 | Method for manufacturing Trench Gate MOS type power device |
-
2022
- 2022-10-10 CN CN202211233767.XA patent/CN115621116A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11251244A (en) * | 1992-04-30 | 1999-09-17 | Toshiba Corp | Semiconductor device and manufacture of the same |
| US5597754A (en) * | 1995-05-25 | 1997-01-28 | Industrial Technology Research Institute | Increased surface area for DRAM, storage node capacitors, using a novel polysilicon deposition and anneal process |
| KR20040096340A (en) * | 2003-05-09 | 2004-11-16 | 주식회사 하이닉스반도체 | Method for forming contact plug of semicondutor device |
| JP2005191480A (en) * | 2003-12-26 | 2005-07-14 | Fuji Photo Film Co Ltd | Manufacturing method of solid-state imaging device |
| US20050191800A1 (en) * | 2004-03-01 | 2005-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for integrated manufacturing of split gate flash memory with high voltage MOSFETS |
| US20160141176A1 (en) * | 2014-07-18 | 2016-05-19 | Asm Ip Holding B.V. | Process for forming silicon-filled openings with a reduced occurrence of voids |
| CN115084242A (en) * | 2022-05-23 | 2022-09-20 | 安徽瑞迪微电子有限公司 | Method for manufacturing Trench Gate MOS type power device |
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