KR20040059892A - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor of a semiconductor device is provided to be capable of obtaining a stable and reliable metal lower electrode. CONSTITUTION: A capacitor insulating layer(34) is formed on a substrate(30). A capacitor hole is formed by selectively etching the capacitor insulating layer. A metal film is formed on the resultant structure. A lower electrode(37) is formed by polishing the metal film using acid slurry, wherein the pH is 1-5. Then, a dielectric film and an upper electrode are sequentially formed on the lower electrode.

Description

Method for fabricating capacitor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing techniques, and more particularly, to a method of manufacturing capacitors in semiconductor devices.

As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.

Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is defined as in Equation 1 below.

C = εAs / d

Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.

Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.

Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of the electrode in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.

In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.

Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO-nitride (NO) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta ₂ O ₅ , Al ₂ O ₃ , HfO ₂ , SrTiO ₃ , (Ba High dielectric material such as Sr) TiO ₃ (hereinafter referred to as BST), or (Pb, Zr) TiO ₃ (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O ₃ (hereinafter referred to as PLZT) Ferroelectric materials, such as SrBi2Ta2O ₉ (hereinafter referred to as SBT) and Bi _4-x La _x Ti ₃ O ₁₂ (hereinafter referred to as BLT), are used as the dielectric thin film materials.

In manufacturing a high dielectric capacitor or a ferroelectric capacitor using such a high dielectric material or ferroelectric material as a dielectric thin film material, proper control of dielectric surrounding materials and processes must be accompanied to realize dielectric properties specific to the high dielectric material or ferroelectric material. do.

In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO ₂ , IrO _2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.

1A to 1C are process cross-sectional views showing a capacitor manufacturing method of a semiconductor device according to the prior art, and in particular, a three-dimensional concave type capacitor manufacturing method.

As shown in FIG. 1A, after the first interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, the first interlayer insulating film 12 penetrates the semiconductor substrate 10. A contact hole connected to the active region 11 is formed. Subsequently, the contact hole is filled with a conductive silicon film to form a storage node contact plug 13.

Subsequently, the capacitor forming insulating film 14 is formed to have a height at which the capacitor is to be formed, and then the capacitor forming insulating film 14 is selectively removed so that the contact plug 13 is exposed to form the capacitor forming hole 15.

Subsequently, as shown in FIG. 1B, the metal layer 16 for lower electrodes is formed along the pattern of the capacitor forming hole 15. The metal film is Pt, Ir, Ru, RuO ₂ , IrO ₂ , W, WN, TiN or the like.

Subsequently, the protective film 17 for protecting the lower electrode is formed in the process of separating the lower electrode conductive film 16 between the capacitor forming hole 15 and the hole. The protective film 17 is formed of a photosensitive film.

Subsequently, as shown in FIG. 1C, the lower electrode conductive layer 16 is separated from the capacitor forming hole 15 and the hole by using an etch-back process to form the lower electrode 17 ′. do.

Subsequently, a dielectric thin film and an upper electrode are sequentially stacked on the lower electrode 37 'to complete a capacitor.

As semiconductor devices are highly integrated, the area for forming capacitors is gradually decreasing. In order to secure a constant capacitance in a limited area, the lower electrode is formed in three dimensions on the one hand, and on the other hand, a high-k dielectric such as Ta ₂ O ₅ , Al ₂ O ₃ , HfO _2, etc. I use it.

However, since the upper and lower electrodes of the capacitor are used as metals for the dielectric properties of the high dielectric material, various problems occur in the process.

When the etch back process is performed to separate the metal film for the lower electrode, a by-product is formed in the capacitor forming hole due to the reaction of the metal film with the chemical used in the etch process. The by-product (B) generated here is very likely to generate a leakage current, thereby reducing the reliability in the semiconductor manufacturing process.

The present invention has been proposed to solve the above problems, and to provide a metal lower electrode having excellent electrical characteristics, an object of the present invention is to provide a stable and reliable capacitor manufacturing method.

1A to 1C are cross-sectional views showing a method of manufacturing a capacitor of a semiconductor device according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

30: substrate

31: active area

32: interlayer insulating film

33: Contact Plug

34: insulating film for capacitor formation

35: stop film for chemical mechanical polishing process

36: capacitor formation hole

37: metal film for the lower electrode

38: protective film for chemical mechanical polishing process

37 ': lower electrode

In order to achieve the above object, the present invention comprises the steps of forming an insulating film for forming a capacitor to a height to form a capacitor on the substrate; Selectively removing the capacitor forming insulating layer in the region where the capacitor is to be formed to form a capacitor forming hole; Forming a lower electrode metal film along the capacitor forming hole pattern; forming a lower electrode by polishing the lower electrode metal film to expose the capacitor forming insulating film by a chemical mechanical polishing process using an acid slurry; Forming a dielectric thin film on the lower electrode; And it provides a method of manufacturing a capacitor of a semiconductor device comprising the step of forming an upper electrode on the dielectric thin film.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2E are process cross-sectional views showing a method of manufacturing a capacitor of a semiconductor device according to a preferred embodiment of the present invention, and in particular, a method of manufacturing a concave type three-dimensional capacitor.

First, as shown in FIG. 2A, the first interlayer insulating film 32 is formed on the semiconductor substrate 30 on which the active region 31 is formed, and then penetrates through the first interlayer insulating film 32 to form the semiconductor substrate 30. A contact hole is formed to be connected to the active region 31 of the. Subsequently, the contact hole is buried using a conductive silicon film, and then planarized using a process such as chemical mechanical polishing to form the storage node contact plug 33.

In addition, the interlayer insulating film 32 may be formed of undoped-silicate glass (USG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), high density plasma (HDP) oxide, spin on glass (SOG) film, It can be formed using a TEOS (Tetra Ethyl Ortho Silicate) film or an oxide film using HDP (high densigy plasma), or a thermal oxide film (Thermal Oxide). Can be.

Subsequently, an insulating film 34 for forming a capacitor is formed on the substrate at a height at which the capacitor is to be formed. The capacitor forming insulating film 34 may include an undoped-silicate glass (USG), a phospho-silicate glass (PSG), a boro-phospho-silicate glass (BPSG), a high density plasma (HDP) oxide film, and a spin on glass (SOG) film. , TEOS (Tetra Ethyl Ortho Silicate) film or HDP (high densigy plasma) using oxide film, etc. or thermal oxide (Thermal Oxide) film formed by oxidizing the silicon substrate at a high temperature between 600 ~ 1,100 ℃ in the furnace can do.

Subsequently, a stop film 35 for chemical mechanical polishing process is formed on the capacitor forming insulating film 35 with a silicon nitride film. The stop film 35 uses a nitride film series such as Si ₃ N ₄ , SiOxNy, or the like.

Subsequently, as shown in FIG. 2B, the stop film 35 and the capacitor forming insulating film 34 are selectively removed so that the contact plug 33 is exposed to form the capacitor forming hole 36.

Subsequently, as shown in FIG. 2C, the metal film 37 for lower electrodes is formed along the pattern of the capacitor forming hole 36. The metal film is Pt, Ir, Ru, RuO ₂ , IrO ₂ , W, WN, TiN or the like.

Subsequently, as shown in FIG. 2D, a protective film 38 for chemical mechanical polishing process is formed on the lower electrode metal film 37 so that the capacitor forming hole 36 is buried.

The protective film 38 here is for preventing the slurry residue from entering the inside of the capacitor forming hole 36 during the chemical mechanical polishing process in a subsequent process. The protective film 38 uses an oxide film having good spin on glass (SOG), a photosensitive film, or a gap fill characteristic.

Subsequently, as shown in FIG. 2E, a chemical mechanical polishing process is performed such that the lower electrode conductive film 37 remains inside the capacitor forming hole 36 to form the lower electrode 37 ′.

SiO ₂ or CeO ₂ is used as the slurry, and the slurry is subjected to the film-forming process using an acidic solution of 1 to 5 as a base solution. Alternatively, by adding an oxidizing agent such as H ₂ O ₂ , Fe (NO ₃ ) _3, and H ₅ IO ₆ , an acid slurry having a pH of 0 to 5 may be used for the chemical mechanical polishing process.

The chemical mechanical polishing process may be performed by separating the chemical mechanical polishing process into two systems for the purpose of removing roughness.

A cleaning process is then performed to remove residues after the chemical mechanical polishing process. A cleaning process using NH ₄ OH + HF may be added to ensure residue removal.

Subsequently, the protective film 38 for chemical mechanical polishing is removed, and the dielectric thin film and the upper electrode are sequentially stacked on the lower electrode 37 '. The dielectric thin film uses high dielectric materials such as Ta ₂ O ₅ , Al ₂ O ₃ , HfO ₂ , SrTiO ₃ , BST, and ferroelectric materials such as PZT, PLZT, SBT, and BLT.

As described above, when the lower electrode is formed through the process, the possibility of leakage current due to the profile nonuniformity generated during the conventional etch back process and the reaction by-product between the etching chemical and the metal film for the lower electrode can be reduced. .

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In addition, in the above-described embodiment, the concave type capacitor has been described, but it is also applicable to the cylinder type capacitor.

According to the present invention, it is possible to stably form the lower electrode, thereby producing a reliable high dielectric constant capacitor.

Claims (5)

Forming an insulating film for forming a capacitor by a height at which the capacitor is formed on the substrate; Selectively removing the capacitor forming insulating layer in the region where the capacitor is to be formed to form a capacitor forming hole; Forming a metal layer for the lower electrode along the hole pattern for forming the capacitor; Forming a lower electrode by polishing the lower electrode metal film to expose the capacitor forming insulating film by a chemical mechanical polishing process using an acid slurry; Forming a dielectric thin film on the lower electrode; And Forming an upper electrode on the dielectric thin film Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, PH of the acid slurry is 1 ~ 5, characterized in that the capacitor manufacturing method of the semiconductor device. The method of claim 2, The acid slurry is a capacitor manufacturing method of a semiconductor device, characterized in that the acid solution to which oxidizing agents such as H2O3, Fe (NO3) 3, and H5IO6 are added. The method of claim 3, wherein And filling the capacitor-type hole with an SOG film or a photosensitive film as a protective film for chemical mechanical polishing. The method of claim 4, wherein And forming a nitride film on the capacitor forming insulating film using a chemical mechanical polishing stop film.