KR20040057551A - Method for fabrication of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of preventing attack of conductive patterns and minimizing the reduction of the area of a contact opening part. CONSTITUTION: A plurality of conductive patterns(32) with a hard mask(33) and a sacrificial hard mask are formed on a substrate(30). An insulating layer(36) is formed on the resultant structure and planarized by removing the insulating layer and the sacrificial hard mask to expose the hard mask. A contact hole(38) is formed by selectively etching the insulating layer using a cell contact open mask(37). A plug is then formed in the contact hole.

Description

Semiconductor device manufacturing method {METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, it is possible to reduce the step difference between a high density pattern region, for example, a cell region and a low density pattern region, for example, a peripheral circuit region. It relates to a method of manufacturing a semiconductor device that can be maximized.

As the degree of integration of semiconductor devices increases, a vertical arrangement of unit devices is used, and a plug forming technology has been adopted for electrical connection between these unit devices. Currently, such a contact plug forming technology has become popular in semiconductor device processing technology. .

In forming the contact plug, a planarization process such as chemical mechanical polishing (CMP) or full surface etching for isolation between the plugs is also required.

On the other hand, in the high density pattern region and the low density pattern region, for example, the cell region and the peripheral circuit region, a step is inevitably generated between the insulating layers. In order to reduce the step, a sufficient flow process is required, and the flow process is a high temperature thermal process. Accompany you.

However, the high temperature thermal process is an example of deterioration of characteristics of a lower device such as a gate electrode and a source / drain junction, and is difficult to apply due to an increase in leakage current due to a decrease in threshold voltage, and excellent fluidity and excellent film flatness and gap-fill characteristics. Efforts to use an insulating film (Flowabledielectric) are in progress, but there are problems of its own, such as micropores occurring in the lower part of the gap-fill, which is difficult to apply to the process.

1A to 1C are cross-sectional views illustrating a process of forming a contact plug of a semiconductor device according to the prior art.

FIG. 1A illustrates a state in which a plurality of gate electrode patterns are formed in a cell region and a peripheral circuit region.

A field oxide film (not shown) is formed on the substrate 10 formed of a cell region and a peripheral circuit region and formed with various elements for forming a semiconductor device through a LOCOS (LOCal Oxidation Of Silicon) or STI (Shallow Trench Isolation) process. Distinguish between active and device isolation areas.

A plurality of conductive film patterns adjacent to the active region, for example, a gate electrode pattern, are formed to deposit an oxide-based gate insulating film 11, and a metal film such as tungsten, a metal nitride film such as tungsten nitride film, a tungsten silicide, and the like on top thereof. The metal silicide or polysilicon alone or in combination to deposit the gate electrode 12 material, and then a nitride film-based hard mask insulating film is deposited.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed, and then the gate insulating film 11 / gate is selectively etched by using the photoresist pattern as an etch mask to selectively etch the insulating film for the hard mask, the gate electrode material and the gate oxide film. A gate electrode pattern forming a stack structure of the electrode 12 / hard mask 13 is formed.

Subsequently, a nitride insulating film-based spacer insulating film 14 is thinly deposited along the entire profile where the gate electrode pattern is formed. The reason why the nitride-based material is used as the insulating film for the spacer is that the etching selectivity with the oxide film during the self alignment contact (hereinafter referred to as SAC) etching process for the subsequent plug formation can be obtained, and the gate electrode This is to prevent the loss of etching of the pattern.

Subsequently, the insulating film 15 is formed to cover the gate electrode pattern and the upper part of the substrate sufficiently for the purpose of interlayer insulation. As the insulating film 15, a BPSG (BoroPhosphoSilicate Glass) film is usually used. On the other hand, as described above, the peripheral circuit region has a lower vertical height than the cell region due to the pattern density difference between the cell region and the peripheral circuit region, resulting in a step such as 'X' shown between the two regions.

Next, a contact plug or contact pad is formed for the electrical connection between the substrate 10 between the gate electrode patterns, specifically, a source / drain junction (not shown) in the substrate 10 and a device to be formed thereon by a subsequent process. A contact hole (not shown) for forming a cell contact open mask (not shown), and then selectively etching the insulating layer with the cell contact open mask as an etch mask to open the surface of the substrate 10 between the gate electrode patterns. After forming a plug, a plug 16 is formed by depositing a conductive material such as polysilicon, which is contacted to the surface of the open substrate 10 and doped with impurities to sufficiently fill the contact hole. Illustrated.

Next, the surface of the plug 16 and the insulating film 15 are planarized by performing an entire surface etching or CMP process for isolation between the plugs 16.

At this time, the planarization with the hard mask 13 and a portion of the insulating film 15 higher than the planarization may be performed.

Meanwhile, since the BPSG film is mainly used as the insulating film 15, the BPSG film has a higher removal rate in the CMP process step than the polysilicon, which is a plug material, and thus, it is difficult to control the insulating film 15. When the planarization process such as CMP is performed until the surface of the hard mask 13 is exposed for the isolation between the plugs 16 in accordance with the stepped area X of the area, the area of the peripheral area as shown in 'A' is shown. An attack occurs in the gate electrode pattern. In FIG. 1C, a cross section in which the hard mask 13 is lost is illustrated.

As such, it is necessary to develop a process technology in consideration of a faster removal rate than polysilicon of a BPSG-based insulating film and prevention of attack such as a gate electrode pattern due to a step between a cell region and a peripheral region.

On the other hand, in order to prevent the loss of the hard mask in the peripheral circuit region due to the step between the cell region and the peripheral circuit region, for example, a method of forming an open portion only in the cell region using a cell open mask has been made.

2 is a cross-sectional SEM photograph showing the SAC etching profile and contact openings for forming a contact.

Referring to (a) of FIG. 2, as the degree of integration increases in the SAC process in the cell region, the thickness of the interlayer insulating layer serving as an etch target is gradually increased. As a result, the angle of the etch cross section during the SAC etching is less than 85 °. (20).

Therefore, as shown in (b) of FIG. 2, the predetermined contact width at the upper end of the contact opening is wide as shown by reference numeral '21', but it can be seen that the upper part of the contact opening becomes narrow as shown by reference numeral '22'. .

The reduction of the contact area at the bottom of the contact opening serves to increase the contact resistance.

The present invention has been proposed to solve the above problems of the prior art, and prevents attack of substructures such as conductive film patterns due to the step difference between the high density pattern region and the low density pattern region and the etching rate of the insulating layer, and reduces the area of the contact opening. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of minimizing the number.

1A to 1C are cross-sectional views illustrating a process of forming a contact plug of a semiconductor device according to the prior art.

FIG. 2 is a cross-sectional SEM photograph showing the SAC etch profile and contact openings for contact formation. FIG.

3A to 3D are cross-sectional views illustrating a process of forming a contact plug of a semiconductor device according to an embodiment of the present invention.

4A and 4B are cross-sectional views illustrating a process of forming a contact plug of a semiconductor device according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

30 substrate 31 gate insulating film

32: gate electrode 33: hard mask

35 etch stop film 36 insulating film

37: Cell contact open mask 38: Contact hole

In order to achieve the above object, the present invention, forming a plurality of conductive film pattern having a structure in which a sacrificial hard mask and a hard mask stacked on the substrate; Forming an insulating film on the entire structure of the conductive film pattern; Planarizing the hard mask and the insulating layer by removing the insulating layer and the sacrificial hard mask with an etching target to which the hard mask is exposed; Forming a contact hole by selectively etching the insulating film between the conductive film patterns using a cell open mask; Forming a conductive plug conductive film on the entire structure of the contact hole; And forming a plurality of plugs separated from each other by performing a planarization process of removing the contact plug conductive film as a target to which the hard mask is exposed.

The present invention applies a double hard mask structure using a conventional nitride film-based hard mask and a metal-based sacrificial hard mask used on conductive film patterns such as gate electrodes. Subsequently, when depositing an interlayer insulating film and performing wide-area planarization identification between the cell region and the peripheral circuit region, even if the etching stops at the upper end of the hard mask of the cell region, the sacrificial hard mask acts as a stopper to effect the damage without damaging the gate electrode. Since the planarization is possible and the thickness of the interlayer insulating layer to be etched is greatly reduced as compared with the related art, it is possible to maximize the critical dimension (hereinafter referred to as CD) of the contact opening during SAC etching for forming the plug.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3D are cross-sectional views illustrating a process of forming a contact plug of a semiconductor device according to an embodiment of the present invention.

3A illustrates a state in which a plurality of conductive film patterns, for example, gate electrode patterns, are formed in a cell region and a peripheral circuit region. Meanwhile, in the exemplary embodiment of the present invention, the gate electrode pattern is taken as an example. However, the gate electrode pattern may be applied to a process of forming a capacitor contact plug formed by being aligned with the bit line.

A field oxide film (not shown) is formed on a substrate 30 having a plurality of elements for forming a semiconductor device and divided into a cell region and a peripheral circuit region through a LOCOS or STI process to distinguish an active region and a device isolation region.

A plurality of conductive film patterns adjacent to the active region, for example, a gate electrode pattern, are formed to deposit a gate insulating film 31 of an oxide film array, and a metal film such as tungsten, a metal nitride film such as tungsten nitride film, a tungsten silicide, and the like. The metal silicide or polysilicon alone or in combination to deposit the gate electrode 32 material, and then to deposit a nitride film-based hard mask insulating film.

Subsequently, a metal film for sacrificial hard mask is deposited to prevent excessive etching occurring in the low density pattern region due to the difference in etching characteristics in the cell region and the peripheral circuit region due to the difference in pattern density due to the global step.

Subsequently, a photoresist pattern (not shown) for forming a gate electrode pattern is formed, and then, by selectively etching the sacrificial hard mask metal film, the hard mask insulating film, the gate electrode material, and the gate insulating film using the gate electrode pattern as an etching mask. A gate electrode pattern forming a stack structure of the gate insulating film 31 / gate electrode 32 / hard mask 33 / sacrificial hard mask 34 is formed. Here, although the thickness of the hard mask 33 is represented by the same thickness in the cell region and the peripheral circuit region, in the actual process, since the SAC process is performed only in the cell region, it is generally lowered to about 500 μs in the peripheral circuit region.

The insulating film for a hard mask uses a nitride film series such as a silicon nitride film or a silicon oxynitride film, and the metal film for a sacrificial hard mask preferably uses tungsten, tungsten silicide, aluminum (Al), chromium (Cr), or molybdenum (Mo). .

Subsequently, the nitride stop layer 35 is deposited thinly along the entire profile of the gate electrode pattern. The reason for using the nitride-based material as the etch stop layer 35 is to obtain an etch selectivity with the oxide layer during the SAC etching process for the subsequent plug formation, and to prevent the etch loss of the gate electrode pattern. .

Subsequently, an oxide-based insulating film 36 such as a BPSG film is formed to sufficiently cover the gate electrode pattern and the upper portion of the substrate 30, and for interlayer insulation. On the other hand, as described above, the peripheral circuit region has a lower vertical height than the cell region due to the pattern density difference between the cell region and the peripheral circuit region, resulting in a step such as 'X' shown between the two regions.

Here, the cell region and the peripheral circuit region are one example in which a step occurs. However, in practice, the cell area and the peripheral circuit area may be regarded as a step occurring in a pattern area integrated at a high density and a pattern area integrated at a relatively low density. In addition to the film, for example, a PSG (Phospho Silicate Glass) film or a BSG (Boro Silicate Glass) film, etc. may be exemplified, and these are usually accompanied by a process of flowing by heat treatment at a predetermined temperature after deposition.

Next, the insulating layer 36, the etch stop layer 35, and the sacrificial hard mask 34 are removed by the entire surface etching or the CMP process as a target to which the hard mask 33 is exposed, thereby removing the hard mask 33 and the insulating layer 36. ) Has a flattened cross-sectional shape as shown in FIG.

In this case, in FIG. 3B, the sacrificial hard mask 34 in the cell region can be almost removed between the cell zero region and the peripheral circuit region. Let (33) be exposed. At this time, the thickness of the insulating layer 36 is lower than that of the cell region in the peripheral circuit region having a low topology, but the etching speed is high, but the etching stop occurs once in the sacrificial hard mask 33.

Since the etching rate of the sacrificial hard mask 33 is significantly lower than the etching rate of the insulating film 36, the loss of the sacrificial hard mask 34 in the peripheral circuit region until the insulating film 36 is removed in the cell region is reduced. Rarely occurs.

Accordingly, as shown in FIG. 3B, the insulating layer 36 may be substantially planarized with the hard mask 33 in the cell region and the peripheral circuit region.

Specifically, the cell contact open mask 37 is formed to form a contact plug for electrical connection between the active region in the substrate 30 and the device to be formed thereon by a subsequent process. In addition, the insulating layer 36 and the etch stop layer 35 are selectively etched using the cell contact open mast 37 as an etch mask to form a contact hole 38 for opening the surface of the substrate 30 between the gate electrode patterns. 3C shows a cross section in which the contact hole 38 is formed.

When etching the insulating film 36 and the etch stop film 35, the fluorine-based plasma used in a normal SAC process, for example, C ₂ F ₄ , C ₂ F ₆ , C ₃ F ₈ , C ₄ F ₆ , C ₅ F CxFy (x, y is 1 to 10) such as ₈ or C ₅ F _{10 is used} as a stock angle gas, and is a gas for generating polymer during SAC process, that is, CH ₂ F ₂ , C ₃ HF ₅ or CHF ₃ In addition, inert gas, such as He, Ne, Ar, or Xe, is used as a carrier gas.

Meanwhile, in the exemplary embodiment of the present invention, since the insulating film 36 is hardly present on the hard mask 33, it can be seen that the etching target is considerably reduced in comparison with the conventional SAC etching process.

Accordingly, the cross-sectional angle etched in the etching profile in which the contact hole 38 is formed may be maintained at about 90 °. As a result, the CD W1 at the bottom of the contact hole 38 and the CD W2 at the upper end of the contact hole 38 do not have much difference.

Here, the cell contact open mask may use a hole type, a bar type, a tee type, or the like.

Subsequently, a conductive material such as polysilicon or tungsten (W) is deposited or contacted to the exposed surface of the substrate 30 by using selective epitaxial growth (hereinafter referred to as SEG) and contact holes ( Make sure that 39) is fully buried.

Subsequently, the plug material is removed with an etch target to which the hard mask 33 is exposed by using front etching, CMP, or both, so that a plurality of plugs isolated from neighboring plug 39 as shown in FIG. 39).

4A and 4B are cross-sectional views illustrating a process of forming a contact plug of a semiconductor device according to another embodiment of the present invention.

In addition, the same reference numerals are used for the same components as in the above-described embodiment, and the description thereof will be omitted for the same process steps.

As shown in FIG. 3A, a series of processes having a step such as 'X' illustrated between the cell region and the peripheral circuit region are performed, and then the hard mask 33 and the insulating layer 36 are planarized as shown in FIG. 3B through a planarization process. .

Subsequently, as illustrated in FIG. 4A, a nitride film-based sacrificial insulating film 40 is deposited on the entire surface where the hard mask 33 and the insulating film 36 are planarized.

Here, the reason for using the sacrificial insulating layer is that in the embodiment of forming a cell contact mask, if misalignment occurs, the hard mask 33 may be damaged at the top during SAC etching, and thus, in the SAC etching process due to misalignment. This is to prevent the loss of the hard mask 33.

Subsequently, the cell contact open mask 37 is formed to form a contact plug for electrically connecting the substrate 30 between the gate electrode patterns, specifically, the active region in the substrate 30 and the device to be formed thereon by a subsequent process. Next, a contact for opening the surface of the substrate 30 between the gate electrode patterns by selectively etching the sacrificial insulating film 40, the insulating film 36, and the etch stop film 35 using the cell contact open mast 37 as an etch mask. The hole 38 is formed. 3C shows a cross section in which the contact hole 38 is formed.

Meanwhile, in another embodiment of the present invention, since the insulating film 36 is hardly present on the hard mask 33, it can be seen that the etching target is considerably reduced in comparison with the conventional SAC etching process.

Accordingly, the cross-sectional angle etched in the etching profile in which the contact hole 38 is formed may be maintained at about 90 °. As a result, the CD W1 at the bottom of the contact hole 38 and the CD W2 at the upper end of the contact hole 38 do not have much difference.

Subsequently, a conductive material such as polysilicon or tungsten (W) is deposited or contacted to the exposed surface of the substrate 30 by using the SEG method, and the contact holes 39 are sufficiently buried, and then the front etching, CMP Alternatively, both of the plurality of plugs 39 isolated from the neighboring plug 39 as shown in FIG. 3D by removing the plug material and the sacrificial insulating layer 40 with the etching target to which the hard mask 33 is exposed using both of them. ).

According to the present invention made as described above, in order to overcome the step between the densely integrated pattern region and the low density integrated pattern region, a low-density pattern region at the time of planarization according to the step difference between the two regions using a sacrificial hard mask of metal is used. Over-etching can be prevented. Therefore, the attack of the lower part in the pattern area integrated at low density can be prevented.

In addition, in the SAC etching process, the thickness of an insulating film (usually an interlayer insulating film), which is an etch target, can be significantly reduced, so that the cross-sectional angle profile angle of the SAC etching due to the increase of the etching target can be brought close to 90 °. As a result, the CD of the contact opening can be secured to the maximum and the contact resistance can be minimized.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can prevent the lower attack of the low density pattern region due to the step according to the pattern density when forming the contact plug, minimize the contact resistance, and ultimately improve the process margin and yield of the semiconductor device. You can expect an excellent effect.

Claims (7)

Forming a plurality of conductive film patterns having a structure in which a sacrificial hard mask and a hard mask are stacked thereon on a substrate; Forming an insulating film on the entire structure of the conductive film pattern; Planarizing the hard mask and the insulating layer by removing the insulating layer and the sacrificial hard mask with an etching target to which the hard mask is exposed; Forming a contact hole by selectively etching the insulating film between the conductive film patterns using a cell open mask; Forming a conductive plug conductive film on the entire structure of the contact hole; And Forming a plurality of plugs separated from each other by performing a planarization process of removing the contact plug conductive film to a target to which the hard mask is exposed; Semiconductor device manufacturing method comprising a. The method of claim 1, The sacrificial hard mask, A method for fabricating a semiconductor device comprising any one selected from the group consisting of tungsten, tungsten silicide, aluminum, chromium and molybdenum. The method of claim 1, The conductive plug conductive film is a semiconductor device manufacturing method characterized in that it comprises polysilicon or tungsten. The method of claim 1, The conductive film pattern is a semiconductor device manufacturing method, characterized in that the conductive line including a gate electrode or a bit line. The method of claim 1, The contact hole is a semiconductor device manufacturing method, characterized in that the pattern of any one of the bar type, T type or hole type. The method according to any one of claims 1 to 5, And after the planarizing the hard mask and the insulating layer, depositing a sacrificial sol film on the entire surface of the semiconductor device. The method of claim 6, The sacrificial insulating film is a semiconductor device manufacturing method, characterized in that the nitride film series.