KR100364806B1 - Method for fabricating of semiconductor device - Google Patents
Method for fabricating of semiconductor device Download PDFInfo
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- KR100364806B1 KR100364806B1 KR1020000084098A KR20000084098A KR100364806B1 KR 100364806 B1 KR100364806 B1 KR 100364806B1 KR 1020000084098 A KR1020000084098 A KR 1020000084098A KR 20000084098 A KR20000084098 A KR 20000084098A KR 100364806 B1 KR100364806 B1 KR 100364806B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
Abstract
본 발명은 게이트 캡층의 상부에 CMP(Chemical Mechanical Polishing) 스톱층을 형성하여 PPP(Pre Poly Plug) 구조에서 셀 플러그 형성시에 게이트 캡층의 손상을 억제할 수 있도록한 반도체 소자의 제조 방법에 관한 것으로, 셀 영역 및 주변 회로 영역상에 복수 종류의 물질층이 적층되는 게이트 전극 형성용 물질층을 형성하는 단계;상기 게이트 형성용 물질층상에 에치스토퍼 역할을 하는 희생 차단층을 형성하는 단계;상기 희생 차단층 및 게이트 전극 형성용 물질층들을 선택적으로 패터닝하여 게이트 전극들을 형성하는 단계;상기 셀 영역에 형성된 게이트 전극들의 양측면에 게이트 스페이서를 형성하는 단계;전면에 플러그 형성용 물질층을 형성하고 희생 차단층을 기준으로 평탄화하는 단계;상기 셀 영역의 평탄화된 플러그형성용 물질층을 선택적으로 패터닝함과 동시에 주변 회로 영역의 플러그 형성용 물질층을 제거하는 단계;상기 주변 회로 영역의 게이트 전극들의 양측면에 게이트 스페이서를 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method of fabricating a semiconductor device in which a chemical mechanical polishing (CMP) stop layer is formed on an upper portion of a gate cap layer to suppress damage of the gate cap layer when forming a cell plug in a PPP structure. Forming a gate electrode forming material layer in which a plurality of material layers are stacked on the cell region and the peripheral circuit region; forming a sacrificial blocking layer serving as an etch stopper on the gate forming material layer; Selectively patterning a blocking layer and a material layer for forming a gate electrode to form gate electrodes; forming gate spacers on both sides of the gate electrodes formed in the cell region; forming a plug forming material layer on a front surface and sacrificial blocking Planarizing the layer; selectively patterning the planarized plugging material layer of the cell region And at the same time removing the plug material layer for forming the peripheral circuit region; comprises forming a gate spacer on both side surfaces of the gate electrode of the peripheral circuit region.
Description
본 발명은 반도체 소자의 제조에 관한 것으로, 특히 게이트 캡층의 상부에CMP(Chemical Mechanical Polishing) 스톱층을 형성하여 PPP(Pre Poly Plug) 구조에서 셀 플러그 형성시에 게이트 캡층의 손상을 억제할 수 있도록한 반도체 소자의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the manufacture of semiconductor devices, and in particular, to form a chemical mechanical polishing (CMP) stop layer on top of the gate cap layer so as to suppress damage of the gate cap layer when forming a cell plug in a PPP structure. A method for manufacturing a semiconductor device.
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 제조 공정에 관하여 설명하면 다음과 같다.Hereinafter, a manufacturing process of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1은 종래 기술의 셀 플러그 형성을 위한 CMP 공정후의 메모리 셀의 단면 구성도이다.1 is a cross-sectional configuration diagram of a memory cell after a CMP process for forming a cell plug of the prior art.
그리고 도 2a는 메인 셀부의 텅스텐층의 노출 상태를 나타낸 사진이고, 도 2b는 주변 회로부의 텅스텐층의 노출 상태를 나타낸 사진이다.2A is a photograph showing an exposed state of the tungsten layer of the main cell portion, and FIG. 2B is a photograph showing an exposed state of the tungsten layer of the peripheral circuit portion.
종래 기술의 PPP 구조의 셀 플러그 형성 방법은 반도체 기판(1)에 소자 격리층(2)에 의해 주변 회로 영역과 셀 영역이 정의되고 셀 영역 및 주변 회로 영역상에 게이트 절연막(3)이 형성된다.In the conventional method of forming a cell plug of the PPP structure, the peripheral circuit region and the cell region are defined by the device isolation layer 2 on the semiconductor substrate 1, and the gate insulating film 3 is formed on the cell region and the peripheral circuit region. .
그리고 게이트 절연막(3)상에 게이트 폴리층(4),게이트 금속층(5), 캡 나이트라이드층(6), 캡 산화막층(7)이 이 차례대로 적층되는 구조의 게이트 전극이 형성된다.On the gate insulating film 3, a gate electrode having a structure in which the gate poly layer 4, the gate metal layer 5, the cap nitride layer 6, and the cap oxide film layer 7 are laminated in this order is formed.
그리고 셀 영역의 게이트 전극의 양측에는 LDD(Lightly Doped Drain) 영역을 형성하기 위한 게이트 스페이서가 형성되는데, 게이트 스페이서는 나이트라이드로 구성된 제 1 측벽(8), 산화막으로 구성된 제 2 측벽(9)으로 구성된다.Gate spacers for forming a lightly doped drain (LDD) region are formed at both sides of the gate electrode of the cell region, and the gate spacers include a first sidewall 8 made of nitride and a second sidewall 9 made of an oxide film. It is composed.
이어, 상기 게이트 전극의 일측에는 셀 플러그층(10)이 형성되는데 셀 플러그층은 셀프 얼라인 공정에 의해 콘택홀이 형성되고 셀 플러그 형성용 물질층 예를들면, 도우프드 폴리 실리콘층이 매립 형성된다.Subsequently, a cell plug layer 10 is formed on one side of the gate electrode, wherein the cell plug layer is formed with a contact hole by a self-aligning process, and a material layer for forming a cell plug, for example, a doped polysilicon layer is buried. do.
이 상태에서 캡 산화막층(7)이 노출되도록 CMP 공정으로 평탄화를 하여 형성한다.In this state, the cap oxide film layer 7 is formed to be flattened by a CMP process.
물론, 이와 같은 셀 플러그(10) 형성 공정시에 주변 회로 영역은 마스킹되어 콘택홀이 형성되지 않는다.Of course, in the cell plug 10 forming process, the peripheral circuit region is masked so that a contact hole is not formed.
셀 플러그 형성시에 평탄화 공정으로 사용되는 CMP는 위치별 불균일에 의해 게이트 캡 산화막의 잔류량이 불균일하게 남을 수 있다.In the CMP used as the planarization process in forming the cell plug, the residual amount of the gate cap oxide film may remain unevenly due to the positional unevenness.
또한, 후속되는 셀 플러그 및 LDD 식각 공정에서 게이트 캡 산화막의 손실이 있을 수 있다.In addition, there may be a loss of the gate cap oxide in subsequent cell plug and LDD etching processes.
이는 도 2a의 (가) 부분에서와 같이 셀 영역 트랜지스터의 게이트 금속층, 주로 텅스텐층을 노출시키게 된다.This exposes the gate metal layer of the cell region transistor, mainly the tungsten layer, as in part (a) of FIG. 2A.
마찬가지로 도 2b에서와 같이, (나)부분의 게이트 금속층, 텅스텐층이나 티타늄 나이트라이드층을 노출시키게 된다.Likewise, as shown in FIG. 2B, the gate metal layer, the tungsten layer, and the titanium nitride layer of part (b) are exposed.
그러나 이와 같은 종래 기술의 PPP 구조의 셀 플러그 형성 공정에 있어서는 다음과 같은 문제가 있다.However, such a cell plug formation process of the prior art PPP structure has the following problems.
셀 플러그 형성시에 평탄화 공정으로 사용되는 CMP는 위치별 불균일에 의해 게이트 캡 산화막의 잔류량이 불균일하게 남고, 후속되는 셀 플러그 및 LDD 식각 공정에서 게이트 캡 산화막의 손실이 있을 수 있다.In the CMP used as the planarization process in forming the cell plug, the residual amount of the gate cap oxide film may remain uneven due to the positional unevenness, and there may be a loss of the gate cap oxide film in the subsequent cell plug and LDD etching process.
이는 셀부 및 주변 회로 영역의 게이트 텅스텐층을 노출시켜 소자 불량 및후속되는 ILD(Inter Layer Dielectric)층의 이상 산화를 일으킨다.This exposes the gate tungsten layer in the cell portion and the peripheral circuit area, resulting in device failure and abnormal oxidation of the subsequent interlayer dielectric (ILD) layer.
본 발명은 이와 같은 종래 기술의 문제를 해결하기 위한 것으로, 게이트 캡층의 상부에 CMP(Chemical Mechanical Polishing) 스톱층을 형성하여 PPP(Pre Poly Plug) 구조에서 셀 플러그 형성시에 게이트 캡층의 손상을 억제할 수 있도록한 반도체 소자의 제조 방법을 제공하는데 그 목적이 있다.The present invention is to solve such a problem of the prior art, by forming a chemical mechanical polishing (CMP) stop layer on top of the gate cap layer to suppress the damage of the gate cap layer when forming the cell plug in the PPP (Pre Poly Plug) structure It is an object of the present invention to provide a method for manufacturing a semiconductor device.
도 1은 종래 기술의 셀 플러그 형성을 위한 CMP 공정후의 메모리 셀의 단면 구성도1 is a cross-sectional configuration diagram of a memory cell after a CMP process for forming a cell plug of the prior art
도 2a는 메인 셀부의 텅스텐층의 노출 상태를 나타낸 사진Figure 2a is a photograph showing the exposed state of the tungsten layer of the main cell portion
도 2b는 주변 회로부의 텅스텐층의 노출 상태를 나타낸 사진Figure 2b is a photograph showing the exposed state of the tungsten layer of the peripheral circuit portion
도 3a내지 도 3d는 본 발명에 따른 반도체 소자의 공정 단면도3A to 3D are cross-sectional views of a semiconductor device in accordance with the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21. 반도체 기판 22. 소자 격리층21. Semiconductor substrate 22. Device isolation layer
23. 게이트 산화막 24. 게이트 폴리층23. Gate oxide 24. Gate poly layer
25. 게이트 금속층 26. 캡 나이트라이드층25. Gate metal layer 26. Cap nitride layer
27. 캡 산화막층 28. 게이트 버퍼 나이트라이드층27. Cap oxide layer 28. Gate buffer nitride layer
29. 29b. 제 1 측벽 30.30a. 제 2 측벽29. 29b. First sidewall 30.30a. Second sidewall
31. 셀 플러그층31. Cell plug layer
이와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 셀 영역 및 주변 회로 영역상에 복수 종류의 물질층이 적층되는 게이트 전극 형성용 물질층을 형성하는 단계;상기 게이트 형성용 물질층상에 에치스토퍼 역할을 하는 희생 차단층을 형성하는 단계;상기 희생 차단층 및 게이트 전극 형성용 물질층들을 선택적으로 패터닝하여 게이트 전극들을 형성하는 단계;상기 셀 영역에 형성된 게이트 전극들의 양측면에 게이트 스페이서를 형성하는 단계;전면에 플러그 형성용 물질층을 형성하고 희생 차단층을 기준으로 평탄화하는 단계;상기 셀 영역의 평탄화된 플러그형성용 물질층을 선택적으로 패터닝함과 동시에 주변 회로 영역의 플러그 형성용 물질층을 제거하는 단계;상기 주변 회로 영역의 게이트 전극들의 양측면에 게이트 스페이서를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a material layer for forming a gate electrode in which a plurality of types of material layers are stacked on a cell region and a peripheral circuit region; Forming a sacrificial blocking layer acting as an etch stopper; selectively patterning the sacrificial blocking layer and a material layer for forming a gate electrode to form gate electrodes; forming gate spacers on both sides of gate electrodes formed in the cell region Forming a plug forming material layer on the front surface and planarizing the sacrificial blocking layer; selectively patterning the planarized plug forming material layer in the cell region and simultaneously forming a plug forming material in the peripheral circuit region Removing a layer; gates on both sides of gate electrodes of the peripheral circuit region; It characterized in that comprises a step of forming a close.
이하, 첨부된 도면을 참고하여 본 발명에 따른 PPP 구조의 셀 플러그 형성을 위한 반도체 소자의 제조 방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device for forming a cell plug having a PPP structure according to the present invention will be described in detail with reference to the accompanying drawings.
도 3a내지 도 3d는 본 발명에 따른 반도체 소자의 공정 단면도이다.3A to 3D are cross-sectional views of a semiconductor device according to the present invention.
본 발명은 PPP 구조의 셀 플러그를 형성하는 공정전에 게이트 최상부 캡층상에 나이트라이드층을 사용하여 CMP(Chemical Mechanical Polishing) 스톱층을 형성하여 게이트 캡을 확보하고 손실을 막아 메인 셀 및 주변 회로 영역의 트랜지스터의 게이트 금속층이 노출되는 것을 억제하기 위한 것이다.The present invention forms a chemical mechanical polishing (CMP) stop layer using a nitride layer on the gate top cap layer prior to forming a cell plug having a PPP structure, thereby securing a gate cap and preventing loss of the main cell and peripheral circuit region. This is to suppress exposure of the gate metal layer of the transistor.
본 발명에 따른 PPP 구조의 셀 플러그 형성 방법은 먼저 도 3a에서와 같이, 반도체 기판(21)에 소자 격리층(22)에 의해 주변 회로 영역과 셀 영역이 정의되고 셀 영역 및 주변 회로 영역상에 게이트 절연막(23)이 형성된다.In the method of forming a cell plug of the PPP structure according to the present invention, first, as shown in FIG. 3A, the peripheral circuit region and the cell region are defined by the device isolation layer 22 on the semiconductor substrate 21, and the cell and peripheral circuit regions are defined. The gate insulating film 23 is formed.
그리고 게이트 절연막(23)상에 게이트 폴리층(24),게이트 금속층(25), 캡 나이트라이드층(26), 캡 산화막층(27), CMP 공정시의 차단층 역할을 하는 희생 차단층으로 사용되는 게이트 버퍼층(28)이 차례대로 적층되는 구조의 게이트 전극이 형성된다.The gate poly layer 24, the gate metal layer 25, the cap nitride layer 26, the cap oxide layer 27, and the sacrificial blocking layer serving as a blocking layer in the CMP process are used on the gate insulating layer 23. A gate electrode having a structure in which the gate buffer layers 28 are stacked in this order is formed.
여기서, 게이트 버퍼층(28)은 캡 산화막층(27)과 식각 선택비가 높은 물질을 사용하여 형성한다.The gate buffer layer 28 is formed using a material having a high etching selectivity with the cap oxide layer 27.
예를들면, 나이트라이드 또는 그를 포함하는 절연 물질중의 어느 하나를 사용할 수 있다.For example, either nitride or an insulating material comprising the same can be used.
그리고 셀 영역의 게이트 전극의 양측에는 LDD(Lightly Doped Drain) 영역을 형성하기 위한 게이트 스페이서가 형성되는데, 게이트 스페이서는 나이트라이드로 구성된 제 1 측벽(29), 산화막으로 구성된 제 2 측벽(30)으로 구성된다.Gate spacers for forming a lightly doped drain (LDD) region are formed at both sides of the gate electrode of the cell region. The gate spacer includes a first sidewall 29 made of nitride and a second sidewall 30 made of an oxide film. It is composed.
이와 같은 셀 영역의 게이트 스페이서 형성 공정시에 주변 회로 영역은 마스킹되어 셀 영역의 측벽 형성 공정의 영향을 배제한다.In the gate spacer forming process of the cell region, the peripheral circuit region is masked to exclude the influence of the sidewall forming process of the cell region.
이어, 도 3b에서와 같이, 상기 게이트 전극의 일측에는 셀 플러그층(31)이 형성되는데 셀 플러그층(31)은 셀프 얼라인 공정에 의해 콘택홀이 형성되고 셀 플러그 형성용 물질층 예를들면, 도우프드 폴리 실리콘층이 매립 형성된다.Subsequently, as shown in FIG. 3B, a cell plug layer 31 is formed on one side of the gate electrode. The cell plug layer 31 has a contact hole formed by a self-aligning process, and for example, a material layer for forming a cell plug. The doped polysilicon layer is buried.
이어, CMP 공정으로 평탄화 공정을 진행하는데, 상기 게이트 버퍼층(28)이 CMP 공정의 에치 스토퍼 역할을 하여 캡 산화막층(27)의 손상을 억제한다.Subsequently, the planarization process is performed in the CMP process, in which the gate buffer layer 28 serves as an etch stopper of the CMP process, thereby suppressing damage to the cap oxide layer 27.
그리고 포토/에치 공정으로 플러그간의 분리 공정을 진행하는데, 이때 주변 회로 영역의 도우프드 폴리 실리콘층은 제거된다.The separation process between the plugs is performed by a photo / etch process, wherein the doped polysilicon layer in the peripheral circuit region is removed.
여기서, 주변 회로 영역 나이트라이드층(29a)은 일부 손상될 수 있으나, 게이트 버퍼층(28)이 CMP 공정의 에치 스토퍼 역할을 하여 주변 회로 영역 캡 산화막층(27)의 손상을 억제한다.Here, the peripheral circuit region nitride layer 29a may be partially damaged, but the gate buffer layer 28 serves as an etch stopper of the CMP process, thereby suppressing damage of the peripheral circuit region cap oxide layer 27.
그리고 도 3c에서와 같이, 주변 회로 영역에 LDD 스페이서를 형성하기 위한 산화막을 증착하고 에치백한후 노출된 주변 회로 나이트라이드층(29a)을 제거하여 주변 회로 영역 게이트 전극의 제 1,2 측벽(29b)(30a)을 형성한다.As shown in FIG. 3C, after the oxide film for forming the LDD spacer is deposited and etched back in the peripheral circuit region, the exposed peripheral circuit nitride layer 29a is removed to remove the first and second sidewalls 29b of the peripheral circuit region gate electrode. ) 30a is formed.
이와 같은 셀 플러그 형성시에 게이트 버퍼층이 CMP 공정에 의한 평탄화 공정시에 에치 스토퍼 역할을 하여 게이트 캡 산화막의 손상을 억제한다.In the cell plug formation, the gate buffer layer acts as an etch stopper during the planarization process by the CMP process, thereby suppressing damage to the gate cap oxide film.
이와 같은 본 발명에 따른 반도체 소자의 제조 방법은 다음과 같은 효과가 있다.Such a method of manufacturing a semiconductor device according to the present invention has the following effects.
셀 플러그 형성 공정을 진행하기 전에 게이트 캡층의 상부에 CMP 에치 스토퍼층을 형성하여 게이트 캡 산화막의 잔류량이 불균일하게 남는 문제를 해결한다.The CMP etch stopper layer is formed on the gate cap layer prior to the cell plug forming process, thereby solving the problem of remaining uneven amount of the gate cap oxide film.
이는 후속되는 셀 플러그 및 LDD 식각 공정에서 게이트 캡 산화막의 손실을 충분히 억제하는 효과가 있다.This has the effect of sufficiently suppressing the loss of the gate cap oxide film in the subsequent cell plug and LDD etching process.
또한, 셀부 및 주변 회로 영역의 게이트 텅스텐층이 노출되는 것을 막아 소자의 신뢰성을 높이고, 후속되는 ILD(Inter Layer Dielectric)층의 이상 산화 막는 효과가 있다.In addition, the gate tungsten layer of the cell portion and the peripheral circuit region is prevented from being exposed to increase the reliability of the device, and there is an effect of the abnormal oxidation film of the subsequent interlayer dielectric (ILD) layer.
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| JPH07142612A (en) * | 1993-06-25 | 1995-06-02 | Mega Chips:Kk | Semiconductor device and manufacture thereof |
| US5909616A (en) * | 1995-10-20 | 1999-06-01 | Micron Technology, Inc. | Method of forming CMOS circuitry |
| KR20000005581A (en) * | 1998-06-08 | 2000-01-25 | 윤종용 | Method for forming self aligned selective silicide layer using chemical mechanical polishing in merged DRAM logic |
| KR100259075B1 (en) * | 1998-03-14 | 2000-06-15 | 김영환 | Semiconductor device and its manufacturing method |
| KR20000045452A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming dual damascene of semiconductor device |
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| JPH07142612A (en) * | 1993-06-25 | 1995-06-02 | Mega Chips:Kk | Semiconductor device and manufacture thereof |
| US5909616A (en) * | 1995-10-20 | 1999-06-01 | Micron Technology, Inc. | Method of forming CMOS circuitry |
| KR100259075B1 (en) * | 1998-03-14 | 2000-06-15 | 김영환 | Semiconductor device and its manufacturing method |
| KR20000005581A (en) * | 1998-06-08 | 2000-01-25 | 윤종용 | Method for forming self aligned selective silicide layer using chemical mechanical polishing in merged DRAM logic |
| KR20000045452A (en) * | 1998-12-30 | 2000-07-15 | 김영환 | Method for forming dual damascene of semiconductor device |
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