KR20010028057A - Bit line contact with a stable contact resistance and method of forming the same - Google Patents

Abstract

PURPOSE: A method for manufacturing a bit line contact is provided to simultaneously guarantee stable contact resistance in regions having different contact characteristics, by forming a titanium silicide layer in a bit line contact formed on a polysilicon pad while not forming the titanium silicide layer in a bit line contact formed on a gate. CONSTITUTION: A plurality of the first and second transistors have gate electrodes composed of polysilicon/tungsten silicide on a semiconductor substrate(100) including a cell array region and a peripheral circuit region. The first interlayer dielectric is formed on the substrate including the plurality of the first and second transistors. The first interlayer dielectric is etched to form the first and second openings for forming a pad exposing the substrate between the first and second transistors. Polysilicon is formed inside the first and second openings to manufacture the first and second conductive pads. A titanium silicide layer(230) is selectively formed on the first and second conductive pads. The second interlayer dielectric is formed on the resultant structure. The second interlayer dielectric is etched to form the first, second and third bit line contact holes which expose the silicide layer on the first and second conductive pad and the tungsten silicide layer of the second transistor. A barrier metal layer(240,290) and a bit line metal layer(300) are formed on the bit line contact hole and the second interlayer dielectric.

Description

BIT LINE CONTACT WITH A STABLE CONTACT RESISTANCE AND METHOD OF FORMING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor device manufacturing, and more particularly, to a reliable bit line contact structure and a method of forming the same.

Recently, with the high integration and ultra-high speed of semiconductor memory devices (DRAM), there is an urgent need to secure stable contact resistance and to reduce sheet resistance of bit lines and word lines. In order to reduce sheet resistance, a method of forming a word line (gate electrode) with a titanium silicide (TiSi _x ) film or a bit line with a metal has been actively studied.

As is well known, sub-layers in which bit line contacts are formed include an active region (impurity diffusion region) of a peripheral circuit region and a conductive pad (polysilicon pad) of a gate electrode and a cell array region. There is a need for a suitable barrier material that lowers the contact resistance of these different areas and prevents current leakage. The barrier material currently used is a titanium / titanium nitride film structure. Tungsten is used as the bit line material. In this case, titanium reacts with silicon exposed at the bottom of the subsequent heat treatment process to form titanium silicide (TiSi _x ) to improve contact resistance, and titanium nitride film penetrates into the lower film by fluorine gas generated during subsequent tungsten deposition. It is used as a prevention film to prevent destabilization of the interface. As an example disclosed herein is "METHOD FOR FABRICATING DYNAMIC RANDOM ACCESS MEMORY BY SIMULTANEOUSLY FORMING OF TUNGSTEN BIT LINE AND TUNGSTEN LANDING PLUG CONTACTS", disclosed in US Pat. No. 5,895,239.

On the other hand, in the initial introduction of the tungsten bit line, the method of forming the barrier film of the titanium / titanium nitride film structure, first depositing the titanium / titanium nitride film in a continuous process, and then performing a heat treatment process to form a titanium silicide film on the contact interface Was performed. However, this method had a significant variation in contact resistance and more than a few tens of kiloohms (KΩ) on the gate.

To improve this, titanium is separated and deposited, and a titanium silicide layer is first formed through a heat treatment process. Then, titanium dioxide (TiO ₂ ) formed at an interface with titanium not reacted with silicon is wet-etched and radio frequency etched. After removing through, a titanium nitride film is deposited. However, for the high frequency etching for removing the titanium and titanium dioxide film, the contact formed on the active region and the polysilicon pad and the contact formed on the gate show different results. That is, the contact formed on the active region and the polysilicon pad decreases the resistance as the amount of high frequency etching decreases, whereas the contact and the resistance on the gate decreases as the amount of high frequency etching decreases.

Because, as is well known, the heat treatment process of about 800 ° C. or more is necessary to reduce the leakage current of the capacitor during the process of forming the capacitor of the high dielectric film quality, and the titanium silicide of the bit line contact interface formed on the tungsten silicide electrode is a high temperature. In the heat treatment process, the contact resistance on the gate is less active because of penetration of the tungsten silicide film to form another new interface and phase transformation, resulting in unstable contact resistance. For contacts on the pad, more titanium silicide production is advantageous in terms of contact resistance.

Therefore, there is an urgent need for a method of forming bit line contacts having bit line stable contact resistances in the different regions.

The present invention has been proposed to solve the above-mentioned problems, and forms a titanium silicide film only in the polysilicon pad and prevents the titanium silicide from forming in the contact of the gate, thereby ensuring stable contact resistance at all the contacts on the polysilicon pad and the gate. To secure the purpose.

1 to 12 are cross-sectional views schematically illustrating a bit line contact forming method according to an exemplary embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100 semiconductor substrate 110 device isolation region

120, 130 polysilicon / tungsten silicide gate electrode

140: gate capping film 150: mask oxide film

160: gate spacer 170: impurity diffusion region

180: transistor 200, 250: insulating film

210: bit line contact hole 220: polysilicon pad

230: titanium silicide film 240, 290: barrier metal film

260, 270, 280: bit line contact hole

300: bit line metal film 310: bit line pattern

(Configuration)

According to one configuration of the present invention for achieving the above object, a method for forming a bit line contact, a plurality of having a gate electrode of at least polysilicon / tungsten silicide on the semiconductor substrate defined cell array region and peripheral circuit region Forming first and second transistors, respectively, forming a first interlayer insulating film on the semiconductor substrate including the plurality of first transistors and the plurality of second transistors, and forming the first interlayer insulating film. Etching to form first and second openings for pad formation exposing a semiconductor substrate between the plurality of first transistors and the plurality of second transistors, and to form polysilicon inside the first and second openings. Forming a first and a second conductive pad, respectively, and selectively forming a tee on top of the first and second conductive pad. Forming a titanium silicide layer, forming a second interlayer dielectric layer on the first interlayer dielectric layer and the titanium silicide layer, and etching the second interlayer dielectric layer to etch the silicide layer on the first and second conductive pads. And forming first, second and third bit line contact holes exposing the tungsten silicide film of the second transistor, respectively, and forming a barrier metal film on the bit line contact hole and the second interlayer insulating film. And forming a bit line metal film.

In the above method, the barrier metal film is formed of any one of TiN, TaN, TiSiN, TaSiN, WN, ZrN and NbN, and has a thickness of about 300 Angstroms to 600 Angstroms.

In the above-described method, a barrier metal film is further formed on the titanium silicide film, and the barrier metal film may be formed by any one of TiN and TiSiN.

(Action)

Referring to FIG. 12, in the case of the bit line contact formed on the polysilicon pad 210 in the cell array region and the peripheral circuit region, the titanium silicide layer 220 / titanium nitride layer 230, 290 / tungsten in order to secure stable contact resistance. The bit line contact formed on the gate of the peripheral circuit region, that is, on the tungsten silicide layer 130, unlike the contact formed on the polysilicon pad to secure a stable contact resistance and prevent an increase in contact resistance, is formed of the film 300. A titanium film nitride film 290 / tungsten film 300 in which a titanium silicide film is not formed.

Thus, by forming a titanium silicide film differentially in a region having different lower film characteristics, there is an effect that all can secure a stable contact resistance.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The film quality and regions formed in the drawings shown are exaggerated somewhat, and detailed descriptions of well-known process technologies commonly used in semiconductor manufacturing processes are omitted.

First, the wafer is prepared. The specific part in which the various elements which comprise a semiconductor device among the said wafer are formed is called a semiconductor substrate below. Only a portion of this semiconductor substrate 100 is shown in the figure. Referring to FIG. 1, an isolation process is performed on the semiconductor substrate 100 to define an active region and an inactive region 110. Then, conventional ion implantation processes such as the ion implantation process for adjusting the well structure and the transistor threshold voltage are performed on the active region. Next, a gate oxide film (not shown) is formed on the entire surface of the semiconductor substrate 100, and a gate electrode material and a gate capping film are increased.

More specifically, the tungsten silicide layer 130 for reducing the resistance of the polysilicon 120 and the gate is formed of the gate electrode material. For example, the polysilicon film 120 is formed to have a thickness of about 800 angstroms to 1,200 angstroms, and the tungsten silicide film 130 is formed to have a thickness of about 800 angstroms to 1,200 angstroms. do.

The gate capping layer is formed of a capping silicon nitride layer 140. More specifically, the silicon nitride film 140 is formed to have a thickness of about 1,800 Angstroms to 2,500 Angstroms.

A mask oxide film 150, for example a high temperature oxide film, is then formed to have a thickness of about 200 Angstroms to 500 Angstroms.

Next, a photolithography process and an etching process are performed to form a gate pattern, and a plurality of gate patterns are formed in the cell array region and the peripheral circuit region of the semiconductor substrate, respectively, as shown in FIG. 2. Most of the mask oxide film is removed during the photolithography process and the etching process, and some of the remaining film quality is removed even in the subsequent spacer forming process.

Next, a gate spacer forming process is performed to form insulating film spacers on both sidewalls of the gate pattern. Specifically, the silicon nitride film is formed as an insulating film to have a thickness of about 500 Angstroms. The sidewall spacers 160 are then etched back to remove only the remaining portions of both sides of the gate pattern and to remove all of the remaining portions.

Next, a conventional ion implantation process is performed to form an impurity diffusion region 170 on the active region, and the transistor 180 is completed.

Next, referring to FIG. 3, a first interlayer insulating film is formed on the semiconductor substrate 100 including the transistor 180. The first interlayer insulating film is typically formed of an oxide film, and has a thickness of about 5,000 Angstroms to 6,000 Angstroms. A planarization process is then performed on the first interlayer insulating film for a suitable surface topology for subsequent photolithography and etching processes, for example, using about 1,000 Angstroms using chemical mechanical polishing (CMP). The first interlayer insulating layer 200 is etched to form a first interlayer insulating layer 200 having a flat upper surface.

Next, a conductive pad process electrically connected to the impurity diffusion region 170 is performed to secure a margin of an etching process for forming a subsequent bit line contact hole. Specifically, a photolithography process and a self-aligned contact etching process are performed. That is, the photoresist film is spin-coated and patterned on the first interlayer insulating film 200. The first interlayer dielectric layer 200 is etched using the patterned photoresist layer. In this case, the etching of the first interlayer dielectric layer is performed by etching the nitride spacer spacer 160 and the capping nitride layer 140 under the condition of excellent etching selectivity, so-called self-aligned contact etching condition, to form an opening 210 for forming a contact pad. Form as shown.

Due to the self-aligned contact etching, even if misalignment occurs, the process margin can be secured because the etching to the interlayer insulating film is stopped in the nitride film.

Next, a conductive material, such as doped polysilicon, for a conductive pad is formed on the first interlayer insulating layer 200 and the opening 210. Next, a chemical mechanical polishing process or a re-etching process is performed on the formed polysilicon film to form conductive pads 220 electrically isolated from each other. More specifically, the chemical mechanical polishing is preferably performed under the condition that the etching selectivity of the polysilicon is about 2: 1 with respect to the oxide film, which is the first interlayer insulating film 200, as shown in FIG. 220 is recessed to a predetermined depth from an upper surface of the first interlayer insulating film 220.

Next, a silicide film forming process is performed to secure stable contact resistance of the bit line contact formed on the polysilicon conductive pad 220. First, a titanium film is formed on the first interlayer insulating film and the recessed conductive pads 220 to have a thickness of about 100 Angstroms to 200 Angstroms. A heat treatment process is performed in a subsequent process to form a titanium silicide layer 230 through a reaction between the exposed polysilicon of the conductive pad 220 and titanium. The silicide heat treatment process is a rapid thermal annealing process (RTP) or a furnace (furnace) is applied. Next, titanium that has not reacted with the exposed polysilicon pad, that is, the titanium film formed on the first interlayer insulating film is selectively removed (see FIG. 5).

Next, as shown in FIG. 6, a titanium nitride film 240 may be formed on the resultant shown in FIG. 5. A titanium silicon nitride film may be formed instead of the titanium nitride film. The titanium nitride layer 240 is to protect the titanium silicide layer 230 formed on the polysilicon pad 220 during an etching process for subsequent bit line contact formation. The titanium nitride film 240 is formed to have a thickness of about 300 Angstroms to 600 Angstroms. Then, the titanium nitride film 240 formed on the first interlayer insulating film 200 is removed by a chemical mechanical polishing process or a re-etching process and remains only on the titanium silicide film 220 as shown in FIG. 7.

Next, as shown in FIG. 8, a second interlayer insulating film 250 is formed on the first interlayer insulating film 200 and the titanium nitride film 240. The second interlayer insulating film 250 is formed of an oxide film, for example, a plasma enhanced-tetraorthosilicate oxide film having a thickness of about 1,000 Angstroms to 3,000 Angstroms.

The next process is a bit line contact formation process. Specifically, a photolithography process and an etching process are performed. That is, the photoresist film is spin-coated and patterned on the second interlayer insulating film 250. The second interlayer insulating layer 250 is etched using the patterned photoresist film to form a titanium nitride film 240 formed on the polysilicon pads of the peripheral circuit and the cell array region and the tungsten silicide of the gate pattern of the peripheral circuit region. First, second and third bitline contact openings 260, 270 and 280 exposing the film 130 are formed as shown in FIG. In this case, the titanium nitride layer 240 may prevent the lower titanium silicide layer 230 from being overetched in the contact etching.

Next, referring to FIG. 10, a reaction prevention barrier layer 290 is formed to prevent proline gas generated when tungsten used as a bit line material penetrate the lower layer to destabilize the interface. The reaction prevention barrier layer 290 is formed of, for example, a titanium nitride layer and has a thickness of about 300 Angstroms to 600 Angstroms. TiN, TaN, TiSiN, TaSiN, WN, ZrN, NbN, etc. may be formed instead of the titanium nitride film.

Next, referring to FIG. 11, tungsten 300 as a bit line forming material is deposited on the reaction prevention layer 290 by chemical vapor deposition (CVD) to completely fill the opening. The tungsten film 300 is formed to have a thickness of about 800 Angstroms to 3,000 Angstroms.

Next, referring to FIG. 12, a bit line 310 is formed by performing a photolithography process and an etching process in a subsequent process.

Although not shown, the bit line may be formed by the following process. That is, after the tungsten film is deposited, the tungsten film is etched again until the titanium nitride film appears to form a tungsten plug. Then, a material such as aluminum or an aluminum alloy is deposited and patterned as the bit line material on the resultant to form a bit line.

Although the present invention has been described based on the preferred embodiments, the present invention is not limited thereto, and various changes and modifications can be made without departing from the spirit and scope of the present invention.

According to the present invention, a titanium silicide film is formed on a bit line contact formed on a polysilicon pad while a titanium silicide film is not formed on a bit line contact formed on a gate, thereby simultaneously making stable contact in a region having different contact characteristics. It is effective to secure resistance.

In addition, by forming contact pads not only in the cell array region but also in the peripheral circuit region, the thickness of the interlayer insulating layer etched in a subsequent bit line contact etching process is almost the same, thereby facilitating an easy bit line contact etching process.

Claims (3)

In the method of forming a bit line contact of a semiconductor device, Forming a plurality of first and second transistors each having a gate electrode of at least polysilicon / tungsten silicide on a semiconductor substrate in which a cell array region and a peripheral circuit region are defined; Forming a first interlayer insulating film on the semiconductor substrate including the plurality of first transistors and the plurality of second transistors; Etching the first interlayer insulating film to form first and second openings for pad formation exposing a semiconductor substrate between the plurality of first transistors and the plurality of second transistors; Forming polysilicon inside the first and second openings to form first and second conductive pads, respectively; Selectively forming titanium silicide layers on the first and second conductive pads, respectively; Forming a second interlayer insulating film on the resultant; Etching the second interlayer insulating layer to form first, second and third bit line contact holes exposing the silicide layer and the tungsten silicide layer of the second transistor on the first and second conductive pads, respectively; ; And And forming a barrier metal film and a bit line metal film on the bit line contact hole and the second interlayer insulating film. The method of claim 1, And the barrier metal film is formed of any one of TiN, TaN, TiSiN, TaSiN, WN, ZrN and NbN, and has a thickness of about 300 Angstroms to 600 Angstroms. The method of claim 1, And forming a silicide protective layer on the titanium silicide layer, wherein the silicide protective layer is formed of TiN or TiSiN.