KR20030049806A - A fabricating method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of minimizing parasitic capacitance of a word line and losses of a hard mask due to misalignment. CONSTITUTION: A plug(48) is formed to contact a substrate(40) between adjacent gate electrodes(43). An etch stop layer(49) and an insulating layer(50) are sequentially formed on the plug(48). The insulating layer(50) is selectively etched by using fluorine-based gas so as to expose the surface of the etch stop layer(49). An open part(52) is formed to expose the surface of the plug(48) by selectively etching the exposed etch stop layer(49).

Description

Semiconductor device manufacturing method {A FABRICATING METHOD OF SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including a landing plug contact.

Conventional plugs are formed in the vertical direction only at the contact forming site. Meanwhile, another plug for contact with another conductive pattern to be formed on the plug is formed to form a stacked structure of elements for improving the degree of integration. As the size decreases, the density decreases, and the possibility of short circuit due to misalignment increases, resulting in a decrease in process margin. Therefore, a landing plug that can be extended to the contact forming area and the surrounding area to increase the contact margin is mainly used. .

As the high integration of semiconductors is accelerated, the cell layout is changing from the 8F2 method to the 6F2 method. FIG. 1 is a plan view schematically illustrating the cell layout of the 6F2.

Referring to FIG. 1, word lines 'W / L' are arranged in one direction, and bit lines 'B / L' are disposed to intersect the word lines. The bit line 'B / L' is contacted like 'BLC' on the active area, and the storage node contact 'SNC' is also contacted on the active area.

FIG. 2 is a cross-sectional view illustrating a semiconductor device including a landing plug contact formed according to the related art in a structure in which FIG. 1 is cut into A-A 'or B-B', and will be described in detail with reference to the FIG.

A device isolation layer 11 is locally formed on the substrate 10, and a gate electrode pattern including a gate insulating layer 12, a gate electrode 13, and a hard mask 14 is formed on the substrate 10. The spacer 16 is formed in the semiconductor substrate, and an impurity diffusion region 15 such as a source / drain is formed in the substrate 10 between adjacent gate electrode patterns.

A plug 18 is formed through the interlayer insulating film 17 and contacted to the impurity diffusion region by a landing plug contact process. The upper portion of the interlayer insulating film 17 is planarized with the interlayer insulating film 17.

After the landing plug is formed, the interlayer dielectric layer 19 is formed to form the storage node or the bit line, and then the interlayer dielectric layer 19 is selectively etched through the photolithography process for forming the bit line or the storage node pattern. A process of forming the open portion 20 exposing the surface of the plug 18 is performed.

Hereinafter, a problem according to the prior art will be described in detail with reference to FIGS. 1 and 2.

As described above, the cell layout is being changed to 6F2, where F is the smallest graphic dimension and is the smallest unit that can be defined by the photolithography process of exposing and post-etching the photoresist film on the substrate through a mask. to be.

In FIG. 1 and FIG. 2, when the alignment is correctly performed in the photolithography process for the storage node contact or the bit line contact, no problem occurs. However, the misalignment occurs as shown in FIG. When the film 20 is out of the plug 18, an oxide-based insulating film, that is, an interlayer insulating film 17, is formed in the region. Therefore, due to the fast etching characteristic of the oxide film, the portion as shown in FIG. Etching at is excessive.

Therefore, the area where the subsequent bit line or storage node meets the gate electrode 13, for example, the word line, is increased, thereby increasing the parasitic capacitance of the word line. In addition, when the etching for forming the open portion 20, the loss of the hard mask 14 occurs as shown in 'D' of FIG. 2, and if the thickness is increased to compensate for the loss of the hard mask 14, It is burdened during the etching process for forming the hard mask 14 pattern, and it is also burdened in the subsequent landing plug etching process, which is shown in FIGS. 3A and 3B showing plan and cross-sectional photographs illustrating the above-described conventional problem. have.

The present invention proposed to solve the problems of the prior art, a method of manufacturing a semiconductor device that can minimize the loss of the gate hard mask due to misalignment when forming the bit line or storage node contact while minimizing the parasitic capacitance of the word line. To provide that purpose.

1 is a plan view schematically showing the cell layout of 6F2;

FIG. 2 is a cross-sectional view of a semiconductor device including a landing plug contact formed according to the prior art in a structure cut from FIG. 1 to A-A 'or B-B'; FIG.

3A and 3B are plan and cross-sectional photographs showing a conventional problem, respectively,

4A to 4C are cross-sectional views illustrating a semiconductor device manufacturing process according to the present invention.

* Explanation of symbols for the main parts of the drawings

40 substrate 41 device isolation film

42: gate insulating film 43: gate electrode

44 hard mask 45 impurity diffusion region

46: spacer 47, 50: interlayer insulating film

48: plug 49: etch stop film

51: photoresist sheet pattern 52: open part

In order to solve the above problems, the present invention comprises the steps of forming a contact plug in the substrate between the adjacent gate electrode; Sequentially forming an etch stop layer and an insulating layer on the plug; Selectively etching the insulating layer using a fluorine-based gas to stop etching on the surface of the etch stop layer; And forming an open portion for exposing the surface of the plug by etching the etch stop layer by using at least the insulating layer as an etch mask.

The present invention forms an etch stop film between the interlayer insulating film and the plug in order to minimize the loss of the gate electrode due to misalignment of the mask in the patterning process for forming the bit line or storage node, the fluorine-based gas during the etching process to expose the plug After etching the insulating film using the etching, the etching stop film is etched by the technical feature to minimize the loss of the gate hard mask without increasing the gate hard mask thickness.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to enable those skilled in the art to more easily implement the present invention.

4A to 4C are cross-sectional views illustrating a semiconductor device manufacturing process according to an embodiment of the present invention, which will be described below in detail.

First, as shown in FIG. 4A, a device isolation layer 41 is locally formed on a substrate 40 on which various elements for forming a semiconductor device are formed, and then a plurality of gates including polysilicon and tungsten silicide are stacked. An electrode 43, for example, forms a word line.

Specifically, an oxide film-type gate insulating film 42 is formed between the substrate 40 and the gate electrode 43, and a nitride film or the like is formed on the gate electrode 43 to prevent the loss of the gate due to subsequent self-aligned etching or the like. To form the gate hard mask 44.

Here, the gate electrode 43 may further include a single or a mixture of tungsten and aluminum alone or in addition to the above-described polysilicon and tungsten silicide structure, the hard mask 44 is a nitride film, tantalum oxide film or aluminum oxide film. Or the like, or may further include an oxide film doped or an undoped oxide film, respectively.

Subsequently, an impurity diffusion region 45 such as a source / drain junction is formed in the substrate 40 between the gate electrodes 43 by ion implantation or the like, and then an insulating film for spacers of the gate electrode 43 such as a nitride film is formed on the entire surface of the substrate 40. 46) to form a barrier in the subsequent SAC process.

Subsequently, an interlayer insulating film 47 is deposited on the entire surface so as to cover the entire top of the hard mask 44, and then a planarization process such as chemical mechanical polishing (hereinafter referred to as CMP) is performed to perform an interlayer insulating film 47. When the surface is flattened, an insulating film excellent in film flatness, such as a fluidized oxide film, can also be used at this time.

Subsequently, the photoresist pattern is applied through a process such as application and exposure and development of a photoresist on the interlayer insulating film 47 to define a contact portion for forming a plug for plugging a storage node or a bit line to be formed by a subsequent process. After forming (not shown), the landing plug contact selectively exposes the surface of the impurity diffusion region 45 of the substrate 40 on which the plug is to be formed by selectively etching the interlayer insulating layer 47 using the photoresist pattern as an etching mask. Carry out the process.

Subsequently, after the cleaning process is performed to remove the polymer which is a by-product generated during etching, the plug 48 is formed to contact the exposed impurity diffusion region 45 described above, and the plug 48 is formed of amorphous silicon or After the deposition using the tube polysilicon, the planarization process such as CMP or full surface etching may be omitted by planarization with the interlayer insulating layer 47 or by selective epitaxial growth (hereinafter, referred to as SEG). .

Next, as shown in FIG. 4B, the etch stop film 49 and the interlayer insulating film 50 are sequentially formed on the entire surface including the plug 48. The etch stop film 49 may be formed of a nitride film, a tantalum oxide film, or an aluminum oxide film. It is preferable to form a thinner than the interlayer insulating film 50 by using a thin film or the like, so that the sum of the thicknesses of the two layers corresponds to the thickness of a normal interlayer insulating film.

The interlayer insulating film 50 is formed of Tetra Ethyl Ortho Silicate (TEOS), High Temperature Oxidation (HTO) oxide, Medium Temperature Oxidation (MTO) oxide, Undoped Silicate Glass (USG), BoroPhospho Silicate Glass (BPSG), and Phospho Silicate Glass (PSG). By using at least one selected from the group consisting of, the interlayer insulating film 50 and the etch stop film 49 have an etch selectivity.

Next, as shown in FIG. 4C, the interlayer insulating layer 50 and the etch stop layer 49 are selectively etched to form an open portion 52 exposing the surface of the plug 48.

In detail, a photoresist pattern 51 for forming a bit line or a storage node is formed on the interlayer insulating layer 50, so that the photoresist pattern 51 overlaps with the plug 48. Subsequently, the interlayer insulating film 50 is etched using the photoresist pattern 51 as an etch mask. At this time, an etching condition in which a polymer is generated using a fluorine-based gas is used, and the etching process uses the surface of the etch stop film 49. Stop at.

The above-described interlayer insulating film 50 etching process is an etching process for forming a conventional self-aligned contact, and the fluorine-based gas such as C ₄ F ₆ , C ₄ F _8, or C ₅ F _{8 is used} as the stock angle gas, and the etching profile In order to improve the reproducibility of the process and improve the reproducibility of the process, it is preferable to further include a single gas or mixed gas such as CH ₂ F ₂ , Ar or CO,

In the etching process, it is preferable to use MERIE (Magnetically Enhanced Reactive Ion Etching), which is an etching device using permanent magnets or electromagnets.In order to secure a profile of a vertical section, the etching process is performed vertically using a general etching recipe, and then in a self-aligned contact. It can be carried out in a two-step etching process of etching using a recipe to have a slope of.

Subsequently, a cleaning process is performed using a plasma containing O ₂ to remove by-products such as a polymer generated by etching the interlayer insulating film 50.

Subsequently, the photoresist pattern 51 and the interlayer insulating film 50, the bar that forms the opening portion 52 for exposing the plug 48 surface is etched to the etching stop film 49 to an etching mask, CF _4, or the use of CHF ₃ alone or a mixture gas, and may further include O ₂ or Ar here.

Meanwhile, the photoresist pattern 51 may be removed after the etching of the interlayer insulating layer 50, and may be removed by a separate photoresist strip process. The process of etching the interlayer insulating layer 50 and the etching stop layer 49 may be etched. It is preferable to proceed in situ within the same equipment described above.

Although not shown in the drawing, a subsequent process may fill the open part 52 and form a bit line or a storage node contacting the exposed plug 48.

According to the present invention, the etching stop film 49 is additionally formed on the plug 48, and the recipe during the etching process of the interlayer insulating film 50 is performed as a recipe in the self-aligned contact process, and the etching stop film 29 ) Is formed on the planarized structure, and even a thin thickness can provide sufficient etch stop function in the self-aligned contact process, so that the loss of the gate hard mask 44 is as much as 'E', even if misalignment due to contact formation occurs. When the etching stop layer 49 is etched, only the excessive etching occurs.

Accordingly, the present invention can reduce the loss of the hard mask 44 as compared with the prior art, can prevent the electrical short-circuit of the gate electrode and the bit line or storage node without increasing the hard mask thickness, subsequent bit line or storage node It can be seen through the embodiment that the area where the L may be reduced can reduce the parasitic capacitance of the word line.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above can reduce the inter-electrode short circuit and parasitic capacitance when forming a contact such as a bit line, it can be expected to have an excellent effect that can ultimately secure the yield and process margin of the semiconductor device.

Claims (10)

Forming a contact plug in a substrate between neighboring gate electrodes; Sequentially forming an etch stop layer and an insulating layer on the plug; Selectively etching the insulating layer using a fluorine-based gas to stop etching on the surface of the etch stop layer; And Forming an open portion exposing the surface of the plug by etching the etch stop layer using at least the insulating film as an etch mask Semiconductor device manufacturing method comprising a. The method of claim 1, The etch stop layer is a semiconductor device manufacturing method characterized in that it comprises any one of a nitride film, tantalum oxide film or aluminum oxide film. The method of claim 1, The fluorine-based gas is a semiconductor device manufacturing method comprising any one of C ₄ F ₆ , C ₄ F ₈ or C ₅ F ₈ . The method of claim 3, wherein And at least one of CH ₂ F ₂ , Ar, and CO in the fluorine-based gas. The method of claim 1, And etching at least one of CF ₄ or CHF ₃ as a stock angle gas in the etching of the etch stop layer. The method of claim 5, The method of manufacturing a semiconductor device further comprising O ₂ or Ar in the stock corner gas. The method of claim 1, And removing the by-products generated by etching the insulating film using a plasma including O ₂ after etching the insulating film. The method of claim 1, And forming a bit line in contact with the exposed plug after forming the open portion. The method of claim 1, And forming a storage node contacting the exposed plug after forming the open portion. The method of claim 1, And etching the insulating film and etching the etch stop film in-situ in the same chamber.