KR20030049138A - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- KR20030049138A KR20030049138A KR1020010079274A KR20010079274A KR20030049138A KR 20030049138 A KR20030049138 A KR 20030049138A KR 1020010079274 A KR1020010079274 A KR 1020010079274A KR 20010079274 A KR20010079274 A KR 20010079274A KR 20030049138 A KR20030049138 A KR 20030049138A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자 제조 방법에 관한 것으로 특히, 자기정렬콘택(SelfAlign Contact; 이하 SAC이라 함) 형성에 관한 것으로 더욱 상세하게는, 층간절연막 사이에 식각정지막을 이용한 SAC 공정의 마진 개선 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to forming a self-aligned contact (hereinafter referred to as SAC). .
소자의 집적도 향상을 통하여 포토레지스트를 이용한 패턴 형성 공정 자체의 마진과 오버래이의 정확도(Overlay accuracy)를 안정적으로 확보하기가 어렵게 됨에 따라 SAC 공정이 도입되었는 바, SAC 공정은 패턴닝을 함에 있어서 별도의 마스크를 사용하지 않고 이미 증착된 물질을 이용하여 식각을 하는 방식으로 비용 감소에 큰 역할을 하는 것으로, SAC 공정 자체는 여러가지 방법을 사용하고 있으나 대표적인 방법으로는 질화막을 식각방지막으로 사용한다.The SAC process was introduced as it was difficult to stably secure the margin and overlay accuracy of the pattern forming process itself using photoresist by improving the device integration density. It does not use a mask of etched by using an already deposited material to play a big role in reducing the cost, SAC process itself uses a variety of methods, but the typical method uses a nitride film as an etch barrier.
한편, SAC 공정에서 전술한 바와 같이 게이트전극 등의 측벽 또는 상부에 형성되는 질화막을 이용한 식각선택비를 이용하여 식각 공정이 진행되기 때문에 이 질화막들이 이후 공정에서 식각 마진 부족으로 인해 일부 손상될 경우에 이후 공정 진행시 공정 마진이 부족해지며 예컨대, 후속 공정 중 플러그물질 증착 후에 플러그간의 격리(Isolation)를 위한 화학기계적연마(Chemical Mechanical Polishing; 이하 CMP라 함) 공정시 하드마스크를 이용하기 때문에 하드마스크의 두께는 매우 중요하므로, SAC 결함(Fail)이 발생하는 바, 도 1은 전술한 SAC 결함을 도시한 사진으로서, 도시된 'A'와 같이 SAC 결함이 발생함을 알 수 있다.On the other hand, since the etching process is performed using the etching selectivity using the nitride film formed on the sidewall or the top of the gate electrode or the like as described above in the SAC process, if the nitride films are partially damaged due to the lack of etching margin in the subsequent process Since the process margin is insufficient during the process, for example, hard masks are used during the chemical mechanical polishing (CMP) process for isolation between the plugs after the deposition of the plug material during the subsequent process. Since the thickness is very important, the SAC failure (Fail) occurs, Figure 1 is a photograph showing the above-described SAC defect, it can be seen that the SAC defect occurs as shown 'A'.
한편, 전술한 SAC 결함을 방지하기 위해 게이트전극 식각시 하드마스크의 두께를 증가시킬 경우, 하드마스크를 포함한 질화막의 손상을 일부 보상할 수는 있지만 게이트전극 배선 식각시 식각 프로파일은 트랜지스터의 특성에 중요한 영향을 미치기 때문에 게이트전극 식각시 하드마스크의 두께 증대를 통한 하드마스크의 보상은 식각 프로파일의 변형을 가져와 이 방법을 통한 공정 개선에는 한계가 있다.On the other hand, if the thickness of the hard mask is increased during etching of the gate electrode to prevent the aforementioned SAC defect, the damage of the nitride layer including the hard mask may be partially compensated, but the etching profile is important for the characteristics of the transistor during the etching of the gate electrode wiring. As it affects, the compensation of the hard mask by increasing the thickness of the hard mask during etching of the gate electrode has a deformation of the etching profile, and thus the process improvement through this method is limited.
본 발명은 상기한 종래기술의 문제점을 해결하기 위해 제안된 것으로서, 자기정렬콘택 형성시 하드마스크의 손실을 최소화하기에 적합한 반도체 소자 제조 방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object of the present invention is to provide a method for manufacturing a semiconductor device suitable for minimizing the loss of a hard mask when forming a self-aligned contact.
도 1은 종래기술에 따른 SAC 공정시의 결함을 도시한 사진,1 is a photograph showing a defect in the SAC process according to the prior art,
도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체 소자 제조 공정을 도시한 단면도.2A through 2D are cross-sectional views illustrating a semiconductor device manufacturing process in accordance with an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10 : 기판11 : 소자분리막10 substrate 11 device isolation film
12 : 게이트전극13 : 하드마스크12 gate electrode 13: hard mask
14 : 스페이서용 절연막15 : 제1층간절연막14 insulating film for spacer 15 first interlayer insulating film
16 : 식각정지막18 : 제2층간절연막16: etch stop film 18: second interlayer insulating film
19 : 포토레지스트 패턴20 : 콘택홀19: photoresist pattern 20: contact hole
상기의 목적을 달성하기 위해 본 발명은, 이웃하는 다수의 도전패턴이 형성된 기판 상에 평탄화된 제1절연막을 형성하는 단계; 상기 도전패턴과 오버랩되는 상기 제1절연막 상에만 식각정지막을 형성하는 단계; 상기 제1절연막 및 상기 식각정지막 상에 평탄화된 제2절연막을 형성하는 단계; 및 상기 제2절연막과 상기 제1절연막을 선택적으로 식각하여 상기 기판 표면을 노출시키는 콘택홀을 형성하는 단계를 포함하는 반도체 소자 제조 방법을 제공한다.In order to achieve the above object, the present invention comprises the steps of: forming a planarized first insulating film on a substrate on which a plurality of neighboring conductive patterns are formed; Forming an etch stop layer only on the first insulating layer overlapping the conductive pattern; Forming a planarized second insulating layer on the first insulating layer and the etch stop layer; And selectively etching the second insulating layer and the first insulating layer to form a contact hole exposing the surface of the substrate.
본 발명은 게이트전극 형성 후 제1층간절연막을 게이트전극 하드마스크 상부 정도의 높이로 일차적으로 증착하고, 질화막 등의 식각정지막을 연속적으로 증착하고, 하드마스크 상부 보호를 위한 마스크를 이용하여 식각정지막을 선택적으로 식각한 후, 재2층간절연막을 증착하며, 계속해서 SAC 형성용 마스크를 이용하여 콘택홀을 형성함으로써, 하드마스크의 손실없이 SAC 공정을 진행하는 것을 기술적 특징으로 한다.According to the present invention, after the gate electrode is formed, the first interlayer insulating film is first deposited to a height approximately equal to the top of the gate electrode hard mask, the etch stop films such as nitride films are continuously deposited, and the etch stop film is formed by using a mask for protecting the hard mask. After selectively etching, a second interlayer insulating film is deposited, and then a contact hole is formed using a SAC forming mask, thereby performing the SAC process without losing a hard mask.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 상세하게 설명하는 바, 도 2a 내지 도 2d는 본 발명의 일실시예에 따른 반도체 소자의 자기정렬콘택 형성 공정을 도시한 단면도이다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. 2A to 2D are cross-sectional views illustrating a process of forming a self-aligned contact of a semiconductor device according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이 반도체 소자를 이루기 위한 여러 요소가 형성된 기판(10)에 국부적으로 STI(Shallow Trench Isolation) 구조의 소자분리막(11)을 형성한 다음, 기판(10) 상에 이웃하는 다수의 도전패턴(12)을 형성하는 바, 도전패턴은 비트라인 또는 게이트전극 등을 포함하며, 이하에서는 게이트전극을 그 일예로 하여 설명한다.First, as shown in FIG. 2A, a device isolation layer 11 having a shallow trench isolation (STI) structure is locally formed on a substrate 10 on which various elements for forming a semiconductor device are formed. A plurality of conductive patterns 12 are formed, and the conductive patterns include bit lines, gate electrodes, and the like. Hereinafter, the gate electrodes will be described as one example.
구체적으로, 산화막계열의 게이트절연막(도시하지 않음)과 폴리실리콘, 텅스텐 또는 텅스텐 실리사이드 등을 단독 또는 혼합하여 게이트전극용 전도막과 실리콘질화막 또는 실리콘산화질화막 등을 이용하여 1000Å ∼ 3000Å의 두께로 하드마스크(13)를 차례로 증착한 후, 게이트전극 마스크를 이용한 사진식각 공정을 실시하여 게이트전극(12)을 형성한다.Specifically, an oxide-based gate insulating film (not shown) and polysilicon, tungsten, or tungsten silicide may be used alone or mixed to form a hard film having a thickness of 1000 Å to 3000 하여 by using a gate electrode conductive film and a silicon nitride film or silicon oxynitride film. After the mask 13 is sequentially deposited, the gate electrode 12 is formed by performing a photolithography process using the gate electrode mask.
이어서, 게이트전극 측벽을 보호하기 위해 스페이서용 절연막(24)를 형성한다. 이 때, 실리콘질화막 또는 실리콘산화질화막을 이용하여 형성한다.Subsequently, an insulating film 24 for spacers is formed to protect the gate electrode sidewalls. At this time, it is formed using a silicon nitride film or a silicon oxynitride film.
계속해서, 스페이서용 절연막(14) 상에 게이트전극(12) 사이의 스페이스를충분히 채울 수 있을 정도로 제1층간절연막(15)을 형성하는 바, 이 때 고온산화막(HTO), APL(Advanced Planalization Layer) 산화막, SOD(Spin On Dielectric), SOG(Spin On Glass), TEOS(Tetra Ethyl Ortho Silicate), BPSG(Boro Phospho Silicate Glass), PSG(Phospho Silicate Glass) 또는 BSG(Boro Silicate Glass) 등의 막 평탄화 특성이 우수한 물질을 사용하여 2000Å ∼ 10000Å의 두께로 형성한다.Subsequently, a first interlayer insulating film 15 is formed on the spacer insulating film 14 to sufficiently fill the space between the gate electrodes 12. At this time, a high temperature oxide film (HTO) and an advanced planarization layer (APL) are formed. ) Planarization of oxide film, SOD (Spin On Dielectric), SOG (Spin On Glass), TEOS (Tetra Ethyl Ortho Silicate), BPSG (Boro Phospho Silicate Glass), PSG (Phospho Silicate Glass) or BSG (Boro Silicate Glass) It is formed to a thickness of 2000 kPa to 10000 kPa using a material having excellent properties.
이 때, 제1층간절연막(15)은 하드마스크(13) 상부에서 0Å ∼ 1000Å의 두께가 되도록 증착 또는 증착/평탄화 공정을 실시한다.At this time, the first interlayer insulating film 15 is deposited or deposited / planarized to have a thickness of 0 mV to 1000 mV on the hard mask 13.
이어서, 제1층간절연막(15) 상에 50Å ∼ 1000Å의 두께로 식각정지막(16)을 형성하는 바, 이 때 산화막 계열과 식각선택비를 갖는 실리콘질화막 또는 실리콘 산화질화막을 이용한다.Subsequently, an etch stop film 16 is formed on the first interlayer insulating film 15 to a thickness of 50 kV to 1000 kV. At this time, a silicon nitride film or a silicon oxynitride film having an oxide film series and an etching selectivity is used.
다음으로, 도 2b에 도시된 바와 같이 식각정지막(16) 상에 하드마스크 보호를 위한 포토레지스트 패턴(17)을 형성하는 바, 게이트전극(12) 상부와 오버랩되도록 한다.Next, as shown in FIG. 2B, the photoresist pattern 17 for hard mask protection is formed on the etch stop layer 16 to overlap the upper portion of the gate electrode 12.
계속해서, 포토레지스트 패턴(17)을 식각마스크로 해서 식각정지막(16)을 선택적으로 식각하여 제1층간절연막(15)을 노출시킴으로써 게이트전극(12) 즉, 하드마스크(13) 오버랩되는 상부에서 식각정지막(16)이 잔류하도록 한다.Subsequently, the etch stop layer 16 is selectively etched using the photoresist pattern 17 as an etch mask to expose the first interlayer insulating layer 15 to overlap the gate electrode 12, that is, the hard mask 13. The etch stop layer 16 remains at.
다음으로, 도 2c에 도시된 바와 같이 포토레지스트 패턴(17)을 제거한 다음, 노출된 제1층간절연막(15) 즉, 식각정지막(16) 사이의 오픈부(B)를 충분히 매립할 수 있을 정도로 제2층간절연막(18)을 형성하는 바, 이 때 고온산화막, APL 산화막,SOD, SOG, TEOS, BPSG, PSG 또는 BSG 등의 막 평탄화 특성이 우수한 물질을 사용하여 1000Å ∼ 20000Å의 두께로 형성한 다음, 주변영역과 셀영역의 단차를 줄이기 위해 CMP 공정을 실시한다.Next, as shown in FIG. 2C, after the photoresist pattern 17 is removed, the open portion B between the exposed first interlayer insulating layer 15, that is, the etch stop layer 16, may be sufficiently filled. The second interlayer dielectric film 18 is formed to a thickness of 1000 kPa to 20,000 kPa using a material having excellent film planarization characteristics such as high temperature oxide film, APL oxide film, SOD, SOG, TEOS, BPSG, PSG or BSG. Next, a CMP process is performed to reduce the step difference between the peripheral region and the cell region.
한편, 제1 및 제2 층간절연막(15, 18)의 막 치밀화 및 단차피복성 등을 향상시키기 위해 실시하는 열처리 공정은 제2층간절연막(18) 형성 후 실시한다.On the other hand, the heat treatment process is performed after the formation of the second interlayer insulating film 18 to improve the film density and the step coverage of the first and second interlayer insulating films 15 and 18.
다음으로, 도 2d에 도시된 바와 같이 제2층간절연막(18) 상에 SAC 형성을 위한 포토레지스트 패턴(19)을 형성한 다음, 이를 식각마스크로 해서 제2층간절연막(18)과 제1층간절연막(15) 및 스페이서용 절연막(14)를 식각하여 기판 표면을 노출시키는 콘택홀(20)을 형성한다.Next, as shown in FIG. 2D, a photoresist pattern 19 for forming SAC is formed on the second interlayer insulating layer 18, and then, as an etching mask, the second interlayer insulating layer 18 and the first layer are interposed therebetween. The insulating film 15 and the spacer insulating film 14 are etched to form a contact hole 20 exposing the substrate surface.
이 때, 게이트전극(12) 상부에는 식각정지막(16)이 존재하므로 전술한 식각공정에서 하드마스크(13)의 손실을 방지할 수 있다.At this time, since the etch stop layer 16 is present on the gate electrode 12, it is possible to prevent the loss of the hard mask 13 in the above-described etching process.
이어서, 도면에 도시되지는 않았지만 폴리실리콘 등을 플러그 물질을 증착한 후, CMP 공정을 실시하거나, 선택적 에피택셜성장(Selective Epitaxial Growth; 이하 SEG라 함)법을 이용하여 플러그를 형성한다.Subsequently, although not shown in the drawings, a plug material is deposited on polysilicon or the like, and then a plug is formed using a CMP process or a selective epitaxial growth (SEG) method.
전술한 본 발명은, 하드마스크 보호를 위한 추가의 마스크 공정을 통해 하드마스크와 오버랩되는 상부에 질화막계열의 식각정지막을 형성하여 SAC 형성을 위한 식각 공정시 하드마스크의 손실을 방지함으로써, 게이트전극의 손실 및 후속 공정의 마진을 높일 수 있음을 실시예를 통해 알아 보았다.The above-described present invention forms an etch stop layer of a nitride film layer on an upper portion overlapping with the hard mask through an additional mask process for protecting the hard mask, thereby preventing the loss of the hard mask during the etching process for forming the SAC. It has been found through the examples that the loss and the margin of subsequent processes can be increased.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
한편, 전술한 실시예서의 콘택홀 형성용 마스크는 홀형(Hole-type) 또는 라인형(Line-type) 등 다양하게 적용이 가능하다.On the other hand, the contact hole forming mask in the above-described embodiment can be applied in various ways, such as hole-type (Line-type).
상술한 바와 같은 본 발명은, 콘택 형성시 게이트전극 하드마스크의 손실을 방지하여 게이트전극의 손실을 방지할 수 있을 뿐만아니라, 후속 공정 마진을 증가시킴으로써, 궁극적으로 반도체 소자의 수율을 향상시킬 수 있는 탁월한 효과를 기대할 수 있다.As described above, the present invention can not only prevent the loss of the gate electrode hard mask during contact formation, thereby preventing the loss of the gate electrode, but also increase the subsequent process margin, thereby ultimately improving the yield of the semiconductor device. Excellent effect can be expected.
Claims (7)
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| US7365000B2 (en) | 2003-11-21 | 2008-04-29 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
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| US7365000B2 (en) | 2003-11-21 | 2008-04-29 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device |
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