KR20040057512A - Method of manufacturing flash memory device - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory device is provided to improve integration degree and capability by improving the mismatch of a floating gate. CONSTITUTION: A gate oxide layer(22) and a first floating gate(23a) are formed on an active region of a semiconductor substrate(21). An isolation trench(24) is formed by etching the exposed substrate. An isolation layer(25) is filled in the trench. A second floating gate(23b) is formed at the side of the first floating gate to overlap the isolation layer. A dielectric film(26) and a control gate(27) are then formed on the floating gate.

Description

Flash memory device manufacturing method {Method of manufacturing flash memory device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a flash memory device capable of improving mismatch characteristics of a floating gate in a NAND flash memory device.

In general, NAND flash memory devices using a self-aligned device isolation scheme require a minimum area to prevent mismatch of floating gates.

1A and 1B are cross-sectional views of a device for explaining a conventional NAND flash memory device manufacturing method using a self-aligned device isolation method.

Referring to FIG. 1A, a gate oxide film 12 and a first floating gate 13a are formed in an active region of the semiconductor substrate 11. In the self-aligned etching process using the first floating gate 13a, the exposed portion of the semiconductor substrate 11 is etched to a predetermined depth to form the isolation trench 14 for device isolation. After thickly depositing a device isolation insulating material over the entire structure including the trench 14, a chemical mechanical polishing process is performed until the first floating gate 13a is exposed to fill the trench 14 with the insulating material. As a result, the device isolation layer 15 is formed.

Referring to FIG. 1B, the second floating gate 13b is formed on the first floating gate 13a to increase the contact area between the floating gate and the control gate so as to improve read and write operation characteristics of the device. As a result, the floating gate 13 including the first and second floating gates 13a and 13b is formed. The thickness of the second floating gate 13b is determined according to the design rule, and the second floating gate 13b is formed so that the line width L1 with the neighboring second floating gate 13b is minimized to the extent that the resolution capability of the exposure equipment allows. As the line width L1 becomes narrower, the overlap width L2 between the element isolation film 15 and the second floating gate 13b becomes wider. Thereafter, a dielectric film (not shown) and a control gate (not shown) are formed to manufacture a NAND flash memory device.

As semiconductor devices become more integrated, the area occupied by unit devices is decreasing. In order to improve the read and write characteristics of the NAND flash memory device, the contact area between the floating gate and the control gate should be increased as much as possible. For this purpose, the line width L1 between the neighboring second floating gates 13b should be as narrow as possible. . Since the line width L1 depends on the resolution capability of the exposure equipment, a limit is followed, and this limit is directly related to the overlap length L2 between the element isolation film 15 and the second floating gate 13b. That is, as the line width L2 between the second floating gates 13b is narrower, the overlap width L2 becomes wider, which means that the more the exposure equipment having excellent resolution capability, the wider the overlap width L2 can be. . 2 is a graph showing the relationship between the overlap width L2 indicating the mismatch improvement ability according to the minimum line width L1 indicating the performance of the exposure equipment. The size of the overlap width L2 can ideally be obtained in the form of "4.81E5 + 0.32 x minimum line width L1", but is substantially obtained in the form of "0.04 + 0.2246 x minimum line width L1". As can be seen from FIG. 2, the overlap width (L2) related to mismatching characteristics is improved even if the minimum line width capability is improved by using expensive equipment (equipment having excellent resolution capability) by the formula of "0.04 + 0.2246 x minimum line width (L1)". Can only be improved by 22%. For example, even with equipment with 0.12 μm technology, mismatching characteristics should consider 65 nm. Since the size of the unit device is increased by twice the size of the overlap width (L2), when the overlap width (L2) is 65nm, the size of the unit device must be made larger by 130nm. In other words, when using a device capable of forming a line width of 120 nm, the ideal minimum unit device size is 240 nm × 240 nm, but the size of the actual device is (130 nm + 240 nm) × 240 nm. do. As described above, in the conventional method, there is a limit to reducing the size of the unit device by the size necessary to prevent mismatch of the floating gate in the NAND flash memory device using the self-aligning device isolation method, making it difficult to realize high integration of the device.

Accordingly, the present invention provides a flash memory device capable of realizing not only the performance of the device but also the high integration of the device by improving the mismatching characteristics of the floating gate in the NAND flash memory device without greatly depending on the resolution capability of the exposure equipment. The purpose is to provide a method.

1A and 1B are cross-sectional views of a device for explaining a conventional NAND flash memory device manufacturing method.

2 is a graph showing a relationship between overlapping widths indicating mismatch improvement capability according to a minimum line width indicating performance of exposure equipment.

3A to 3C are cross-sectional views of devices for explaining a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11, 21: semiconductor substrate 12, 22: gate oxide film

13, 23: floating gate 13a, 23a: first floating gate

13b, 23b: second floating gate 14, 24: trench

15, 25: device isolation layer 26: dielectric film

27: control gate

In the flash memory device manufacturing method according to the embodiment of the present invention for achieving this object is formed a gate oxide film and a first floating gate in the active region of the semiconductor substrate, and etching the exposed portion of the semiconductor substrate to trench isolation device Forming a device isolation film by filling the trench with an insulating material for isolating the device, forming a second floating gate overlapping the device isolation film on the side of the first floating gate, and forming a dielectric film on the first and second floating gates. This is done by forming a control gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, and to those skilled in the art the scope of the invention It is provided for complete information.

3A to 3C are cross-sectional views of devices for explaining a method of manufacturing a NAND flash memory device according to an embodiment of the present invention using a self-aligned device isolation method.

Referring to FIG. 3A, a gate oxide film 22 and a first floating gate 23a are formed in an active region of the semiconductor substrate 21. In the self-aligned etching process using the first floating gate 23a as an etching mask, the exposed portion of the semiconductor substrate 21 is etched to a predetermined depth to form the device isolation trench 24. After thickly depositing an insulating material for isolation of the device on the entire structure including the trench 24, the chemical mechanical polishing process and the etching process may be sequentially performed, but the etching process may be performed at least until the gate oxide layer 22 is not exposed. A portion of the trench 24 is filled with an insulating material, thereby forming the device isolation layer 25.

In the above description, the first floating gate 23a is formed by one deposition process and one patterning process without being formed by dividing the first floating gate 13a and the second floating gate 13b unlike the conventional art. Assuming that the device manufactured by the method according to the embodiment has the same design rules as the device manufactured by the aforementioned conventional method, the thickness of the first floating gate 23a is lost by the chemical mechanical polishing process and the etching process. It is formed to be thicker than the thickness of the conventional floating gate 13 in consideration of. That is, the first floating gate 23a is formed thicker than the thickness set in the design rule of the device. The etching step performed after the polishing step may be either a wet method or a dry method.

Referring to FIG. 3B, an element overlapped with the device isolation layer 25 on the side of the first floating gate 23a to increase the contact area between the floating gate and the control gate so as to improve read and write operation characteristics of the device. The second floating gate 23b is formed, whereby a floating gate 23 composed of the first and second floating gates 23a and 23b is formed.

In the above, the second floating gate 23b is formed by depositing a gate material such as polysilicon on the entire structure including the first floating gate 23a, and then spacers on the side of the first floating gate 23a by a spacer etching process. It is formed in the form. In order to maximize the contact area between the floating gate and the control gate, the thickness T of the spacer-type second floating gate 23b should be less than 1/2 of the line width between the neighboring first floating gates 23a. It is made smaller than twice the thickness of the dielectric film formed by the subsequent process. In this way, the additional contact area between the floating gate and the control gate is 2πT / 4-T = 0.57T.

Referring to FIG. 3C, the NAND flash memory device of the present invention is manufactured by forming the dielectric film 26 on the entire structure including the floating gate 23 and the control gate 27 on the dielectric film 26. .

As described above, the NAND flash memory device using the self-aligned device isolation method of the present invention forms a part of the floating gate overlapping the device isolation layer by a spacer etching process rather than a patterning process using exposure equipment, so that misalignment of the floating gate is performed. By improving the characteristics, not only the performance of the device but also high integration of the device can be realized.

Claims (7)

Forming a gate oxide film and a first floating gate in an active region of the semiconductor substrate; Etching the exposed portion of the semiconductor substrate to form a device isolation trench; Forming a device isolation layer by filling the trench with an insulating material for device isolation; Forming a second floating gate on the side of the first floating gate, the second floating gate overlapping the device isolation layer; And And forming a dielectric film and a control gate on the first and second floating gates. The method of claim 1, And the first floating gate is deposited to be thicker than a thickness set in a device design rule during an initial deposition process. The method of claim 1, The device isolation trench is formed by a self-aligned etching process using the first floating gate as an etching mask. The method of claim 1, The device isolation layer is formed by depositing a thick insulating material on the entire structure including the trench, followed by a chemical mechanical polishing process and an etching process sequentially. The method of claim 4, wherein The etching process may be performed by a wet method or a dry method until at least a point where the gate oxide film is not exposed. The method of claim 1, And the second floating gate is formed in the form of a spacer on the side of the first floating gate. The method according to claim 1 or 6, And the size of the second floating gate is less than or equal to 1/2 of the line width between neighboring first floating gates, but smaller than twice the thickness of the dielectric film.