KR20020000466A - Method of manufacturing a flash memory cell - Google Patents

Abstract

PURPOSE: A method for manufacturing a flash memory cell is provided to reduce a cell size when the same design rule is used, by forming an isolation layer of a minimum design rule and by forming a spacer on the sidewall of a floating gate after the floating gate not overlapping the isolation layer is formed. CONSTITUTION: An isolation layer(22) is formed in a predetermined region of a semiconductor substrate(21). A tunnel oxide layer(23) and the first polysilicon layer(24) are sequentially formed on the resultant structure, and are patterned to form a floating gate. A spacer(25) is formed on the sidewall of the floating gate. A dielectric layer(26) and the second polysilicon layer(27) are formed on the resultant structure, and are patterned to form a control gate.

Description

Method of manufacturing a flash memory cell

The present invention relates to a method of manufacturing a flash memory cell, and in particular, a device isolation layer is formed with a minimum design rule, and a spacer is formed on the sidewall of the floating gate after the floating gate is formed so as not to overlap with the device isolation layer. A method of manufacturing a flash memory cell that can reduce the cell size.

1 is a cross-sectional view of an element for explaining a method of manufacturing a conventional flash memory cell, which is a cross-sectional view of an ETOX cell.

An isolation layer 12 is formed on the semiconductor substrate 11 by a trench type or a LOCOS process. The tunnel oxide film 13 and the first polysilicon film 14 are sequentially formed on the entire structure. The first polysilicon layer 14 and the tunnel oxide layer 13 are patterned by a lithography process and an etching process using a floating gate mask to form a floating gate. The floating gate formed by patterning the first polysilicon film 14 and the tunnel oxide film 13 is formed to overlap a predetermined portion with the device isolation film 12. The dielectric layer 15 and the second polysilicon layer 16 are formed on the entire structure, and then patterned by a lithography process and an etching process using a control gate mask to form a control gate.

However, in the flash memory cell manufactured by the above process, as the device is highly integrated, the device isolation layer is formed with the minimum design rule, and the floating gate is also formed with the minimum design rule. As a result, misalignment occurs during the lithography process for forming the floating gate. The second polysilicon film deposited to form the control gate in the misalignment state comes into contact with the semiconductor substrate (part denoted by A in FIG. 1), which causes an error in cell operation. In order to prevent such misalignment, when the floating gate is applied as the minimum design rule, the device isolation layer should be formed larger than this. However, as the size of the device isolation film increases, the cell size increases.

An object of the present invention is to provide a method of manufacturing a flash memory cell that can prevent the control gate from contacting the semiconductor substrate to prevent malfunction of the cell.

Another object of the present invention is to provide a method of manufacturing a flash memory cell capable of forming a floating gate with a minimum design rule without increasing the cell size.

Another object of the present invention is to provide a method of manufacturing a flash memory cell in which a device isolation layer is formed with a minimum design rule so that the floating gate does not overlap with the device isolation layer.

1 is a cross-sectional view of an element for explaining a method of manufacturing a conventional flash memory cell.

2 (a) to 2 (c) are cross-sectional views of devices sequentially shown for explaining a method of manufacturing a flash memory cell according to the present invention.

<Explanation of symbols for the main parts of the drawings>

11 and 21: semiconductor substrate 12 and 22: device isolation film

13 and 23: tunnel oxide film 14 and 24: first polysilicon film

15 and 26: dielectric film 16 and 27: second polysilicon film

25: spacer

In the method of manufacturing a flash memory cell according to the present invention, a device isolation film is formed in a predetermined region on a semiconductor substrate, and a tunnel oxide film and a first polysilicon film are sequentially formed on an entire structure, and then patterned so as not to overlap the device isolation film. Forming a floating gate, forming a spacer on the sidewall of the floating gate, and forming a dielectric film and a second polysilicon film on the entire structure and then patterning the control gate to form a control gate. .

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory cell according to the present invention.

Referring to FIG. 2A, the device isolation layer 22 is formed in a predetermined region on the semiconductor substrate 21. The device isolation layer 22 may be formed by a minimum design rule, may be formed in a trench shape, and may be formed by a LOCOS method. The tunnel oxide film 23 and the first polysilicon film 24 are sequentially formed on the entire structure. The first polysilicon layer 24 and the tunnel oxide layer 23 are patterned by a lithography process and an etching process using a floating gate mask to form a floating gate. The floating gate is formed so as not to overlap the device isolation layer 22. That is, the spacing between the floating gates is formed larger than the minimum design rule.

FIG. 2B is a cross-sectional view illustrating a spacer 25 formed on a sidewall of a floating gate by performing an entire surface etching process after an insulating film is formed over an entire structure.

Referring to FIG. 2C, a dielectric film 26 is formed over the entire structure, and a second polysilicon film 27 is formed. The second polysilicon layer 27 and the dielectric layer 26 are patterned by a lithography process and an etching process using a control gate mask to form a control gate.

As described above, according to the present invention, since the device isolation layer is formed with the minimum design rule, the floating gate is formed so as not to overlap the device isolation layer, and the spacer is formed on the sidewall of the floating gate, the cell size can be reduced compared to the case where the same design rule is applied. .

Claims (2)

Forming an isolation layer in a predetermined region on the semiconductor substrate, A tunnel oxide film and a first polysilicon film are sequentially formed on the entire structure and then patterned to form a floating gate; Forming a spacer on sidewalls of the floating gate; And forming a control gate after the dielectric film and the second polysilicon film are formed over the entire structure, thereby forming a control gate. The method of claim 1, wherein the floating gate is formed so as not to overlap the device isolation layer.